Mercurial > repos > blastem
annotate m68k_to_x86.c @ 559:6b248602ab84
blastem builds and almost works on OS X now
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Tue, 17 Jun 2014 01:50:29 -0400 |
| parents | dc9f178085a0 |
| children | f9431cb3a39c |
| rev | line source |
|---|---|
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "gen_x86.h" |
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7 #include "m68k_to_x86.h" |
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8 #include "68kinst.h" |
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9 #include "mem.h" |
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10 #include "backend.h" |
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11 #include <stdio.h> |
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12 #include <stddef.h> |
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13 #include <stdlib.h> |
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14 #include <string.h> |
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15 |
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16 #define BUS 4 |
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17 #define PREDEC_PENALTY 2 |
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18 |
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19 #define CYCLES RAX |
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20 #define LIMIT RBP |
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21 #define CONTEXT RSI |
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22 #define SCRATCH1 RCX |
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23 |
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24 #ifdef X86_64 |
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25 #define SCRATCH2 RDI |
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26 #else |
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27 #define SCRATCH2 RBX |
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28 #endif |
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29 |
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30 enum { |
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31 FLAG_X, |
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32 FLAG_N, |
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33 FLAG_Z, |
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34 FLAG_V, |
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35 FLAG_C |
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36 }; |
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37 |
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Implement MULU/MULS and DIVU/DIVS
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38 char disasm_buf[1024]; |
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39 |
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40 m68k_context * sync_components(m68k_context * context, uint32_t address); |
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41 |
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42 extern void bcd_add() asm("bcd_add"); |
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43 extern void bcd_sub() asm("bcd_sub"); |
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44 |
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45 void m68k_invalid(uint32_t address, m68k_context * context) |
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46 { |
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47 printf("Invalid instruction at %X\n", address); |
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48 exit(1); |
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49 } |
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50 |
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51 code_ptr cycles(code_ptr dst, uint32_t num) |
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52 { |
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53 dst = add_ir(dst, num, CYCLES, SZ_D); |
| 118 | 54 return dst; |
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55 } |
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56 |
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57 code_ptr check_cycles_int(code_ptr dst, uint32_t address, x86_68k_options * opts) |
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58 { |
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59 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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60 code_ptr jmp_off = dst+1; |
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61 dst = jcc(dst, CC_NC, dst + 7); |
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62 dst = mov_ir(dst, address, SCRATCH1, SZ_D); |
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63 dst = call(dst, opts->gen.handle_cycle_limit_int); |
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64 *jmp_off = dst - (jmp_off+1); |
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65 return dst; |
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66 } |
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67 |
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68 code_ptr check_cycles(code_ptr dst, cpu_options * opts) |
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69 { |
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70 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
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71 code_ptr jmp_off = dst+1; |
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72 dst = jcc(dst, CC_NC, dst + 7); |
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73 dst = call(dst, opts->handle_cycle_limit); |
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74 *jmp_off = dst - (jmp_off+1); |
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75 return dst; |
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76 } |
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77 |
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78 code_ptr set_flag(code_ptr dst, uint8_t val, uint8_t flag, x86_68k_options * opts) |
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79 { |
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80 if (opts->flag_regs[flag] >= 0) { |
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81 dst = mov_ir(dst, val, opts->flag_regs[flag], SZ_B); |
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82 } else { |
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83 int8_t offset = offsetof(m68k_context, flags) + flag; |
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84 if (offset) { |
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85 dst = mov_irdisp8(dst, val, CONTEXT, offset, SZ_B); |
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86 } else { |
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87 dst = mov_irind(dst, val, CONTEXT, SZ_B); |
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88 } |
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89 } |
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90 |
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91 return dst; |
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92 } |
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93 |
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94 code_ptr set_flag_cond(code_ptr dst, uint8_t cond, uint8_t flag, x86_68k_options *opts) |
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95 { |
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96 if (opts->flag_regs[flag] >= 0) { |
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97 dst = setcc_r(dst, cond, opts->flag_regs[flag]); |
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98 } else { |
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99 int8_t offset = offsetof(m68k_context, flags) + flag; |
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100 if (offset) { |
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101 dst = setcc_rdisp8(dst, cond, CONTEXT, offset); |
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102 } else { |
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103 dst = setcc_rind(dst, cond, CONTEXT); |
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104 } |
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105 } |
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106 |
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107 return dst; |
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108 } |
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109 |
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110 code_ptr check_flag(code_ptr dst, uint8_t flag, x86_68k_options *opts) |
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111 { |
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112 if (opts->flag_regs[flag] >= 0) { |
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113 dst = cmp_ir(dst, 0, opts->flag_regs[flag], SZ_B); |
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114 } else { |
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115 dst = cmp_irdisp8(dst, 0, CONTEXT, offsetof(m68k_context, flags) + flag, SZ_B); |
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116 } |
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117 return dst; |
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118 } |
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119 |
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120 code_ptr flag_to_reg(code_ptr dst, uint8_t flag, uint8_t reg, x86_68k_options *opts) |
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121 { |
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122 if (opts->flag_regs[flag] >= 0) { |
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123 dst = mov_rr(dst, opts->flag_regs[flag], reg, SZ_B); |
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124 } else { |
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125 int8_t offset = offsetof(m68k_context, flags) + flag; |
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126 if (offset) { |
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127 dst = mov_rdisp8r(dst, CONTEXT, offset, reg, SZ_B); |
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128 } else { |
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129 dst = mov_rindr(dst, CONTEXT, reg, SZ_B); |
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130 } |
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131 } |
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132 return dst; |
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133 } |
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134 |
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135 code_ptr reg_to_flag(code_ptr dst, uint8_t flag, uint8_t reg, x86_68k_options *opts) |
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136 { |
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137 if (opts->flag_regs[flag] >= 0) { |
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138 dst = mov_rr(dst, reg, opts->flag_regs[flag], SZ_B); |
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139 } else { |
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140 int8_t offset = offsetof(m68k_context, flags) + flag; |
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141 if (offset) { |
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142 dst = mov_rrdisp8(dst, reg, CONTEXT, offset, SZ_B); |
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143 } else { |
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144 dst = mov_rrind(dst, reg, CONTEXT, SZ_B); |
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145 } |
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146 } |
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147 return dst; |
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148 } |
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149 |
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150 code_ptr flag_to_flag(code_ptr dst, uint8_t flag1, uint8_t flag2, x86_68k_options *opts) |
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151 { |
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152 if (opts->flag_regs[flag1] >= 0 && opts->flag_regs[flag2] >= 0) { |
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153 dst = mov_rr(dst, opts->flag_regs[flag1], opts->flag_regs[flag2], SZ_B); |
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154 } else if(opts->flag_regs[flag1] >= 0) { |
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155 dst = mov_rrdisp8(dst, opts->flag_regs[flag1], CONTEXT, offsetof(m68k_context, flags) + flag2, SZ_B); |
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156 } else if (opts->flag_regs[flag2] >= 0) { |
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157 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + flag1, opts->flag_regs[flag2], SZ_B); |
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158 } else { |
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159 dst = push_r(dst, SCRATCH1); |
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160 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + flag1, SCRATCH1, SZ_B); |
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161 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, flags) + flag2, SZ_B); |
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162 dst = pop_r(dst, SCRATCH1); |
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163 } |
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164 return dst; |
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165 } |
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166 |
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167 code_ptr flag_to_carry(code_ptr dst, uint8_t flag, x86_68k_options * opts) |
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168 { |
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169 if (opts->flag_regs[flag] >= 0) { |
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170 dst = bt_ir(dst, 0, opts->flag_regs[flag], SZ_B); |
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171 } else { |
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172 dst = bt_irdisp8(dst, 0, CONTEXT, offsetof(m68k_context, flags) + flag, SZ_B); |
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173 } |
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174 return dst; |
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175 } |
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176 |
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177 code_ptr or_flag_to_reg(code_ptr dst, uint8_t flag, uint8_t reg, x86_68k_options *opts) |
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178 { |
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179 if (opts->flag_regs[flag] >= 0) { |
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180 dst = or_rr(dst, opts->flag_regs[flag], reg, SZ_B); |
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181 } else { |
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182 dst = or_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + flag, reg, SZ_B); |
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183 } |
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184 return dst; |
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185 } |
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186 |
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187 code_ptr xor_flag_to_reg(code_ptr dst, uint8_t flag, uint8_t reg, x86_68k_options *opts) |
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188 { |
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189 if (opts->flag_regs[flag] >= 0) { |
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190 dst = xor_rr(dst, opts->flag_regs[flag], reg, SZ_B); |
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191 } else { |
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192 dst = xor_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + flag, reg, SZ_B); |
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193 } |
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194 return dst; |
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195 } |
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196 |
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197 code_ptr xor_flag(code_ptr dst, uint8_t val, uint8_t flag, x86_68k_options *opts) |
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198 { |
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199 if (opts->flag_regs[flag] >= 0) { |
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200 dst = xor_ir(dst, val, opts->flag_regs[flag], SZ_B); |
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201 } else { |
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202 dst = xor_irdisp8(dst, val, CONTEXT, offsetof(m68k_context, flags) + flag, SZ_B); |
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203 } |
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204 return dst; |
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205 } |
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206 |
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207 code_ptr cmp_flags(code_ptr dst, uint8_t flag1, uint8_t flag2, x86_68k_options *opts) |
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208 { |
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209 if (opts->flag_regs[flag1] >= 0 && opts->flag_regs[flag2] >= 0) { |
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210 dst = cmp_rr(dst, opts->flag_regs[flag1], opts->flag_regs[flag2], SZ_B); |
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211 } else if(opts->flag_regs[flag1] >= 0 || opts->flag_regs[flag2] >= 0) { |
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212 if (opts->flag_regs[flag2] >= 0) { |
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213 uint8_t tmp = flag1; |
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214 flag1 = flag2; |
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215 flag2 = tmp; |
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216 } |
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217 dst = cmp_rrdisp8(dst, opts->flag_regs[flag1], CONTEXT, offsetof(m68k_context, flags) + flag2, SZ_B); |
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218 } else { |
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219 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + flag1, SCRATCH1, SZ_B); |
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220 dst = cmp_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, flags) + flag2, SZ_B); |
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221 } |
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222 return dst; |
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Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
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223 } |
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224 |
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225 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) |
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226 { |
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227 if (op->addr_mode == MODE_REG) { |
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228 return opts->dregs[op->params.regs.pri]; |
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229 } |
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230 if (op->addr_mode == MODE_AREG) { |
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231 return opts->aregs[op->params.regs.pri]; |
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232 } |
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233 return -1; |
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234 } |
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235 |
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236 //must be called with an m68k_op_info that uses a register |
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237 size_t reg_offset(m68k_op_info *op) |
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238 { |
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239 if (op->addr_mode == MODE_REG) { |
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240 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri; |
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241 } |
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242 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri; |
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243 } |
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244 |
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245 void print_regs_exit(m68k_context * context) |
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246 { |
| 207 | 247 printf("XNZVC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]); |
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248 for (int i = 0; i < 8; i++) { |
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249 printf("d%d: %X\n", i, context->dregs[i]); |
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250 } |
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251 for (int i = 0; i < 8; i++) { |
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252 printf("a%d: %X\n", i, context->aregs[i]); |
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253 } |
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254 exit(0); |
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255 } |
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256 |
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558
dc9f178085a0
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257 code_ptr translate_m68k_src(m68kinst * inst, x86_ea * ea, code_ptr out, x86_68k_options * opts) |
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258 { |
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259 int8_t reg = native_reg(&(inst->src), opts); |
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260 uint8_t sec_reg; |
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261 int32_t dec_amount,inc_amount; |
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262 if (reg >= 0) { |
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263 ea->mode = MODE_REG_DIRECT; |
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264 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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265 out = movsx_rr(out, reg, SCRATCH1, SZ_W, SZ_D); |
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266 ea->base = SCRATCH1; |
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267 } else { |
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268 ea->base = reg; |
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269 } |
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270 return out; |
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271 } |
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272 switch (inst->src.addr_mode) |
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273 { |
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274 case MODE_REG: |
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275 case MODE_AREG: |
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276 //We only get one memory parameter, so if the dst operand is a register in memory, |
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277 //we need to copy this to a temp register first |
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278 reg = native_reg(&(inst->dst), opts); |
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279 if (reg >= 0 || inst->dst.addr_mode == MODE_UNUSED || !(inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) |
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280 || inst->op == M68K_EXG) { |
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281 |
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282 ea->mode = MODE_REG_DISPLACE8; |
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283 ea->base = CONTEXT; |
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284 ea->disp = reg_offset(&(inst->src)); |
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285 } else { |
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286 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
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287 out = movsx_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_W, SZ_D); |
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288 } else { |
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289 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size); |
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290 } |
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291 ea->mode = MODE_REG_DIRECT; |
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292 ea->base = SCRATCH1; |
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293 //we're explicitly handling the areg dest here, so we exit immediately |
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294 return out; |
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295 } |
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296 break; |
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297 case MODE_AREG_PREDEC: |
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216
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298 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 :1)); |
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299 out = cycles(out, PREDEC_PENALTY); |
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300 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
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301 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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302 } else { |
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303 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
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304 } |
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305 case MODE_AREG_INDIRECT: |
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306 case MODE_AREG_POSTINC: |
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307 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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308 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
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309 } else { |
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310 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
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311 } |
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312 switch (inst->extra.size) |
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313 { |
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314 case OPSIZE_BYTE: |
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315 out = call(out, opts->read_8); |
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316 break; |
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317 case OPSIZE_WORD: |
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318 out = call(out, opts->read_16); |
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319 break; |
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320 case OPSIZE_LONG: |
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321 out = call(out, opts->read_32); |
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322 break; |
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323 } |
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324 |
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325 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
|
183
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326 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->src.params.regs.pri == 7 ? 2 : 1)); |
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327 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
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328 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); |
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329 } else { |
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330 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
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14
diff
changeset
|
331 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
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14
diff
changeset
|
332 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
333 ea->mode = MODE_REG_DIRECT; |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
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183
diff
changeset
|
334 ea->base = (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? SCRATCH2 : SCRATCH1; |
|
18
3e7bfde7606e
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parents:
14
diff
changeset
|
335 break; |
|
71
f80fa1776507
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70
diff
changeset
|
336 case MODE_AREG_DISPLACE: |
|
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70
diff
changeset
|
337 out = cycles(out, BUS); |
|
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Implement more instructions and address modes
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parents:
70
diff
changeset
|
338 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
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70
diff
changeset
|
339 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
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70
diff
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|
340 } else { |
|
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70
diff
changeset
|
341 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
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70
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|
342 } |
|
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70
diff
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|
343 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
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Implement more instructions and address modes
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70
diff
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|
344 switch (inst->extra.size) |
|
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70
diff
changeset
|
345 { |
|
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70
diff
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|
346 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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324
diff
changeset
|
347 out = call(out, opts->read_8); |
|
71
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70
diff
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|
348 break; |
|
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diff
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|
349 case OPSIZE_WORD: |
|
343
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324
diff
changeset
|
350 out = call(out, opts->read_16); |
|
71
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70
diff
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|
351 break; |
|
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70
diff
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|
352 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
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324
diff
changeset
|
353 out = call(out, opts->read_32); |
|
71
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70
diff
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|
354 break; |
|
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70
diff
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|
355 } |
|
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|
356 ea->mode = MODE_REG_DIRECT; |
|
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diff
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|
357 ea->base = SCRATCH1; |
|
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|
358 break; |
|
81
6d231dbe75ab
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78
diff
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|
359 case MODE_AREG_INDEX_DISP8: |
|
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78
diff
changeset
|
360 out = cycles(out, 6); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
361 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
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diff
changeset
|
362 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
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78
diff
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|
363 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
364 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
365 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
366 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
6d231dbe75ab
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78
diff
changeset
|
367 if (inst->src.params.regs.sec & 1) { |
|
6d231dbe75ab
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Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
368 if (inst->src.params.regs.sec & 0x10) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
369 if (opts->aregs[sec_reg] >= 0) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
370 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
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Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
371 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
372 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
6d231dbe75ab
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78
diff
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|
373 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
374 } else { |
|
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Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
375 if (opts->dregs[sec_reg] >= 0) { |
|
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Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
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78
diff
changeset
|
376 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
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Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
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78
diff
changeset
|
377 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
378 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
379 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
380 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
381 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
382 if (inst->src.params.regs.sec & 0x10) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
383 if (opts->aregs[sec_reg] >= 0) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
384 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
385 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
386 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
387 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
388 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
389 if (opts->dregs[sec_reg] >= 0) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
390 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
391 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
392 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
393 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
394 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
395 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
396 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
397 if (inst->src.params.regs.displacement) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
398 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
399 } |
|
97
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
400 switch (inst->extra.size) |
|
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
401 { |
|
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
402 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
403 out = call(out, opts->read_8); |
|
97
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
404 break; |
|
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
405 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
406 out = call(out, opts->read_16); |
|
97
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
407 break; |
|
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
408 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
409 out = call(out, opts->read_32); |
|
97
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
410 break; |
|
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
411 } |
|
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
412 ea->mode = MODE_REG_DIRECT; |
|
c7185fd840fc
Fix address register indexed addressing (probably)
Mike Pavone <pavone@retrodev.com>
parents:
96
diff
changeset
|
413 ea->base = SCRATCH1; |
|
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
414 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
415 case MODE_PC_DISPLACE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
416 out = cycles(out, BUS); |
|
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
417 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
418 switch (inst->extra.size) |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
419 { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
420 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
421 out = call(out, opts->read_8); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
422 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
423 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
424 out = call(out, opts->read_16); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
425 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
426 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
427 out = call(out, opts->read_32); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
428 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
429 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
430 ea->mode = MODE_REG_DIRECT; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
431 ea->base = SCRATCH1; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
432 break; |
|
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
433 case MODE_PC_INDEX_DISP8: |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
434 out = cycles(out, 6); |
|
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
435 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
|
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
436 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
437 if (inst->src.params.regs.sec & 1) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
438 if (inst->src.params.regs.sec & 0x10) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
439 if (opts->aregs[sec_reg] >= 0) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
440 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
441 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
442 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
443 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
444 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
445 if (opts->dregs[sec_reg] >= 0) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
446 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
447 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
448 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
449 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
450 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
451 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
452 if (inst->src.params.regs.sec & 0x10) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
453 if (opts->aregs[sec_reg] >= 0) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
454 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
455 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
456 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
457 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
458 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
459 if (opts->dregs[sec_reg] >= 0) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
460 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
461 } else { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
462 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
463 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
464 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
465 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
466 } |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
467 if (inst->src.params.regs.displacement) { |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
468 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
469 } |
|
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
470 switch (inst->extra.size) |
|
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
471 { |
|
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
472 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
473 out = call(out, opts->read_8); |
|
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
474 break; |
|
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
475 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
476 out = call(out, opts->read_16); |
|
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
477 break; |
|
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
478 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
479 out = call(out, opts->read_32); |
|
96
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
480 break; |
|
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
481 } |
|
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
482 ea->mode = MODE_REG_DIRECT; |
|
f894f85cf39d
Fix pc indexed addressing (probably) when used as a source
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
483 ea->base = SCRATCH1; |
|
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
484 break; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
485 case MODE_ABSOLUTE: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
486 case MODE_ABSOLUTE_SHORT: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
487 if (inst->src.addr_mode == MODE_ABSOLUTE) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
488 out = cycles(out, BUS*2); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
489 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
490 out = cycles(out, BUS); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
491 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
492 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
493 switch (inst->extra.size) |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
494 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
495 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
496 out = call(out, opts->read_8); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
497 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
498 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
499 out = call(out, opts->read_16); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
500 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
501 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
502 out = call(out, opts->read_32); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
503 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
504 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
505 ea->mode = MODE_REG_DIRECT; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
506 ea->base = SCRATCH1; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
507 break; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
508 case MODE_IMMEDIATE: |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
509 case MODE_IMMEDIATE_WORD: |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
510 if (inst->variant != VAR_QUICK) { |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
511 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
512 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
513 ea->mode = MODE_IMMED; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
514 ea->disp = inst->src.params.immed; |
|
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
515 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && ea->disp & 0x8000) { |
|
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
516 ea->disp |= 0xFFFF0000; |
|
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
517 } |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
518 return out; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
519 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
520 m68k_disasm(inst, disasm_buf); |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
521 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
522 exit(1); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
523 } |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
524 if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
525 if (ea->mode == MODE_REG_DIRECT) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
526 out = movsx_rr(out, ea->base, SCRATCH1, SZ_W, SZ_D); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
527 } else { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
528 out = movsx_rdisp8r(out, ea->base, ea->disp, SCRATCH1, SZ_W, SZ_D); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
529 ea->mode = MODE_REG_DIRECT; |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
530 } |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
531 ea->base = SCRATCH1; |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
532 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
533 return out; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
534 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
535 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
536 code_ptr translate_m68k_dst(m68kinst * inst, x86_ea * ea, code_ptr out, x86_68k_options * opts, uint8_t fake_read) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
537 { |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
538 int8_t reg = native_reg(&(inst->dst), opts), sec_reg; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
539 int32_t dec_amount, inc_amount; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
540 if (reg >= 0) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
541 ea->mode = MODE_REG_DIRECT; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
542 ea->base = reg; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
543 return out; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
544 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
545 switch (inst->dst.addr_mode) |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 { |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
547 case MODE_REG: |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
548 case MODE_AREG: |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
549 ea->mode = MODE_REG_DISPLACE8; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
550 ea->base = CONTEXT; |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
551 ea->disp = reg_offset(&(inst->dst)); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
552 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
553 case MODE_AREG_PREDEC: |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
554 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
555 out = push_r(out, SCRATCH1); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
556 } |
|
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
557 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
558 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
559 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
560 } else { |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
561 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
562 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
563 case MODE_AREG_INDIRECT: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
564 case MODE_AREG_POSTINC: |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
565 if (fake_read) { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
566 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
567 } else { |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
568 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
569 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
570 } else { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
571 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
572 } |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
573 switch (inst->extra.size) |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
574 { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
575 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
576 out = call(out, opts->read_8); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
577 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
578 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
579 out = call(out, opts->read_16); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
580 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
581 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
582 out = call(out, opts->read_32); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
583 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
584 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
585 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
586 if (inst->src.addr_mode == MODE_AREG_PREDEC) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
587 //restore src operand to SCRATCH2 |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
588 out =pop_r(out, SCRATCH2); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
589 } else { |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
590 //save reg value in SCRATCH2 so we can use it to save the result in memory later |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
591 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
592 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
593 } else { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
594 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
595 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
596 } |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
597 |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
598 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
|
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
599 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
600 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
601 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
602 } else { |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
603 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
604 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
605 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
606 ea->mode = MODE_REG_DIRECT; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
607 ea->base = SCRATCH1; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
608 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
609 case MODE_AREG_DISPLACE: |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
610 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
611 reg = fake_read ? SCRATCH2 : SCRATCH1; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
612 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
613 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
614 } else { |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
615 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
616 } |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
617 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
618 if (!fake_read) { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
619 out = push_r(out, SCRATCH1); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
620 switch (inst->extra.size) |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
621 { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
622 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
623 out = call(out, opts->read_8); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
624 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
625 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
626 out = call(out, opts->read_16); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
627 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
628 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
629 out = call(out, opts->read_32); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
630 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
631 } |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
632 out = pop_r(out, SCRATCH2); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
633 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
634 ea->mode = MODE_REG_DIRECT; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
635 ea->base = SCRATCH1; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
636 break; |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
637 case MODE_AREG_INDEX_DISP8: |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
638 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
639 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
640 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
641 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
642 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
643 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
644 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
645 if (inst->dst.params.regs.sec & 1) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
646 if (inst->dst.params.regs.sec & 0x10) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
647 if (opts->aregs[sec_reg] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
648 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
649 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
650 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
651 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
652 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
653 if (opts->dregs[sec_reg] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
654 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
655 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
656 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
657 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
658 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
659 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
660 if (inst->dst.params.regs.sec & 0x10) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
661 if (opts->aregs[sec_reg] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
662 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
663 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
664 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
665 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
666 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
667 if (opts->dregs[sec_reg] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
668 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
669 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
670 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
671 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
672 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
673 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
674 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
675 if (inst->dst.params.regs.displacement) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
676 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
677 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
678 if (fake_read) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
679 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
680 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
681 out = push_r(out, SCRATCH1); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
682 switch (inst->extra.size) |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
683 { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
684 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
685 out = call(out, opts->read_8); |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
686 break; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
687 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
688 out = call(out, opts->read_16); |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
689 break; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
690 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
691 out = call(out, opts->read_32); |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
692 break; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
693 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
694 out = pop_r(out, SCRATCH2); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
695 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
696 ea->mode = MODE_REG_DIRECT; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
697 ea->base = SCRATCH1; |
|
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
698 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
699 case MODE_PC_DISPLACE: |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
700 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
701 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
702 if (!fake_read) { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
703 out = push_r(out, SCRATCH1); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
704 switch (inst->extra.size) |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
705 { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
706 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
707 out = call(out, opts->read_8); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
708 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
709 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
710 out = call(out, opts->read_16); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
711 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
712 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
713 out = call(out, opts->read_32); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
714 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
715 } |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
716 out = pop_r(out, SCRATCH2); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
717 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
718 ea->mode = MODE_REG_DIRECT; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
719 ea->base = SCRATCH1; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
720 break; |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
721 case MODE_PC_INDEX_DISP8: |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
722 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
723 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
724 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
725 if (inst->dst.params.regs.sec & 1) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
726 if (inst->dst.params.regs.sec & 0x10) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
727 if (opts->aregs[sec_reg] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
728 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
729 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
730 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
731 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
732 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
733 if (opts->dregs[sec_reg] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
734 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
735 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
736 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
737 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
738 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
739 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
740 if (inst->dst.params.regs.sec & 0x10) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
741 if (opts->aregs[sec_reg] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
742 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
743 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
744 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
745 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
746 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
747 if (opts->dregs[sec_reg] >= 0) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
748 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
749 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
750 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
751 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
752 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
753 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
754 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
755 if (inst->dst.params.regs.displacement) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
756 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
757 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
758 if (fake_read) { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
759 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
760 } else { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
761 out = push_r(out, SCRATCH1); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
762 switch (inst->extra.size) |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
763 { |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
764 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
765 out = call(out, opts->read_8); |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
766 break; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
767 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
768 out = call(out, opts->read_16); |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
769 break; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
770 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
771 out = call(out, opts->read_32); |
|
98
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
772 break; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
773 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
774 out = pop_r(out, SCRATCH2); |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
775 } |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
776 ea->mode = MODE_REG_DIRECT; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
777 ea->base = SCRATCH1; |
|
104e257fb93c
Allow indexed modes to be used as a destination
Mike Pavone <pavone@retrodev.com>
parents:
97
diff
changeset
|
778 break; |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
779 case MODE_ABSOLUTE: |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
780 case MODE_ABSOLUTE_SHORT: |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
781 //Add cycles for reading address from instruction stream |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
782 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : 0)); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
783 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
784 if (!fake_read) { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
785 out = push_r(out, SCRATCH1); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
786 switch (inst->extra.size) |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
787 { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
788 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
789 out = call(out, opts->read_8); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
790 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
791 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
792 out = call(out, opts->read_16); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
793 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
794 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
795 out = call(out, opts->read_32); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
796 break; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
797 } |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
798 out = pop_r(out, SCRATCH2); |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
799 } |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
800 ea->mode = MODE_REG_DIRECT; |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
801 ea->base = SCRATCH1; |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
802 break; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
803 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
804 m68k_disasm(inst, disasm_buf); |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
805 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
806 exit(1); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
807 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
808 return out; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
809 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
810 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
811 code_ptr m68k_save_result(m68kinst * inst, code_ptr out, x86_68k_options * opts) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
812 { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
813 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
814 if (inst->dst.addr_mode == MODE_AREG_PREDEC && inst->src.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
815 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
816 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
817 } else { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
818 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
819 } |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
820 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
821 switch (inst->extra.size) |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
822 { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
823 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
824 out = call(out, opts->write_8); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
825 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
826 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
827 out = call(out, opts->write_16); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
828 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
829 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
830 out = call(out, opts->write_32_lowfirst); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
831 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
832 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
833 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
834 return out; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
835 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
836 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
837 code_ptr get_native_address(native_map_slot * native_code_map, uint32_t address) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
838 { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
839 address &= 0xFFFFFF; |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
840 address /= 2; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
841 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
842 if (!native_code_map[chunk].base) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
843 return NULL; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
844 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
845 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
846 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET || native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
847 return NULL; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
848 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
849 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset]; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
850 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
851 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
852 code_ptr get_native_from_context(m68k_context * context, uint32_t address) |
|
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
853 { |
|
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
228
diff
changeset
|
854 return get_native_address(context->native_code_map, address); |
|
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
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855 } |
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856 |
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857 uint32_t get_instruction_start(native_map_slot * native_code_map, uint32_t address) |
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858 { |
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859 address &= 0xFFFFFF; |
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860 address /= 2; |
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861 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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862 if (!native_code_map[chunk].base) { |
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863 return 0; |
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864 } |
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865 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
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866 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) { |
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867 return 0; |
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868 } |
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869 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD) { |
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870 --address; |
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871 chunk = address / NATIVE_CHUNK_SIZE; |
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872 offset = address % NATIVE_CHUNK_SIZE; |
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873 } |
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874 return address*2; |
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875 } |
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876 |
|
558
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Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
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877 void map_native_address(m68k_context * context, uint32_t address, code_ptr native_addr, uint8_t size, uint8_t native_size) |
|
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878 { |
|
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879 native_map_slot * native_code_map = context->native_code_map; |
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880 x86_68k_options * opts = context->options; |
|
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881 address &= 0xFFFFFF; |
|
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882 if (address > 0xE00000) { |
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883 context->ram_code_flags[(address & 0xC000) >> 14] |= 1 << ((address & 0x3800) >> 11); |
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884 if (((address & 0x3FFF) + size) & 0xC000) { |
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885 context->ram_code_flags[((address+size) & 0xC000) >> 14] |= 1 << (((address+size) & 0x3800) >> 11); |
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886 } |
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|
887 uint32_t slot = (address & 0xFFFF)/1024; |
|
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888 if (!opts->gen.ram_inst_sizes[slot]) { |
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889 opts->gen.ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 512); |
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890 } |
|
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891 opts->gen.ram_inst_sizes[slot][((address & 0xFFFF)/2)%512] = native_size; |
|
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892 } |
|
95
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Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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893 address/= 2; |
|
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894 uint32_t chunk = address / NATIVE_CHUNK_SIZE; |
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895 if (!native_code_map[chunk].base) { |
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896 native_code_map[chunk].base = native_addr; |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
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|
897 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
|
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898 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
|
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899 } |
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900 uint32_t offset = address % NATIVE_CHUNK_SIZE; |
|
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901 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base; |
|
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902 for(address++,size-=2; size; address++,size-=2) { |
|
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903 chunk = address / NATIVE_CHUNK_SIZE; |
|
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904 offset = address % NATIVE_CHUNK_SIZE; |
|
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|
905 if (!native_code_map[chunk].base) { |
|
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|
906 native_code_map[chunk].base = native_addr; |
|
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|
907 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
|
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908 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE); |
|
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|
909 } |
|
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diff
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|
910 native_code_map[chunk].offsets[offset] = EXTENSION_WORD; |
|
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|
911 } |
|
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|
912 } |
|
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|
913 |
|
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diff
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|
914 uint8_t get_native_inst_size(x86_68k_options * opts, uint32_t address) |
|
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|
915 { |
|
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diff
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|
916 if (address < 0xE00000) { |
|
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diff
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|
917 return 0; |
|
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diff
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|
918 } |
|
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|
919 uint32_t slot = (address & 0xFFFF)/1024; |
|
558
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Mike Pavone <pavone@retrodev.com>
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diff
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|
920 return opts->gen.ram_inst_sizes[slot][((address & 0xFFFF)/2)%512]; |
|
18
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diff
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|
921 } |
|
3e7bfde7606e
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diff
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|
922 |
|
558
dc9f178085a0
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Mike Pavone <pavone@retrodev.com>
parents:
557
diff
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|
923 code_ptr translate_m68k_move(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
18
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diff
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|
924 { |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
925 int8_t reg, flags_reg, sec_reg; |
|
18
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diff
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|
926 uint8_t dir = 0; |
|
3e7bfde7606e
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diff
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|
927 int32_t offset; |
|
3e7bfde7606e
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14
diff
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|
928 int32_t inc_amount, dec_amount; |
|
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diff
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|
929 x86_ea src; |
|
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diff
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|
930 dst = translate_m68k_src(inst, &src, dst, opts); |
|
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diff
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|
931 reg = native_reg(&(inst->dst), opts); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
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183
diff
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|
932 if (inst->dst.addr_mode != MODE_AREG) { |
|
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183
diff
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|
933 //update statically set flags |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
934 dst = set_flag(dst, 0, FLAG_V, opts); |
|
90aca661542b
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Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
935 dst = set_flag(dst, 0, FLAG_C, opts); |
|
184
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|
936 } |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
937 |
|
216
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
938 if (inst->dst.addr_mode != MODE_AREG) { |
|
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|
939 if (src.mode == MODE_REG_DIRECT) { |
|
0b5ec22dcda2
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diff
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|
940 flags_reg = src.base; |
|
18
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|
941 } else { |
|
216
0b5ec22dcda2
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diff
changeset
|
942 if (reg >= 0) { |
|
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diff
changeset
|
943 flags_reg = reg; |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
944 } else { |
|
216
0b5ec22dcda2
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diff
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|
945 if(src.mode == MODE_REG_DISPLACE8) { |
|
0b5ec22dcda2
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diff
changeset
|
946 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
|
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213
diff
changeset
|
947 } else { |
|
0b5ec22dcda2
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213
diff
changeset
|
948 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
|
0b5ec22dcda2
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Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
949 } |
|
0b5ec22dcda2
Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
950 src.mode = MODE_REG_DIRECT; |
|
0b5ec22dcda2
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Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
951 flags_reg = src.base = SCRATCH1; |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
952 } |
|
18
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
953 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
954 } |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
955 uint8_t size = inst->extra.size; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
956 switch(inst->dst.addr_mode) |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
957 { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
958 case MODE_AREG: |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
959 size = OPSIZE_LONG; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
960 case MODE_REG: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
961 if (reg >= 0) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
962 if (src.mode == MODE_REG_DIRECT) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
963 dst = mov_rr(dst, src.base, reg, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
964 } else if (src.mode == MODE_REG_DISPLACE8) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
965 dst = mov_rdisp8r(dst, src.base, src.disp, reg, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
966 } else { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
967 dst = mov_ir(dst, src.disp, reg, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
968 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
969 } else if(src.mode == MODE_REG_DIRECT) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
970 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
971 } else { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
972 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
973 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
974 if (inst->dst.addr_mode != MODE_AREG) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
975 dst = cmp_ir(dst, 0, flags_reg, size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
976 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
977 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
978 } |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 break; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
980 case MODE_AREG_PREDEC: |
|
182
924af8b2f7a0
Fix -(a7) dest when size is byte
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
981 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
982 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
983 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
984 } else { |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
985 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
986 } |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 case MODE_AREG_INDIRECT: |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
988 case MODE_AREG_POSTINC: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
989 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
990 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
991 } else { |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
992 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
993 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
994 if (src.mode == MODE_REG_DIRECT) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
995 if (src.base != SCRATCH1) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
996 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
997 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
998 } else if (src.mode == MODE_REG_DISPLACE8) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
999 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1000 } else { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1001 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1002 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1003 if (inst->dst.addr_mode != MODE_AREG) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1004 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1005 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1006 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1007 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1008 switch (inst->extra.size) |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1009 { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1010 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1011 dst = call(dst, opts->write_8); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1012 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1013 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1014 dst = call(dst, opts->write_16); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1015 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1016 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1017 dst = call(dst, opts->write_32_highfirst); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1018 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1019 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1020 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
|
218
1abf8e967b33
Fix autoincrement on a7 when used as a destination in a byte sized instruction
Mike Pavone <pavone@retrodev.com>
parents:
216
diff
changeset
|
1021 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1022 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1023 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1024 } else { |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1025 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1026 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1027 } |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1029 case MODE_AREG_DISPLACE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1030 dst = cycles(dst, BUS); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1031 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1032 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1033 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1034 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1035 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1036 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1037 if (src.mode == MODE_REG_DIRECT) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1038 if (src.base != SCRATCH1) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1039 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1040 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1041 } else if (src.mode == MODE_REG_DISPLACE8) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1042 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1043 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1044 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1045 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1046 if (inst->dst.addr_mode != MODE_AREG) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1047 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1048 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1049 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1050 } |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1051 switch (inst->extra.size) |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1052 { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1053 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1054 dst = call(dst, opts->write_8); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1055 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1056 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1057 dst = call(dst, opts->write_16); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1058 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1059 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1060 dst = call(dst, opts->write_32_highfirst); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1061 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1062 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1063 break; |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1064 case MODE_AREG_INDEX_DISP8: |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1065 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
|
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1066 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1067 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1068 } else { |
|
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1069 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1070 } |
|
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1071 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
|
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1072 if (inst->dst.params.regs.sec & 1) { |
|
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1073 if (inst->dst.params.regs.sec & 0x10) { |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1074 if (opts->aregs[sec_reg] >= 0) { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1075 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1076 } else { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1077 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1078 } |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1079 } else { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1080 if (opts->dregs[sec_reg] >= 0) { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1081 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1082 } else { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1083 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1084 } |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1085 } |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1086 } else { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1087 if (src.base == SCRATCH1) { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1088 dst = push_r(dst, SCRATCH1); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1089 } |
|
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1090 if (inst->dst.params.regs.sec & 0x10) { |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1091 if (opts->aregs[sec_reg] >= 0) { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1092 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1093 } else { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1094 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1095 } |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1096 } else { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1097 if (opts->dregs[sec_reg] >= 0) { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1098 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1099 } else { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1100 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1101 } |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1102 } |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1103 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1104 if (src.base == SCRATCH1) { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1105 dst = pop_r(dst, SCRATCH1); |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1106 } |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1107 } |
|
107
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1108 if (inst->dst.params.regs.displacement) { |
|
9705075fcf36
Fix areg indexed mode for move dst
Mike Pavone <pavone@retrodev.com>
parents:
106
diff
changeset
|
1109 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1110 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1111 if (src.mode == MODE_REG_DIRECT) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1112 if (src.base != SCRATCH1) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1113 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1114 } |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1115 } else if (src.mode == MODE_REG_DISPLACE8) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1116 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1117 } else { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1118 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1119 } |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1120 if (inst->dst.addr_mode != MODE_AREG) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1121 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1122 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1123 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1124 } |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1125 switch (inst->extra.size) |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1126 { |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1127 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1128 dst = call(dst, opts->write_8); |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1129 break; |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1130 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1131 dst = call(dst, opts->write_16); |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1132 break; |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1133 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1134 dst = call(dst, opts->write_32_highfirst); |
|
99
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1135 break; |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1136 } |
|
8491de5d6c06
Allow use of indexed modes as move dst
Mike Pavone <pavone@retrodev.com>
parents:
98
diff
changeset
|
1137 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1138 case MODE_PC_DISPLACE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1139 dst = cycles(dst, BUS); |
|
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1140 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1141 if (src.mode == MODE_REG_DIRECT) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1142 if (src.base != SCRATCH1) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1143 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1144 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1145 } else if (src.mode == MODE_REG_DISPLACE8) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1146 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1147 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1148 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1149 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1150 if (inst->dst.addr_mode != MODE_AREG) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1151 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1152 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1153 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1154 } |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1155 switch (inst->extra.size) |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1156 { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1157 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1158 dst = call(dst, opts->write_8); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1159 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1160 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1161 dst = call(dst, opts->write_16); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1162 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1163 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1164 dst = call(dst, opts->write_32_highfirst); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1165 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1166 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1167 break; |
|
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1168 case MODE_PC_INDEX_DISP8: |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1169 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1170 dst = mov_ir(dst, inst->address, SCRATCH2, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1171 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1172 if (inst->dst.params.regs.sec & 1) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1173 if (inst->dst.params.regs.sec & 0x10) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1174 if (opts->aregs[sec_reg] >= 0) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1175 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1176 } else { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1177 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1178 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1179 } else { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1180 if (opts->dregs[sec_reg] >= 0) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1181 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1182 } else { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1183 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1184 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1185 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1186 } else { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1187 if (src.base == SCRATCH1) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1188 dst = push_r(dst, SCRATCH1); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1189 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1190 if (inst->dst.params.regs.sec & 0x10) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1191 if (opts->aregs[sec_reg] >= 0) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1192 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1193 } else { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1194 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1195 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1196 } else { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1197 if (opts->dregs[sec_reg] >= 0) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1198 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1199 } else { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1200 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1201 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1202 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1203 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1204 if (src.base == SCRATCH1) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1205 dst = pop_r(dst, SCRATCH1); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1206 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1207 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1208 if (inst->dst.params.regs.displacement) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1209 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1210 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1211 if (src.mode == MODE_REG_DIRECT) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1212 if (src.base != SCRATCH1) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1213 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1214 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1215 } else if (src.mode == MODE_REG_DISPLACE8) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1216 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1217 } else { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1218 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1219 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1220 if (inst->dst.addr_mode != MODE_AREG) { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1221 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1222 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1223 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1224 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1225 switch (inst->extra.size) |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1226 { |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1227 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1228 dst = call(dst, opts->write_8); |
|
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1229 break; |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1230 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1231 dst = call(dst, opts->write_16); |
|
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1232 break; |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1233 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1234 dst = call(dst, opts->write_32_highfirst); |
|
196
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1235 break; |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1236 } |
|
f8955d33486d
Implement pc indexed mode as move dst
Mike Pavone <pavone@retrodev.com>
parents:
194
diff
changeset
|
1237 break; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1238 case MODE_ABSOLUTE: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1239 case MODE_ABSOLUTE_SHORT: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1240 if (src.mode == MODE_REG_DIRECT) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1241 if (src.base != SCRATCH1) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1242 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1243 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1244 } else if (src.mode == MODE_REG_DISPLACE8) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1245 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1246 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1247 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1248 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1249 if (inst->dst.addr_mode == MODE_ABSOLUTE) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1250 dst = cycles(dst, BUS*2); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1251 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1252 dst = cycles(dst, BUS); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1253 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1254 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1255 if (inst->dst.addr_mode != MODE_AREG) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1256 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1257 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1258 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1259 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1260 switch (inst->extra.size) |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1261 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1262 case OPSIZE_BYTE: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1263 dst = call(dst, opts->write_8); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1264 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1265 case OPSIZE_WORD: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1266 dst = call(dst, opts->write_16); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1267 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1268 case OPSIZE_LONG: |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1269 dst = call(dst, opts->write_32_highfirst); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1270 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1271 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
53
diff
changeset
|
1272 break; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1273 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1274 m68k_disasm(inst, disasm_buf); |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1275 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1276 exit(1); |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1277 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1278 |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1279 //add cycles for prefetch |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1280 dst = cycles(dst, BUS); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1281 return dst; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1282 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1283 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1284 code_ptr translate_m68k_movem(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1285 { |
|
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1286 int8_t bit,reg,sec_reg; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1287 uint8_t early_cycles; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1288 if(inst->src.addr_mode == MODE_REG) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1289 //reg to mem |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1290 early_cycles = 8; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1291 int8_t dir; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1292 switch (inst->dst.addr_mode) |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1293 { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1294 case MODE_AREG_INDIRECT: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1295 case MODE_AREG_PREDEC: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1296 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1297 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1298 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1299 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1300 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1301 break; |
|
161
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1302 case MODE_AREG_DISPLACE: |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1303 early_cycles += BUS; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1304 reg = SCRATCH2; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1305 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1306 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1307 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1308 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1309 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1310 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1311 break; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1312 case MODE_AREG_INDEX_DISP8: |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1313 early_cycles += 6; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1314 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1315 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1316 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1317 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1318 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1319 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1320 if (inst->dst.params.regs.sec & 1) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1321 if (inst->dst.params.regs.sec & 0x10) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1322 if (opts->aregs[sec_reg] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1323 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1324 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1325 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1326 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1327 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1328 if (opts->dregs[sec_reg] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1329 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1330 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1331 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1332 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1333 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1334 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1335 if (inst->dst.params.regs.sec & 0x10) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1336 if (opts->aregs[sec_reg] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1337 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1338 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1339 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1340 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1341 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1342 if (opts->dregs[sec_reg] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1343 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1344 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1345 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1346 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1347 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1348 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1349 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1350 if (inst->dst.params.regs.displacement) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1351 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1352 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1353 break; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1354 case MODE_PC_DISPLACE: |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1355 early_cycles += BUS; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1356 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1357 break; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1358 case MODE_PC_INDEX_DISP8: |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1359 early_cycles += 6; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1360 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1361 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1362 if (inst->dst.params.regs.sec & 1) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1363 if (inst->dst.params.regs.sec & 0x10) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1364 if (opts->aregs[sec_reg] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1365 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1366 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1367 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1368 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1369 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1370 if (opts->dregs[sec_reg] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1371 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1372 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1373 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1374 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1375 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1376 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1377 if (inst->dst.params.regs.sec & 0x10) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1378 if (opts->aregs[sec_reg] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1379 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1380 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1381 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1382 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1383 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1384 if (opts->dregs[sec_reg] >= 0) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1385 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1386 } else { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1387 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1388 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1389 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1390 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1391 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1392 if (inst->dst.params.regs.displacement) { |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1393 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1394 } |
|
6748022656b7
Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Mike Pavone <pavone@retrodev.com>
parents:
159
diff
changeset
|
1395 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1396 case MODE_ABSOLUTE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1397 early_cycles += 4; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1398 case MODE_ABSOLUTE_SHORT: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1399 early_cycles += 4; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1400 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1401 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1402 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1403 m68k_disasm(inst, disasm_buf); |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1404 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1405 exit(1); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1406 } |
|
210
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1407 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
|
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1408 reg = 15; |
|
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1409 dir = -1; |
|
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1410 } else { |
|
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1411 reg = 0; |
|
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1412 dir = 1; |
|
4beaad3a9a50
Fix movem reg to mem for certain addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
209
diff
changeset
|
1413 } |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1414 dst = cycles(dst, early_cycles); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1415 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1416 if (inst->src.params.immed & (1 << bit)) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1417 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1418 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1419 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1420 dst = push_r(dst, SCRATCH2); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1421 if (reg > 7) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1422 if (opts->aregs[reg-8] >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1423 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1424 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1425 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1426 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1427 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1428 if (opts->dregs[reg] >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1429 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1430 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1431 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1432 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1433 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1434 if (inst->extra.size == OPSIZE_LONG) { |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1435 dst = call(dst, opts->write_32_lowfirst); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1436 } else { |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1437 dst = call(dst, opts->write_16); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1438 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1439 dst = pop_r(dst, SCRATCH2); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1440 if (inst->dst.addr_mode != MODE_AREG_PREDEC) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1441 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1442 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1443 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1444 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1445 if (inst->dst.addr_mode == MODE_AREG_PREDEC) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1446 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1447 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1448 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1449 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1450 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1451 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1452 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1453 //mem to reg |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1454 early_cycles = 4; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1455 switch (inst->src.addr_mode) |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1456 { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1457 case MODE_AREG_INDIRECT: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1458 case MODE_AREG_POSTINC: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1459 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1460 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
f80fa1776507
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Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1461 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1462 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1463 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1464 break; |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1465 case MODE_AREG_DISPLACE: |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1466 early_cycles += BUS; |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1467 reg = SCRATCH2; |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1468 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1469 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1470 } else { |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1471 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1472 } |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1473 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1474 break; |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1475 case MODE_AREG_INDEX_DISP8: |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1476 early_cycles += 6; |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1477 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1478 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1479 } else { |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1480 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1481 } |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1482 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1483 if (inst->src.params.regs.sec & 1) { |
|
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1484 if (inst->src.params.regs.sec & 0x10) { |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1485 if (opts->aregs[sec_reg] >= 0) { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1486 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1487 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1488 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1489 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1490 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1491 if (opts->dregs[sec_reg] >= 0) { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1492 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1493 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1494 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1495 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1496 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1497 } else { |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1498 if (inst->src.params.regs.sec & 0x10) { |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1499 if (opts->aregs[sec_reg] >= 0) { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1500 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1501 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1502 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1503 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1504 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1505 if (opts->dregs[sec_reg] >= 0) { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1506 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1507 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1508 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1509 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1510 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1511 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1512 } |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1513 if (inst->src.params.regs.displacement) { |
|
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1514 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1515 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1516 break; |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1517 case MODE_PC_DISPLACE: |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1518 early_cycles += BUS; |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1519 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1520 break; |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1521 case MODE_PC_INDEX_DISP8: |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1522 early_cycles += 6; |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1523 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1524 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1525 if (inst->src.params.regs.sec & 1) { |
|
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1526 if (inst->src.params.regs.sec & 0x10) { |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1527 if (opts->aregs[sec_reg] >= 0) { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1528 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1529 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1530 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1531 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1532 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1533 if (opts->dregs[sec_reg] >= 0) { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1534 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1535 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1536 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1537 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1538 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1539 } else { |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1540 if (inst->src.params.regs.sec & 0x10) { |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1541 if (opts->aregs[sec_reg] >= 0) { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1542 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1543 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1544 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1545 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1546 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1547 if (opts->dregs[sec_reg] >= 0) { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1548 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1549 } else { |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1550 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1551 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1552 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1553 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1554 } |
|
169
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1555 if (inst->src.params.regs.displacement) { |
|
c07713463c91
Fix a bunch of addressing modes in movem when a register list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
168
diff
changeset
|
1556 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
162
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1557 } |
|
eba78ad49a11
Implement more movem modes src
Mike Pavone <pavone@retrodev.com>
parents:
161
diff
changeset
|
1558 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1559 case MODE_ABSOLUTE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1560 early_cycles += 4; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1561 case MODE_ABSOLUTE_SHORT: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1562 early_cycles += 4; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1563 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1564 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1565 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1566 m68k_disasm(inst, disasm_buf); |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1567 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1568 exit(1); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1569 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1570 dst = cycles(dst, early_cycles); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1571 for(reg = 0; reg < 16; reg ++) { |
|
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1572 if (inst->dst.params.immed & (1 << reg)) { |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1573 dst = push_r(dst, SCRATCH1); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1574 if (inst->extra.size == OPSIZE_LONG) { |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1575 dst = call(dst, opts->read_32); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1576 } else { |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1577 dst = call(dst, opts->read_16); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1578 } |
|
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1579 if (inst->extra.size == OPSIZE_WORD) { |
|
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1580 dst = movsx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
|
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1581 } |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1582 if (reg > 7) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1583 if (opts->aregs[reg-8] >= 0) { |
|
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1584 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1585 } else { |
|
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1586 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1587 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1588 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1589 if (opts->dregs[reg] >= 0) { |
|
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1590 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1591 } else { |
|
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
1592 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1593 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1594 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1595 dst = pop_r(dst, SCRATCH1); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1596 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1597 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1598 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1599 if (inst->src.addr_mode == MODE_AREG_POSTINC) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1600 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1601 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1602 } else { |
|
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1603 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1604 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1605 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1606 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1607 //prefetch |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1608 dst = cycles(dst, 4); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1609 return dst; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1610 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1611 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1612 code_ptr translate_m68k_clr(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1613 { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1614 dst = set_flag(dst, 0, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1615 dst = set_flag(dst, 0, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1616 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1617 dst = set_flag(dst, 1, FLAG_Z, opts); |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1618 int8_t reg = native_reg(&(inst->dst), opts); |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1619 if (reg >= 0) { |
|
64
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1620 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); |
|
2b1a65f4b85d
Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents:
61
diff
changeset
|
1621 return xor_rr(dst, reg, reg, inst->extra.size); |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1622 } |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1623 x86_ea dst_op; |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1624 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1625 if (dst_op.mode == MODE_REG_DIRECT) { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1626 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size); |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1627 } else { |
|
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1628 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1629 } |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1630 dst = m68k_save_result(inst, dst, opts); |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1631 return dst; |
|
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1632 } |
|
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
1633 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1634 code_ptr translate_m68k_ext(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1635 { |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1636 x86_ea dst_op; |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1637 uint8_t dst_size = inst->extra.size; |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1638 inst->extra.size--; |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1639 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1640 if (dst_op.mode == MODE_REG_DIRECT) { |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1641 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size); |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1642 dst = cmp_ir(dst, 0, dst_op.base, dst_size); |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1643 } else { |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1644 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size); |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1645 dst = cmp_ir(dst, 0, SCRATCH1, dst_size); |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1646 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size); |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1647 } |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1648 inst->extra.size = dst_size; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1649 dst = set_flag(dst, 0, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1650 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1651 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1652 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1653 //M68K EXT only operates on registers so no need for a call to save result here |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1654 return dst; |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1655 } |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
1656 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1657 code_ptr translate_m68k_lea(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1658 { |
|
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1659 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1660 switch(inst->src.addr_mode) |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1661 { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1662 case MODE_AREG_INDIRECT: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1663 dst = cycles(dst, BUS); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1664 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1665 if (dst_reg >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1666 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1667 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1668 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1669 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1670 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1671 if (dst_reg >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1672 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1673 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1674 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1675 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1676 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1677 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1678 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1679 case MODE_AREG_DISPLACE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1680 dst = cycles(dst, 8); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1681 if (dst_reg >= 0) { |
|
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1682 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1683 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1684 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1685 } else { |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1686 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1687 } |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1688 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1689 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1690 } else { |
|
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1691 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) { |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1692 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1693 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1694 } else { |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1695 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1696 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1697 } |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1698 } |
|
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1699 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1700 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1701 break; |
|
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1702 case MODE_AREG_INDEX_DISP8: |
|
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1703 dst = cycles(dst, 12); |
|
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1704 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1705 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1706 } else { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1707 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1708 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1709 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1710 if (inst->src.params.regs.sec & 1) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1711 if (inst->src.params.regs.sec & 0x10) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1712 if (opts->aregs[sec_reg] >= 0) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1713 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1714 } else { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1715 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1716 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1717 } else { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1718 if (opts->dregs[sec_reg] >= 0) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1719 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1720 } else { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1721 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1722 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1723 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1724 } else { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1725 if (inst->src.params.regs.sec & 0x10) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1726 if (opts->aregs[sec_reg] >= 0) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1727 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1728 } else { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1729 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1730 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1731 } else { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1732 if (opts->dregs[sec_reg] >= 0) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1733 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1734 } else { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1735 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1736 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1737 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1738 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1739 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1740 if (inst->src.params.regs.displacement) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1741 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1742 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1743 if (dst_reg >= 0) { |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1744 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D); |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1745 } else { |
|
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
1746 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
100
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1747 } |
|
45cd7d3e7918
Implement areg indexed mode for lea
Mike Pavone <pavone@retrodev.com>
parents:
99
diff
changeset
|
1748 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1749 case MODE_PC_DISPLACE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1750 dst = cycles(dst, 8); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1751 if (dst_reg >= 0) { |
|
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1752 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1753 } else { |
|
74
6396dc91f61e
Fix some bugs in movem with a register list destination
Mike Pavone <pavone@retrodev.com>
parents:
73
diff
changeset
|
1754 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1755 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1756 break; |
|
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1757 case MODE_PC_INDEX_DISP8: |
|
168
7b099f2b382b
Minor optimization and a cycle count fix to lea
Mike Pavone <pavone@retrodev.com>
parents:
167
diff
changeset
|
1758 dst = cycles(dst, BUS*3); |
|
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1759 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1760 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1761 if (inst->src.params.regs.sec & 1) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1762 if (inst->src.params.regs.sec & 0x10) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1763 if (opts->aregs[sec_reg] >= 0) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1764 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1765 } else { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1766 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1767 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1768 } else { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1769 if (opts->dregs[sec_reg] >= 0) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1770 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1771 } else { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1772 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1773 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1774 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1775 } else { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1776 if (inst->src.params.regs.sec & 0x10) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1777 if (opts->aregs[sec_reg] >= 0) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1778 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1779 } else { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1780 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1781 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1782 } else { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1783 if (opts->dregs[sec_reg] >= 0) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1784 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1785 } else { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1786 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1787 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1788 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1789 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1790 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1791 if (inst->src.params.regs.displacement) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1792 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1793 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1794 if (dst_reg >= 0) { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1795 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1796 } else { |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1797 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1798 } |
|
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1799 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1800 case MODE_ABSOLUTE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1801 case MODE_ABSOLUTE_SHORT: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1802 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1803 if (dst_reg >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1804 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1805 } else { |
|
133
c4d10c2aaee2
Add support for pc indexed addressing mode to lea
Mike Pavone <pavone@retrodev.com>
parents:
132
diff
changeset
|
1806 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1807 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1808 break; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1809 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1810 m68k_disasm(inst, disasm_buf); |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1811 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1812 exit(1); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
1813 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1814 return dst; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1815 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1816 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1817 code_ptr translate_m68k_pea(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1818 { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1819 uint8_t sec_reg; |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1820 switch(inst->src.addr_mode) |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1821 { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1822 case MODE_AREG_INDIRECT: |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1823 dst = cycles(dst, BUS); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1824 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1825 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1826 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1827 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1828 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1829 break; |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1830 case MODE_AREG_DISPLACE: |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1831 dst = cycles(dst, 8); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1832 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1833 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1834 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1835 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1836 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1837 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1838 break; |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1839 case MODE_AREG_INDEX_DISP8: |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1840 dst = cycles(dst, 6);//TODO: Check to make sure this is correct |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1841 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1842 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1843 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1844 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1845 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1846 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1847 if (inst->src.params.regs.sec & 1) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1848 if (inst->src.params.regs.sec & 0x10) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1849 if (opts->aregs[sec_reg] >= 0) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1850 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1851 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1852 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1853 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1854 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1855 if (opts->dregs[sec_reg] >= 0) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1856 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1857 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1858 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1859 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1860 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1861 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1862 if (inst->src.params.regs.sec & 0x10) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1863 if (opts->aregs[sec_reg] >= 0) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1864 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1865 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1866 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1867 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1868 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1869 if (opts->dregs[sec_reg] >= 0) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1870 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1871 } else { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1872 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1873 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1874 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1875 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1876 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1877 if (inst->src.params.regs.displacement) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1878 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1879 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1880 break; |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1881 case MODE_PC_DISPLACE: |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1882 dst = cycles(dst, 8); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1883 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1884 break; |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1885 case MODE_ABSOLUTE: |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1886 case MODE_ABSOLUTE_SHORT: |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1887 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1888 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1889 break; |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1890 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
1891 m68k_disasm(inst, disasm_buf); |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1892 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode); |
|
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1893 exit(1); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1894 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1895 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1896 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1897 dst = call(dst, opts->write_32_lowfirst); |
|
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1898 return dst; |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1899 } |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
1900 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1901 code_ptr translate_m68k_bsr(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1902 { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1903 int32_t disp = inst->src.params.immed; |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
1904 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1905 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
1906 dst = cycles(dst, 10); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1907 dst = mov_ir(dst, after, SCRATCH1, SZ_D); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1908 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1909 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
1910 dst = call(dst, opts->write_32_highfirst); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1911 code_ptr dest_addr = get_native_address(opts->gen.native_code_map, (inst->address+2) + disp); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1912 if (!dest_addr) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1913 opts->gen.deferred = defer_address(opts->gen.deferred, (inst->address+2) + disp, dst + 1); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1914 //dummy address to be replaced later |
|
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
1915 dest_addr = dst + 256; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1916 } |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
1917 dst = jmp(dst, (char *)dest_addr); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1918 return dst; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1919 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1920 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1921 code_ptr translate_m68k_bcc(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1922 { |
|
156
3900cfde9dbb
Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)
Mike Pavone <pavone@retrodev.com>
parents:
155
diff
changeset
|
1923 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1924 int32_t disp = inst->src.params.immed; |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
1925 uint32_t after = inst->address + 2; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1926 code_ptr dest_addr = get_native_address(opts->gen.native_code_map, after + disp); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1927 if (inst->extra.cond == COND_TRUE) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1928 if (!dest_addr) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1929 opts->gen.deferred = defer_address(opts->gen.deferred, after + disp, dst + 1); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1930 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1931 dest_addr = dst + 256; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1932 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1933 dst = jmp(dst, dest_addr); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1934 } else { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1935 uint8_t cond = CC_NZ; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1936 switch (inst->extra.cond) |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1937 { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1938 case COND_HIGH: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1939 cond = CC_Z; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1940 case COND_LOW_SAME: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1941 dst = flag_to_reg(dst, FLAG_Z, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1942 dst = or_flag_to_reg(dst, FLAG_C, SCRATCH1, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1943 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1944 case COND_CARRY_CLR: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1945 cond = CC_Z; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1946 case COND_CARRY_SET: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1947 dst = check_flag(dst, FLAG_C, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1948 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1949 case COND_NOT_EQ: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1950 cond = CC_Z; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1951 case COND_EQ: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1952 dst = check_flag(dst, FLAG_Z, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1953 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1954 case COND_OVERF_CLR: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1955 cond = CC_Z; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1956 case COND_OVERF_SET: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1957 dst = check_flag(dst, FLAG_V, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1958 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1959 case COND_PLUS: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1960 cond = CC_Z; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1961 case COND_MINUS: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1962 dst = check_flag(dst, FLAG_N, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1963 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1964 case COND_GREATER_EQ: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1965 cond = CC_Z; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1966 case COND_LESS: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1967 dst = cmp_flags(dst, FLAG_N, FLAG_V, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1968 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1969 case COND_GREATER: |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1970 cond = CC_Z; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1971 case COND_LESS_EQ: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1972 dst = flag_to_reg(dst, FLAG_V, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1973 dst = xor_flag_to_reg(dst, FLAG_N, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
1974 dst = or_flag_to_reg(dst, FLAG_Z, SCRATCH1, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1975 break; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1976 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1977 if (!dest_addr) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
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|
1978 opts->gen.deferred = defer_address(opts->gen.deferred, after + disp, dst + 2); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
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|
1979 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1980 dest_addr = dst + 256; |
|
3e7bfde7606e
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parents:
14
diff
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|
1981 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
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parents:
14
diff
changeset
|
1982 dst = jcc(dst, cond, dest_addr); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1983 } |
|
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
1984 return dst; |
|
3e7bfde7606e
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Mike Pavone <pavone@retrodev.com>
parents:
14
diff
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|
1985 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
1986 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
1987 code_ptr translate_m68k_scc(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
| 112 | 1988 { |
| 1989 uint8_t cond = inst->extra.cond; | |
| 1990 x86_ea dst_op; | |
| 1991 inst->extra.size = OPSIZE_BYTE; | |
| 1992 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1); | |
| 1993 if (cond == COND_TRUE || cond == COND_FALSE) { | |
| 1994 if ((inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) { | |
| 1995 dst = cycles(dst, 6); | |
| 1996 } else { | |
| 1997 dst = cycles(dst, BUS); | |
| 1998 } | |
| 1999 if (dst_op.mode == MODE_REG_DIRECT) { | |
|
179
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2000 dst = mov_ir(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B); |
| 112 | 2001 } else { |
|
179
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
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|
2002 dst = mov_irdisp8(dst, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B); |
| 112 | 2003 } |
| 2004 } else { | |
| 2005 uint8_t cc = CC_NZ; | |
| 2006 switch (cond) | |
| 2007 { | |
| 2008 case COND_HIGH: | |
| 2009 cc = CC_Z; | |
| 2010 case COND_LOW_SAME: | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2011 dst = flag_to_reg(dst, FLAG_Z, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2012 dst = or_flag_to_reg(dst, FLAG_C, SCRATCH1, opts); |
| 112 | 2013 break; |
| 2014 case COND_CARRY_CLR: | |
| 2015 cc = CC_Z; | |
| 2016 case COND_CARRY_SET: | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2017 dst = check_flag(dst, FLAG_C, opts); |
| 112 | 2018 break; |
| 2019 case COND_NOT_EQ: | |
| 2020 cc = CC_Z; | |
| 2021 case COND_EQ: | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2022 dst = check_flag(dst, FLAG_Z, opts); |
| 112 | 2023 break; |
| 2024 case COND_OVERF_CLR: | |
| 2025 cc = CC_Z; | |
| 2026 case COND_OVERF_SET: | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2027 dst = check_flag(dst, FLAG_V, opts); |
| 112 | 2028 break; |
| 2029 case COND_PLUS: | |
| 2030 cc = CC_Z; | |
| 2031 case COND_MINUS: | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2032 dst = check_flag(dst, FLAG_N, opts); |
| 112 | 2033 break; |
| 2034 case COND_GREATER_EQ: | |
| 2035 cc = CC_Z; | |
| 2036 case COND_LESS: | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2037 dst = cmp_flags(dst, FLAG_N, FLAG_V, opts); |
| 112 | 2038 break; |
| 2039 case COND_GREATER: | |
| 2040 cc = CC_Z; | |
| 2041 case COND_LESS_EQ: | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2042 dst = flag_to_reg(dst, FLAG_V, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2043 dst = xor_flag_to_reg(dst, FLAG_N, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2044 dst = or_flag_to_reg(dst, FLAG_Z, SCRATCH1, opts); |
| 112 | 2045 break; |
| 2046 } | |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2047 code_ptr true_off = dst + 1; |
|
179
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2048 dst = jcc(dst, cc, dst+2); |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2049 dst = cycles(dst, BUS); |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2050 if (dst_op.mode == MODE_REG_DIRECT) { |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2051 dst = mov_ir(dst, 0, dst_op.base, SZ_B); |
| 112 | 2052 } else { |
|
179
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2053 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B); |
| 112 | 2054 } |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2055 code_ptr end_off = dst+1; |
|
179
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2056 dst = jmp(dst, dst+2); |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2057 *true_off = dst - (true_off+1); |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2058 dst = cycles(dst, 6); |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2059 if (dst_op.mode == MODE_REG_DIRECT) { |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2060 dst = mov_ir(dst, 0xFF, dst_op.base, SZ_B); |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2061 } else { |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2062 dst = mov_irdisp8(dst, 0xFF, dst_op.base, dst_op.disp, SZ_B); |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2063 } |
|
68af8a56ab7a
Fix scc to set reg to 0xFF rather than 1 when the condition is true
Mike Pavone <pavone@retrodev.com>
parents:
178
diff
changeset
|
2064 *end_off = dst - (end_off+1); |
| 112 | 2065 } |
| 2066 dst = m68k_save_result(inst, dst, opts); | |
| 2067 return dst; | |
| 2068 } | |
| 2069 | |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2070 code_ptr translate_m68k_jmp(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2071 { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2072 code_ptr dest_addr; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2073 uint8_t sec_reg; |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2074 uint32_t m68k_addr; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2075 switch(inst->src.addr_mode) |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2076 { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2077 case MODE_AREG_INDIRECT: |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2078 dst = cycles(dst, BUS*2); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2079 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2080 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2081 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2082 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2083 } |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2084 dst = call(dst, opts->native_addr); |
|
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2085 dst = jmp_r(dst, SCRATCH1); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2086 break; |
|
132
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2087 case MODE_AREG_INDEX_DISP8: |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2088 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2089 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2090 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2091 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2092 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2093 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2094 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2095 if (inst->src.params.regs.sec & 1) { |
|
516
7f54f1773e84
Properly handle jmp instructions in the debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
485
diff
changeset
|
2096 //32-bit index register |
|
132
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2097 if (inst->src.params.regs.sec & 0x10) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2098 if (opts->aregs[sec_reg] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2099 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2100 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2101 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2102 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2103 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2104 if (opts->dregs[sec_reg] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2105 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2106 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2107 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2108 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2109 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2110 } else { |
|
516
7f54f1773e84
Properly handle jmp instructions in the debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
485
diff
changeset
|
2111 //16-bit index register |
|
132
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2112 if (inst->src.params.regs.sec & 0x10) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2113 if (opts->aregs[sec_reg] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2114 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2115 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2116 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2117 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2118 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2119 if (opts->dregs[sec_reg] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2120 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2121 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2122 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2123 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2124 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2125 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2126 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2127 if (inst->src.params.regs.displacement) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2128 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2129 } |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2130 dst = call(dst, opts->native_addr); |
|
132
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2131 dst = jmp_r(dst, SCRATCH1); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2132 break; |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2133 case MODE_PC_DISPLACE: |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2134 dst = cycles(dst, 10); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2135 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2136 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2137 dest_addr = get_native_address(opts->gen.native_code_map, m68k_addr); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2138 if (!dest_addr) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2139 opts->gen.deferred = defer_address(opts->gen.deferred, m68k_addr, dst + 1); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2140 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2141 dest_addr = dst + 256; |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2142 } |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2143 dst = jmp(dst, dest_addr); |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2144 } else { |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2145 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2146 dst = call(dst, opts->native_addr); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2147 dst = jmp_r(dst, SCRATCH1); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2148 } |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2149 break; |
|
132
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2150 case MODE_PC_INDEX_DISP8: |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2151 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2152 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2153 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2154 if (inst->src.params.regs.sec & 1) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2155 if (inst->src.params.regs.sec & 0x10) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2156 if (opts->aregs[sec_reg] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2157 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2158 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2159 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2160 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2161 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2162 if (opts->dregs[sec_reg] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2163 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2164 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2165 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2166 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2167 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2168 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2169 if (inst->src.params.regs.sec & 0x10) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2170 if (opts->aregs[sec_reg] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2171 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2172 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2173 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2174 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2175 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2176 if (opts->dregs[sec_reg] >= 0) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2177 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2178 } else { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2179 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2180 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2181 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2182 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2183 } |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2184 if (inst->src.params.regs.displacement) { |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2185 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2186 } |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2187 dst = call(dst, opts->native_addr); |
|
132
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2188 dst = jmp_r(dst, SCRATCH1); |
|
0969d8363a20
Support more address modes for jmp
Mike Pavone <pavone@retrodev.com>
parents:
129
diff
changeset
|
2189 break; |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2190 case MODE_ABSOLUTE: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2191 case MODE_ABSOLUTE_SHORT: |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2192 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2193 m68k_addr = inst->src.params.immed; |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2194 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2195 dest_addr = get_native_address(opts->gen.native_code_map, m68k_addr); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2196 if (!dest_addr) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2197 opts->gen.deferred = defer_address(opts->gen.deferred, m68k_addr, dst + 1); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2198 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2199 dest_addr = dst + 256; |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2200 } |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2201 dst = jmp(dst, dest_addr); |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2202 } else { |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2203 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2204 dst = call(dst, opts->native_addr); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2205 dst = jmp_r(dst, SCRATCH1); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2206 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2207 break; |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2208 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2209 m68k_disasm(inst, disasm_buf); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2210 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode); |
|
104
a0fdaa134964
Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Mike Pavone <pavone@retrodev.com>
parents:
102
diff
changeset
|
2211 exit(1); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2212 } |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2213 return dst; |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2214 } |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2215 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2216 code_ptr translate_m68k_jsr(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2217 { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2218 code_ptr dest_addr; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2219 uint8_t sec_reg; |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2220 uint32_t after; |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2221 uint32_t m68k_addr; |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2222 switch(inst->src.addr_mode) |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2223 { |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2224 case MODE_AREG_INDIRECT: |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2225 dst = cycles(dst, BUS*2); |
|
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2226 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D); |
|
81
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2227 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
6d231dbe75ab
Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents:
78
diff
changeset
|
2228 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2229 dst = call(dst, opts->write_32_highfirst); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2230 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2231 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2232 } else { |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2233 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2234 } |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2235 dst = call(dst, opts->native_addr); |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2236 dst = jmp_r(dst, SCRATCH1); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2237 break; |
|
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2238 case MODE_AREG_DISPLACE: |
|
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2239 dst = cycles(dst, BUS*2); |
|
187
8e138da572ab
Fix return address for areg displacement mode JSR
Mike Pavone <pavone@retrodev.com>
parents:
184
diff
changeset
|
2240 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
|
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2241 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2242 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2243 dst = call(dst, opts->write_32_highfirst); |
|
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2244 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2245 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2246 } else { |
|
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2247 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); |
|
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2248 } |
|
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2249 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2250 dst = call(dst, opts->native_addr); |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2251 dst = jmp_r(dst, SCRATCH1); |
|
174
a1c3ecb4823f
Implement areg displacement mode for jsr
Mike Pavone <pavone@retrodev.com>
parents:
173
diff
changeset
|
2252 break; |
|
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2253 case MODE_AREG_INDEX_DISP8: |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2254 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
|
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2255 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
|
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2256 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2257 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2258 dst = call(dst, opts->write_32_highfirst); |
|
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2259 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2260 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2261 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2262 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2263 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2264 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2265 if (inst->src.params.regs.sec & 1) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2266 if (inst->src.params.regs.sec & 0x10) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2267 if (opts->aregs[sec_reg] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2268 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2269 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2270 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2271 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2272 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2273 if (opts->dregs[sec_reg] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2274 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2275 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2276 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2277 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2278 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2279 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2280 if (inst->src.params.regs.sec & 0x10) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2281 if (opts->aregs[sec_reg] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2282 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2283 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2284 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2285 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2286 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2287 if (opts->dregs[sec_reg] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2288 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2289 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2290 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2291 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2292 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2293 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2294 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2295 if (inst->src.params.regs.displacement) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2296 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2297 } |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2298 dst = call(dst, opts->native_addr); |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2299 dst = jmp_r(dst, SCRATCH1); |
|
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2300 break; |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2301 case MODE_PC_DISPLACE: |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2302 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2303 dst = cycles(dst, 10); |
|
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2304 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2305 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2306 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2307 dst = call(dst, opts->write_32_highfirst); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2308 m68k_addr = inst->src.params.regs.displacement + inst->address + 2; |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2309 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2310 dest_addr = get_native_address(opts->gen.native_code_map, m68k_addr); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2311 if (!dest_addr) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2312 opts->gen.deferred = defer_address(opts->gen.deferred, m68k_addr, dst + 1); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2313 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
|
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2314 dest_addr = dst + 256; |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2315 } |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2316 dst = jmp(dst, dest_addr); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2317 } else { |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2318 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2319 dst = call(dst, opts->native_addr); |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2320 dst = jmp_r(dst, SCRATCH1); |
|
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2321 } |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2322 break; |
|
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2323 case MODE_PC_INDEX_DISP8: |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2324 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct |
|
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2325 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D); |
|
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2326 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2327 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2328 dst = call(dst, opts->write_32_highfirst); |
|
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2329 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2330 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2331 if (inst->src.params.regs.sec & 1) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2332 if (inst->src.params.regs.sec & 0x10) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2333 if (opts->aregs[sec_reg] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2334 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2335 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2336 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2337 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2338 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2339 if (opts->dregs[sec_reg] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2340 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2341 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2342 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2343 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2344 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2345 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2346 if (inst->src.params.regs.sec & 0x10) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2347 if (opts->aregs[sec_reg] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2348 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2349 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2350 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2351 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2352 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2353 if (opts->dregs[sec_reg] >= 0) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2354 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2355 } else { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2356 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2357 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2358 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2359 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2360 } |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2361 if (inst->src.params.regs.displacement) { |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2362 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); |
|
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2363 } |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2364 dst = call(dst, opts->native_addr); |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2365 dst = jmp_r(dst, SCRATCH1); |
|
110
a575808dd90b
Implement more address modes for jsr
Mike Pavone <pavone@retrodev.com>
parents:
107
diff
changeset
|
2366 break; |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2367 case MODE_ABSOLUTE: |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2368 case MODE_ABSOLUTE_SHORT: |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2369 //TODO: Add cycles in the right place relative to pushing the return address on the stack |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2370 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); |
|
119
ee19ddadb398
Fix return address pushed to stack for jsr
Mike Pavone <pavone@retrodev.com>
parents:
118
diff
changeset
|
2371 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2372 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2373 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2374 dst = call(dst, opts->write_32_highfirst); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2375 m68k_addr = inst->src.params.immed; |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2376 if ((m68k_addr & 0xFFFFFF) < 0x400000) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2377 dest_addr = get_native_address(opts->gen.native_code_map, m68k_addr); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2378 if (!dest_addr) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2379 opts->gen.deferred = defer_address(opts->gen.deferred, m68k_addr, dst + 1); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2380 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
|
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2381 dest_addr = dst + 256; |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2382 } |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2383 dst = jmp(dst, dest_addr); |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2384 } else { |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
2385 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2386 dst = call(dst, opts->native_addr); |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2387 dst = jmp_r(dst, SCRATCH1); |
|
155
94a65fb4e1c7
Don't use the native call stack for M68K calls by default
Mike Pavone <pavone@retrodev.com>
parents:
154
diff
changeset
|
2388 } |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2389 break; |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2390 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2391 m68k_disasm(inst, disasm_buf); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2392 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode); |
| 105 | 2393 exit(1); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2394 } |
|
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2395 return dst; |
|
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2396 } |
|
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2397 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2398 code_ptr translate_m68k_rts(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2399 { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2400 //TODO: Add cycles |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2401 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2402 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2403 dst = call(dst, opts->read_32); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
2404 dst = call(dst, opts->native_addr); |
|
541
a59ac6b4b5b5
Get rid of the native stack option the 68K core. Trying to make it work with code that messes with the stack is not worth the trouble.
Michael Pavone <pavone@retrodev.com>
parents:
540
diff
changeset
|
2405 dst = jmp_r(dst, SCRATCH1); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2406 return dst; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2407 } |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2408 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2409 code_ptr translate_m68k_dbcc(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2410 { |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2411 //best case duration |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2412 dst = cycles(dst, 10); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2413 code_ptr skip_loc = NULL; |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2414 //TODO: Check if COND_TRUE technically valid here even though |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2415 //it's basically a slow NOP |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2416 if (inst->extra.cond != COND_FALSE) { |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2417 uint8_t cond = CC_NZ; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2418 switch (inst->extra.cond) |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2419 { |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2420 case COND_HIGH: |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2421 cond = CC_Z; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2422 case COND_LOW_SAME: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2423 dst = flag_to_reg(dst, FLAG_Z, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2424 dst = or_flag_to_reg(dst, FLAG_C, SCRATCH1, opts); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2425 break; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2426 case COND_CARRY_CLR: |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2427 cond = CC_Z; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2428 case COND_CARRY_SET: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2429 dst = check_flag(dst, FLAG_C, opts); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2430 break; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2431 case COND_NOT_EQ: |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2432 cond = CC_Z; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2433 case COND_EQ: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2434 dst = check_flag(dst, FLAG_Z, opts); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2435 break; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2436 case COND_OVERF_CLR: |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2437 cond = CC_Z; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2438 case COND_OVERF_SET: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2439 dst = check_flag(dst, FLAG_V, opts); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2440 break; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2441 case COND_PLUS: |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2442 cond = CC_Z; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2443 case COND_MINUS: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2444 dst = check_flag(dst, FLAG_N, opts); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2445 break; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2446 case COND_GREATER_EQ: |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2447 cond = CC_Z; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2448 case COND_LESS: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2449 dst = cmp_flags(dst, FLAG_N, FLAG_V, opts); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2450 break; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2451 case COND_GREATER: |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2452 cond = CC_Z; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2453 case COND_LESS_EQ: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2454 dst = flag_to_reg(dst, FLAG_V, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2455 dst = xor_flag_to_reg(dst, FLAG_N, SCRATCH1, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2456 dst = or_flag_to_reg(dst, FLAG_Z, SCRATCH1, opts); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2457 break; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2458 } |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2459 skip_loc = dst + 1; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2460 dst = jcc(dst, cond, dst + 2); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2461 } |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2462 if (opts->dregs[inst->dst.params.regs.pri] >= 0) { |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2463 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2464 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2465 } else { |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2466 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2467 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2468 } |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2469 code_ptr loop_end_loc = dst+1; |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2470 dst = jcc(dst, CC_Z, dst+2); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2471 uint32_t after = inst->address + 2; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2472 code_ptr dest_addr = get_native_address(opts->gen.native_code_map, after + inst->src.params.immed); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2473 if (!dest_addr) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2474 opts->gen.deferred = defer_address(opts->gen.deferred, after + inst->src.params.immed, dst + 1); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2475 //dummy address to be replaced later, make sure it generates a 4-byte displacement |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2476 dest_addr = dst + 256; |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2477 } |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2478 dst = jmp(dst, dest_addr); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2479 *loop_end_loc = dst - (loop_end_loc+1); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2480 if (skip_loc) { |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2481 dst = cycles(dst, 2); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2482 *skip_loc = dst - (skip_loc+1); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2483 dst = cycles(dst, 2); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2484 } else { |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2485 dst = cycles(dst, 4); |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2486 } |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2487 return dst; |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2488 } |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2489 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2490 code_ptr translate_m68k_link(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2491 { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2492 int8_t reg = native_reg(&(inst->src), opts); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2493 //compensate for displacement word |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2494 dst = cycles(dst, BUS); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2495 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2496 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2497 if (reg >= 0) { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2498 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2499 } else { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2500 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2501 } |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2502 dst = call(dst, opts->write_32_highfirst); |
|
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2503 if (reg >= 0) { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2504 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2505 } else { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2506 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2507 } |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2508 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2509 //prefetch |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2510 dst = cycles(dst, BUS); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2511 return dst; |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2512 } |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2513 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2514 code_ptr translate_m68k_movep(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
| 172 | 2515 { |
| 2516 int8_t reg; | |
| 2517 dst = cycles(dst, BUS*2); | |
| 2518 if (inst->src.addr_mode == MODE_REG) { | |
| 2519 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { | |
| 2520 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); | |
| 2521 } else { | |
| 2522 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); | |
| 2523 } | |
| 2524 if (inst->dst.params.regs.displacement) { | |
| 2525 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D); | |
| 2526 } | |
| 2527 reg = native_reg(&(inst->src), opts); | |
| 2528 if (inst->extra.size == OPSIZE_LONG) { | |
| 2529 if (reg >= 0) { | |
| 2530 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
| 2531 dst = shr_ir(dst, 24, SCRATCH1, SZ_D); | |
| 2532 dst = push_r(dst, SCRATCH2); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2533 dst = call(dst, opts->write_8); |
| 172 | 2534 dst = pop_r(dst, SCRATCH2); |
| 2535 dst = mov_rr(dst, reg, SCRATCH1, SZ_D); | |
| 2536 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); | |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2537 |
| 172 | 2538 } else { |
| 2539 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+3, SCRATCH1, SZ_B); | |
| 2540 dst = push_r(dst, SCRATCH2); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2541 dst = call(dst, opts->write_8); |
| 172 | 2542 dst = pop_r(dst, SCRATCH2); |
| 2543 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+2, SCRATCH1, SZ_B); | |
| 2544 } | |
| 2545 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
| 2546 dst = push_r(dst, SCRATCH2); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2547 dst = call(dst, opts->write_8); |
| 172 | 2548 dst = pop_r(dst, SCRATCH2); |
| 2549 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
| 2550 } | |
| 2551 if (reg >= 0) { | |
| 2552 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
| 2553 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); | |
| 2554 dst = push_r(dst, SCRATCH2); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2555 dst = call(dst, opts->write_8); |
| 172 | 2556 dst = pop_r(dst, SCRATCH2); |
| 2557 dst = mov_rr(dst, reg, SCRATCH1, SZ_W); | |
| 2558 } else { | |
| 2559 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src))+1, SCRATCH1, SZ_B); | |
| 2560 dst = push_r(dst, SCRATCH2); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2561 dst = call(dst, opts->write_8); |
| 172 | 2562 dst = pop_r(dst, SCRATCH2); |
| 2563 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_B); | |
| 2564 } | |
| 2565 dst = add_ir(dst, 2, SCRATCH2, SZ_D); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2566 dst = call(dst, opts->write_8); |
| 172 | 2567 } else { |
| 2568 if (opts->aregs[inst->src.params.regs.pri] >= 0) { | |
| 2569 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); | |
| 2570 } else { | |
| 2571 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); | |
| 2572 } | |
| 2573 if (inst->src.params.regs.displacement) { | |
| 2574 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D); | |
| 2575 } | |
| 2576 reg = native_reg(&(inst->dst), opts); | |
| 2577 if (inst->extra.size == OPSIZE_LONG) { | |
| 2578 if (reg >= 0) { | |
| 2579 dst = push_r(dst, SCRATCH1); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2580 dst = call(dst, opts->read_8); |
| 172 | 2581 dst = shl_ir(dst, 24, SCRATCH1, SZ_D); |
| 2582 dst = mov_rr(dst, SCRATCH1, reg, SZ_D); | |
| 2583 dst = pop_r(dst, SCRATCH1); | |
| 2584 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
| 2585 dst = push_r(dst, SCRATCH1); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2586 dst = call(dst, opts->read_8); |
| 172 | 2587 dst = shl_ir(dst, 16, SCRATCH1, SZ_D); |
| 2588 dst = or_rr(dst, SCRATCH1, reg, SZ_D); | |
| 2589 } else { | |
| 2590 dst = push_r(dst, SCRATCH1); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2591 dst = call(dst, opts->read_8); |
| 172 | 2592 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+3, SZ_B); |
| 2593 dst = pop_r(dst, SCRATCH1); | |
| 2594 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
| 2595 dst = push_r(dst, SCRATCH1); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2596 dst = call(dst, opts->read_8); |
| 172 | 2597 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+2, SZ_B); |
| 2598 } | |
| 2599 dst = pop_r(dst, SCRATCH1); | |
| 2600 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
| 2601 } | |
| 2602 dst = push_r(dst, SCRATCH1); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2603 dst = call(dst, opts->read_8); |
| 172 | 2604 if (reg >= 0) { |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2605 |
| 172 | 2606 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
| 2607 dst = mov_rr(dst, SCRATCH1, reg, SZ_W); | |
| 2608 dst = pop_r(dst, SCRATCH1); | |
| 2609 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2610 dst = call(dst, opts->read_8); |
| 172 | 2611 dst = mov_rr(dst, SCRATCH1, reg, SZ_B); |
| 2612 } else { | |
| 2613 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst))+1, SZ_B); | |
| 2614 dst = pop_r(dst, SCRATCH1); | |
| 2615 dst = add_ir(dst, 2, SCRATCH1, SZ_D); | |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
2616 dst = call(dst, opts->read_8); |
| 172 | 2617 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_B); |
| 2618 } | |
| 2619 } | |
| 2620 return dst; | |
| 2621 } | |
| 2622 | |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2623 code_ptr translate_m68k_cmp(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2624 { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2625 uint8_t size = inst->extra.size; |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2626 x86_ea src_op, dst_op; |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2627 dst = translate_m68k_src(inst, &src_op, dst, opts); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2628 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2629 dst = push_r(dst, SCRATCH1); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2630 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2631 dst = pop_r(dst, SCRATCH2); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2632 src_op.base = SCRATCH2; |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2633 } else { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2634 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2635 if (inst->dst.addr_mode == MODE_AREG && size == OPSIZE_WORD) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2636 size = OPSIZE_LONG; |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2637 } |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2638 } |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2639 dst = cycles(dst, BUS); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2640 if (src_op.mode == MODE_REG_DIRECT) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2641 if (dst_op.mode == MODE_REG_DIRECT) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2642 dst = cmp_rr(dst, src_op.base, dst_op.base, size); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2643 } else { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2644 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2645 } |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2646 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2647 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2648 } else { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2649 if (dst_op.mode == MODE_REG_DIRECT) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2650 dst = cmp_ir(dst, src_op.disp, dst_op.base, size); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2651 } else { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2652 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2653 } |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2654 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2655 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2656 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2657 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2658 dst = set_flag_cond(dst, CC_O, FLAG_V, opts); |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2659 return dst; |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2660 } |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2661 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2662 typedef code_ptr (*shift_ir_t)(code_ptr out, uint8_t val, uint8_t dst, uint8_t size); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2663 typedef code_ptr (*shift_irdisp8_t)(code_ptr out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2664 typedef code_ptr (*shift_clr_t)(code_ptr out, uint8_t dst, uint8_t size); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2665 typedef code_ptr (*shift_clrdisp8_t)(code_ptr out, uint8_t dst_base, int8_t disp, uint8_t size); |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2666 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2667 code_ptr translate_shift(code_ptr dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2668 { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2669 code_ptr end_off = NULL; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2670 code_ptr nz_off = NULL; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2671 code_ptr z_off = NULL; |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2672 if (inst->src.addr_mode == MODE_UNUSED) { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2673 dst = cycles(dst, BUS); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2674 //Memory shift |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2675 dst = shift_ir(dst, 1, dst_op->base, SZ_W); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2676 } else { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2677 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2678 if (src_op->mode == MODE_IMMED) { |
| 207 | 2679 if (src_op->disp != 1 && inst->op == M68K_ASL) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2680 dst = set_flag(dst, 0, FLAG_V, opts); |
| 207 | 2681 for (int i = 0; i < src_op->disp; i++) { |
| 2682 if (dst_op->mode == MODE_REG_DIRECT) { | |
| 2683 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
| 2684 } else { | |
| 2685 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
| 2686 } | |
| 2687 //dst = setcc_r(dst, CC_O, FLAG_V); | |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2688 code_ptr after_flag_set = dst+1; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2689 dst = jcc(dst, CC_NO, dst+2); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2690 dst = set_flag(dst, 1, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2691 *after_flag_set = dst - (after_flag_set+1); |
| 207 | 2692 } |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2693 } else { |
| 207 | 2694 if (dst_op->mode == MODE_REG_DIRECT) { |
| 2695 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); | |
| 2696 } else { | |
| 2697 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); | |
| 2698 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2699 dst = set_flag_cond(dst, CC_O, FLAG_V, opts); |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2700 } |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2701 } else { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2702 if (src_op->base != RCX) { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2703 if (src_op->mode == MODE_REG_DIRECT) { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2704 dst = mov_rr(dst, src_op->base, RCX, SZ_B); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2705 } else { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2706 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2707 } |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2708 |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2709 } |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2710 dst = and_ir(dst, 63, RCX, SZ_D); |
| 207 | 2711 nz_off = dst+1; |
| 2712 dst = jcc(dst, CC_NZ, dst+2); | |
| 2713 //Flag behavior for shift count of 0 is different for x86 than 68K | |
| 2714 if (dst_op->mode == MODE_REG_DIRECT) { | |
| 2715 dst = cmp_ir(dst, 0, dst_op->base, inst->extra.size); | |
| 2716 } else { | |
| 2717 dst = cmp_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
| 2718 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2719 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2720 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2721 dst = set_flag(dst, 0, FLAG_C, opts); |
| 207 | 2722 //For other instructions, this flag will be set below |
| 2723 if (inst->op == M68K_ASL) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2724 dst = set_flag(dst, 0, FLAG_V, opts); |
| 207 | 2725 } |
| 2726 z_off = dst+1; | |
| 2727 dst = jmp(dst, dst+2); | |
| 2728 *nz_off = dst - (nz_off + 1); | |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2729 //add 2 cycles for every bit shifted |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2730 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2731 dst = add_rr(dst, RCX, CYCLES, SZ_D); |
| 207 | 2732 if (inst->op == M68K_ASL) { |
| 2733 //ASL has Overflow flag behavior that depends on all of the bits shifted through the MSB | |
| 2734 //Easiest way to deal with this is to shift one bit at a time | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2735 dst = set_flag(dst, 0, FLAG_V, opts); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2736 code_ptr loop_start = dst; |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2737 if (dst_op->mode == MODE_REG_DIRECT) { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2738 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2739 } else { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2740 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2741 } |
| 207 | 2742 //dst = setcc_r(dst, CC_O, FLAG_V); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2743 code_ptr after_flag_set = dst+1; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2744 dst = jcc(dst, CC_NO, dst+2); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2745 dst = set_flag(dst, 1, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2746 *after_flag_set = dst - (after_flag_set+1); |
| 207 | 2747 dst = loop(dst, loop_start); |
| 2748 } else { | |
| 2749 //x86 shifts modulo 32 for operand sizes less than 64-bits | |
| 2750 //but M68K shifts modulo 64, so we need to check for large shifts here | |
| 2751 dst = cmp_ir(dst, 32, RCX, SZ_B); | |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2752 code_ptr norm_shift_off = dst + 1; |
| 207 | 2753 dst = jcc(dst, CC_L, dst+2); |
| 2754 if (special) { | |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2755 code_ptr after_flag_set = NULL; |
| 207 | 2756 if (inst->extra.size == OPSIZE_LONG) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2757 code_ptr neq_32_off = dst + 1; |
| 207 | 2758 dst = jcc(dst, CC_NZ, dst+2); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2759 |
| 207 | 2760 //set the carry bit to the lsb |
| 2761 if (dst_op->mode == MODE_REG_DIRECT) { | |
| 2762 dst = special(dst, 1, dst_op->base, SZ_D); | |
| 2763 } else { | |
| 2764 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D); | |
| 2765 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2766 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2767 after_flag_set = dst+1; |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2768 dst = jmp(dst, dst+2); |
| 207 | 2769 *neq_32_off = dst - (neq_32_off+1); |
| 2770 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2771 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2772 if (after_flag_set) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2773 *after_flag_set = dst - (after_flag_set+1); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2774 } |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2775 dst = set_flag(dst, 1, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2776 dst = set_flag(dst, 0, FLAG_N, opts); |
| 207 | 2777 if (dst_op->mode == MODE_REG_DIRECT) { |
| 2778 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size); | |
| 2779 } else { | |
| 2780 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size); | |
| 2781 } | |
| 2782 } else { | |
| 2783 if (dst_op->mode == MODE_REG_DIRECT) { | |
| 2784 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size); | |
| 2785 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size); | |
| 2786 } else { | |
| 2787 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size); | |
| 2788 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size); | |
| 2789 } | |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2790 |
| 207 | 2791 } |
| 2792 end_off = dst+1; | |
| 2793 dst = jmp(dst, dst+2); | |
| 2794 *norm_shift_off = dst - (norm_shift_off+1); | |
| 2795 if (dst_op->mode == MODE_REG_DIRECT) { | |
| 2796 dst = shift_clr(dst, dst_op->base, inst->extra.size); | |
| 2797 } else { | |
| 2798 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size); | |
| 2799 } | |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2800 } |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2801 } |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
2802 |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2803 } |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2804 if (!special && end_off) { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2805 *end_off = dst - (end_off + 1); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2806 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2807 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2808 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2809 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2810 if (special && end_off) { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2811 *end_off = dst - (end_off + 1); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2812 } |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2813 //set X flag to same as C flag |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2814 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2815 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2816 } else { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2817 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2818 } |
| 207 | 2819 if (z_off) { |
| 2820 *z_off = dst - (z_off + 1); | |
| 2821 } | |
|
219
8d3c16071559
Fix overflow flag behavior for lsl/lsr/asr
Mike Pavone <pavone@retrodev.com>
parents:
218
diff
changeset
|
2822 if (inst->op != M68K_ASL) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2823 dst = set_flag(dst, 0, FLAG_V, opts); |
| 207 | 2824 } |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2825 if (inst->src.addr_mode == MODE_UNUSED) { |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2826 dst = m68k_save_result(inst, dst, opts); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2827 } |
| 66 | 2828 return dst; |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2829 } |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
2830 |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2831 #define BIT_SUPERVISOR 5 |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
2832 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2833 code_ptr translate_m68k(code_ptr dst, m68kinst * inst, x86_68k_options * opts) |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2834 { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2835 code_ptr end_off, zero_off, norm_off; |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
2836 uint8_t dst_reg; |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
2837 dst = check_cycles_int(dst, inst->address, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2838 if (inst->op == M68K_MOVE) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2839 return translate_m68k_move(dst, inst, opts); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2840 } else if(inst->op == M68K_LEA) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2841 return translate_m68k_lea(dst, inst, opts); |
|
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2842 } else if(inst->op == M68K_PEA) { |
|
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
113
diff
changeset
|
2843 return translate_m68k_pea(dst, inst, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2844 } else if(inst->op == M68K_BSR) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2845 return translate_m68k_bsr(dst, inst, opts); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2846 } else if(inst->op == M68K_BCC) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2847 return translate_m68k_bcc(dst, inst, opts); |
|
53
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2848 } else if(inst->op == M68K_JMP) { |
|
44e661913a51
Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents:
52
diff
changeset
|
2849 return translate_m68k_jmp(dst, inst, opts); |
|
76
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2850 } else if(inst->op == M68K_JSR) { |
|
187c65f40a64
Implement JSR for some addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
74
diff
changeset
|
2851 return translate_m68k_jsr(dst, inst, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2852 } else if(inst->op == M68K_RTS) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2853 return translate_m68k_rts(dst, inst, opts); |
|
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2854 } else if(inst->op == M68K_DBCC) { |
|
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
19
diff
changeset
|
2855 return translate_m68k_dbcc(dst, inst, opts); |
|
52
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2856 } else if(inst->op == M68K_CLR) { |
|
f02ba3808757
Implement CLR, minor refactor of register offset calculation in context struct
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2857 return translate_m68k_clr(dst, inst, opts); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2858 } else if(inst->op == M68K_MOVEM) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
2859 return translate_m68k_movem(dst, inst, opts); |
|
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2860 } else if(inst->op == M68K_LINK) { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
2861 return translate_m68k_link(dst, inst, opts); |
|
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2862 } else if(inst->op == M68K_EXT) { |
|
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
2863 return translate_m68k_ext(dst, inst, opts); |
| 112 | 2864 } else if(inst->op == M68K_SCC) { |
| 2865 return translate_m68k_scc(dst, inst, opts); | |
| 172 | 2866 } else if(inst->op == M68K_MOVEP) { |
| 2867 return translate_m68k_movep(dst, inst, opts); | |
|
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
175
diff
changeset
|
2868 } else if(inst->op == M68K_INVALID) { |
|
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2869 if (inst->src.params.immed == 0x7100) { |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2870 return retn(dst); |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
2871 } |
|
559
6b248602ab84
blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2872 dst = mov_ir(dst, inst->address, SCRATCH2, SZ_D); |
|
6b248602ab84
blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2873 #ifdef X86_32 |
|
6b248602ab84
blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2874 dst = push_r(dst, CONTEXT); |
|
6b248602ab84
blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2875 dst = push_r(dst, SCRATCH2); |
|
6b248602ab84
blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents:
558
diff
changeset
|
2876 #endif |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2877 return call(dst, (code_ptr)m68k_invalid); |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2878 } else if(inst->op == M68K_CMP) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2879 return translate_m68k_cmp(dst, inst, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2880 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2881 x86_ea src_op, dst_op; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2882 if (inst->src.addr_mode != MODE_UNUSED) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2883 dst = translate_m68k_src(inst, &src_op, dst, opts); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2884 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2885 if (inst->dst.addr_mode != MODE_UNUSED) { |
|
92
c3d034e076ee
Fix some bugs in emulation of CLR
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
2886 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2887 } |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2888 uint8_t size; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2889 switch(inst->op) |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2890 { |
|
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2891 case M68K_ABCD: |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2892 if (src_op.base != SCRATCH2) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2893 if (src_op.mode == MODE_REG_DIRECT) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2894 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2895 } else { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2896 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2897 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2898 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2899 if (dst_op.base != SCRATCH1) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2900 if (dst_op.mode == MODE_REG_DIRECT) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2901 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2902 } else { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2903 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2904 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2905 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2906 dst = flag_to_carry(dst, FLAG_X, opts); |
|
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2907 dst = jcc(dst, CC_NC, dst+5); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2908 dst = add_ir(dst, 1, SCRATCH1, SZ_B); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2909 dst = call(dst, (code_ptr)bcd_add); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2910 dst = reg_to_flag(dst, CH, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2911 dst = reg_to_flag(dst, CH, FLAG_X, opts); |
|
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2912 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2913 dst = jcc(dst, CC_Z, dst+4); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2914 dst = set_flag(dst, 0, FLAG_Z, opts); |
|
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2915 if (dst_op.base != SCRATCH1) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2916 if (dst_op.mode == MODE_REG_DIRECT) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2917 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2918 } else { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2919 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2920 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2921 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2922 dst = m68k_save_result(inst, dst, opts); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
2923 break; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2924 case M68K_ADD: |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2925 dst = cycles(dst, BUS); |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2926 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2927 if (src_op.mode == MODE_REG_DIRECT) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2928 if (dst_op.mode == MODE_REG_DIRECT) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2929 dst = add_rr(dst, src_op.base, dst_op.base, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2930 } else { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2931 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2932 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2933 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2934 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2935 } else { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2936 if (dst_op.mode == MODE_REG_DIRECT) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2937 dst = add_ir(dst, src_op.disp, dst_op.base, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2938 } else { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
2939 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2940 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2941 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2942 if (inst->dst.addr_mode != MODE_AREG) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2943 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2944 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2945 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2946 dst = set_flag_cond(dst, CC_O, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2947 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2948 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2949 } else { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2950 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2951 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
2952 } |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2953 dst = m68k_save_result(inst, dst, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
2954 break; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2955 case M68K_ADDX: { |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2956 dst = cycles(dst, BUS); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2957 dst = flag_to_carry(dst, FLAG_X, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2958 if (src_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2959 if (dst_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2960 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2961 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2962 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2963 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2964 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2965 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2966 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2967 if (dst_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2968 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2969 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2970 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2971 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2972 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2973 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2974 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
2975 code_ptr after_flag_set = dst+1; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2976 dst = jcc(dst, CC_Z, dst+2); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2977 dst = set_flag(dst, 0, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2978 *after_flag_set = dst - (after_flag_set+1); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2979 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2980 dst = set_flag_cond(dst, CC_O, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2981 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2982 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2983 } else { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2984 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2985 } |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2986 dst = m68k_save_result(inst, dst, opts); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
2987 break; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
2988 } |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2989 case M68K_AND: |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2990 dst = cycles(dst, BUS); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2991 if (src_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2992 if (dst_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2993 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2994 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2995 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2996 } |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2997 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2998 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2999 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3000 if (dst_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3001 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3002 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3003 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3004 } |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3005 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3006 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3007 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3008 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3009 dst = set_flag(dst, 0, FLAG_V, opts); |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3010 dst = m68k_save_result(inst, dst, opts); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3011 break; |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3012 case M68K_ANDI_CCR: |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3013 case M68K_ANDI_SR: |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3014 dst = cycles(dst, 20); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3015 //TODO: If ANDI to SR, trap if not in supervisor mode |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3016 if (!(inst->src.params.immed & 0x1)) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3017 dst = set_flag(dst, 0, FLAG_C, opts); |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3018 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3019 if (!(inst->src.params.immed & 0x2)) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3020 dst = set_flag(dst, 0, FLAG_V, opts); |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3021 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3022 if (!(inst->src.params.immed & 0x4)) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3023 dst = set_flag(dst, 0, FLAG_Z, opts); |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3024 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3025 if (!(inst->src.params.immed & 0x8)) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3026 dst = set_flag(dst, 0, FLAG_N, opts); |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3027 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3028 if (!(inst->src.params.immed & 0x10)) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3029 dst = set_flag(dst, 0, FLAG_X, opts); |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3030 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3031 if (inst->op == M68K_ANDI_SR) { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3032 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3033 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3034 //leave supervisor mode |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3035 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3036 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3037 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3038 } |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3039 if (inst->src.params.immed & 0x700) { |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3040 dst = call(dst, opts->do_sync); |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3041 } |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3042 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3043 break; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3044 case M68K_ASL: |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3045 case M68K_LSL: |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
3046 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
3047 break; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3048 case M68K_ASR: |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
3049 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
3050 break; |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3051 case M68K_LSR: |
|
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
3052 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); |
|
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
49
diff
changeset
|
3053 break; |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3054 case M68K_BCHG: |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3055 case M68K_BCLR: |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3056 case M68K_BSET: |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3057 case M68K_BTST: |
|
457
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
3058 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : ( |
|
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
3059 inst->op == M68K_BTST ? 6 : (inst->op == M68K_BCLR ? 10 : 8)) |
|
6a315728fede
Fix bit instruction timing
Mike Pavone <pavone@retrodev.com>
parents:
447
diff
changeset
|
3060 ); |
| 67 | 3061 if (src_op.mode == MODE_IMMED) { |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3062 if (inst->extra.size == OPSIZE_BYTE) { |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3063 src_op.disp &= 0x7; |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3064 } |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3065 if (inst->op == M68K_BTST) { |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3066 if (dst_op.mode == MODE_REG_DIRECT) { |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3067 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3068 } else { |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3069 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3070 } |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3071 } else if (inst->op == M68K_BSET) { |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3072 if (dst_op.mode == MODE_REG_DIRECT) { |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3073 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3074 } else { |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3075 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3076 } |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3077 } else if (inst->op == M68K_BCLR) { |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3078 if (dst_op.mode == MODE_REG_DIRECT) { |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3079 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3080 } else { |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3081 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3082 } |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3083 } else { |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3084 if (dst_op.mode == MODE_REG_DIRECT) { |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3085 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3086 } else { |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3087 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3088 } |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3089 } |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3090 } else { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3091 if (src_op.mode == MODE_REG_DISPLACE8 || (inst->dst.addr_mode != MODE_REG && src_op.base != SCRATCH1 && src_op.base != SCRATCH2)) { |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3092 if (dst_op.base == SCRATCH1) { |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3093 dst = push_r(dst, SCRATCH2); |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3094 if (src_op.mode == MODE_REG_DIRECT) { |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3095 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3096 } else { |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3097 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3098 } |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3099 src_op.base = SCRATCH2; |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3100 } else { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3101 if (src_op.mode == MODE_REG_DIRECT) { |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3102 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3103 } else { |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3104 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3105 } |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3106 src_op.base = SCRATCH1; |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3107 } |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3108 } |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3109 uint8_t size = inst->extra.size; |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3110 if (dst_op.mode == MODE_REG_DISPLACE8) { |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3111 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) { |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3112 if (src_op.mode == MODE_REG_DIRECT) { |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3113 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D); |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3114 } else { |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3115 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3116 src_op.mode = MODE_REG_DIRECT; |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3117 } |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3118 src_op.base = SCRATCH1; |
|
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3119 } |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3120 //b### with register destination is modulo 32 |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3121 //x86 with a memory destination isn't modulo anything |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3122 //so use an and here to force the value to be modulo 32 |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3123 dst = and_ir(dst, 31, SCRATCH1, SZ_D); |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3124 } else if(inst->dst.addr_mode != MODE_REG) { |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3125 //b### with memory destination is modulo 8 |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3126 //x86-64 doesn't support 8-bit bit operations |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3127 //so we fake it by forcing the bit number to be modulo 8 |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3128 dst = and_ir(dst, 7, src_op.base, SZ_D); |
|
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3129 size = SZ_D; |
|
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
152
diff
changeset
|
3130 } |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3131 if (inst->op == M68K_BTST) { |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3132 if (dst_op.mode == MODE_REG_DIRECT) { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3133 dst = bt_rr(dst, src_op.base, dst_op.base, size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3134 } else { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3135 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3136 } |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3137 } else if (inst->op == M68K_BSET) { |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3138 if (dst_op.mode == MODE_REG_DIRECT) { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3139 dst = bts_rr(dst, src_op.base, dst_op.base, size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3140 } else { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3141 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3142 } |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3143 } else if (inst->op == M68K_BCLR) { |
|
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3144 if (dst_op.mode == MODE_REG_DIRECT) { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3145 dst = btr_rr(dst, src_op.base, dst_op.base, size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3146 } else { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3147 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3148 } |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3149 } else { |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3150 if (dst_op.mode == MODE_REG_DIRECT) { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3151 dst = btc_rr(dst, src_op.base, dst_op.base, size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3152 } else { |
|
221
71f6b76639db
Fix modulo on bit operations with a memory destination
Mike Pavone <pavone@retrodev.com>
parents:
219
diff
changeset
|
3153 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
|
123
bd3858121ab0
Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
122
diff
changeset
|
3154 } |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3155 } |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3156 if (src_op.base == SCRATCH2) { |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3157 dst = pop_r(dst, SCRATCH2); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3158 } |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3159 } |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3160 //x86 sets the carry flag to the value of the bit tested |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3161 //68K sets the zero flag to the complement of the bit tested |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3162 dst = set_flag_cond(dst, CC_NC, FLAG_Z, opts); |
|
128
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3163 if (inst->op != M68K_BTST) { |
|
fe598ffd85ce
Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Mike Pavone <pavone@retrodev.com>
parents:
126
diff
changeset
|
3164 dst = m68k_save_result(inst, dst, opts); |
|
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3165 } |
|
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
59
diff
changeset
|
3166 break; |
|
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3167 case M68K_CHK: |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3168 { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3169 dst = cycles(dst, 6); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3170 if (dst_op.mode == MODE_REG_DIRECT) { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3171 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3172 } else { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3173 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3174 } |
|
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3175 uint32_t isize; |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3176 switch(inst->src.addr_mode) |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3177 { |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3178 case MODE_AREG_DISPLACE: |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3179 case MODE_AREG_INDEX_DISP8: |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3180 case MODE_ABSOLUTE_SHORT: |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3181 case MODE_PC_INDEX_DISP8: |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3182 case MODE_PC_DISPLACE: |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3183 case MODE_IMMEDIATE: |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3184 isize = 4; |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3185 break; |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3186 case MODE_ABSOLUTE: |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3187 isize = 6; |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3188 break; |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3189 default: |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3190 isize = 2; |
|
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3191 } |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3192 code_ptr passed = dst+1; |
|
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3193 dst = jcc(dst, CC_GE, dst+2); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3194 dst = set_flag(dst, 1, FLAG_N, opts); |
|
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3195 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
|
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3196 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); |
|
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3197 dst = jmp(dst, opts->trap); |
|
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3198 *passed = dst - (passed+1); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3199 if (dst_op.mode == MODE_REG_DIRECT) { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3200 if (src_op.mode == MODE_REG_DIRECT) { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3201 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3202 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3203 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3204 } else { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3205 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3206 } |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3207 } else if(dst_op.mode == MODE_REG_DISPLACE8) { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3208 if (src_op.mode == MODE_REG_DIRECT) { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3209 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3210 } else { |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3211 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3212 } |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3213 } |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3214 passed = dst+1; |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3215 dst = jcc(dst, CC_LE, dst+2); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3216 dst = set_flag(dst, 0, FLAG_N, opts); |
|
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3217 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); |
|
324
4f2711899866
Fix retrun address calculation for CHK exceptions
Mike Pavone <pavone@retrodev.com>
parents:
321
diff
changeset
|
3218 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); |
|
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3219 dst = jmp(dst, opts->trap); |
|
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3220 *passed = dst - (passed+1); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3221 dst = cycles(dst, 4); |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3222 break; |
|
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
3223 } |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3224 case M68K_DIVS: |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3225 case M68K_DIVU: |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3226 { |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3227 //TODO: cycle exact division |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3228 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3229 dst = set_flag(dst, 0, FLAG_C, opts); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3230 dst = push_r(dst, RDX); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3231 dst = push_r(dst, RAX); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3232 if (dst_op.mode == MODE_REG_DIRECT) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3233 dst = mov_rr(dst, dst_op.base, RAX, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3234 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3235 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3236 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3237 if (src_op.mode == MODE_IMMED) { |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3238 dst = mov_ir(dst, (src_op.disp & 0x8000) && inst->op == M68K_DIVS ? src_op.disp | 0xFFFF0000 : src_op.disp, SCRATCH2, SZ_D); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3239 } else if (src_op.mode == MODE_REG_DIRECT) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3240 if (inst->op == M68K_DIVS) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3241 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3242 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3243 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3244 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3245 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3246 if (inst->op == M68K_DIVS) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3247 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3248 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3249 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3250 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3251 } |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3252 dst = cmp_ir(dst, 0, SCRATCH2, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3253 code_ptr not_zero = dst+1; |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3254 dst = jcc(dst, CC_NZ, dst+2); |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3255 dst = pop_r(dst, RAX); |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3256 dst = pop_r(dst, RDX); |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3257 dst = mov_ir(dst, VECTOR_INT_DIV_ZERO, SCRATCH2, SZ_D); |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3258 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
|
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
3259 dst = jmp(dst, opts->trap); |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3260 *not_zero = dst - (not_zero+1); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3261 if (inst->op == M68K_DIVS) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3262 dst = cdq(dst); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3263 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3264 dst = xor_rr(dst, RDX, RDX, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3265 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3266 if (inst->op == M68K_DIVS) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3267 dst = idiv_r(dst, SCRATCH2, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3268 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3269 dst = div_r(dst, SCRATCH2, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3270 } |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3271 code_ptr skip_sec_check; |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3272 if (inst->op == M68K_DIVS) { |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3273 dst = cmp_ir(dst, 0x8000, RAX, SZ_D); |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3274 skip_sec_check = dst + 1; |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3275 dst = jcc(dst, CC_GE, dst+2); |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3276 dst = cmp_ir(dst, -0x8000, RAX, SZ_D); |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3277 norm_off = dst+1; |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3278 dst = jcc(dst, CC_L, dst+2); |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3279 } else { |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3280 dst = cmp_ir(dst, 0x10000, RAX, SZ_D); |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3281 norm_off = dst+1; |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3282 dst = jcc(dst, CC_NC, dst+2); |
|
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3283 } |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3284 if (dst_op.mode == MODE_REG_DIRECT) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3285 dst = mov_rr(dst, RDX, dst_op.base, SZ_W); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3286 dst = shl_ir(dst, 16, dst_op.base, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3287 dst = mov_rr(dst, RAX, dst_op.base, SZ_W); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3288 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3289 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3290 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3291 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3292 } |
|
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3293 dst = cmp_ir(dst, 0, RAX, SZ_W); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3294 dst = pop_r(dst, RAX); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3295 dst = pop_r(dst, RDX); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3296 dst = set_flag(dst, 0, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3297 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3298 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3299 end_off = dst+1; |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3300 dst = jmp(dst, dst+2); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3301 *norm_off = dst - (norm_off + 1); |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3302 if (inst->op == M68K_DIVS) { |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3303 *skip_sec_check = dst - (skip_sec_check+1); |
|
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3304 } |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3305 dst = pop_r(dst, RAX); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3306 dst = pop_r(dst, RDX); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3307 dst = set_flag(dst, 1, FLAG_V, opts); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3308 *end_off = dst - (end_off + 1); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3309 break; |
|
228
1ed81ef2a3a2
Fix overflow detection in divs. Fix negative immediate source for divs
Mike Pavone <pavone@retrodev.com>
parents:
226
diff
changeset
|
3310 } |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3311 case M68K_EOR: |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3312 dst = cycles(dst, BUS); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3313 if (src_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3314 if (dst_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3315 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3316 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3317 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3318 } |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3319 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3320 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3321 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3322 if (dst_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3323 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3324 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3325 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3326 } |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3327 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3328 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3329 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3330 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3331 dst = set_flag(dst, 0, FLAG_V, opts); |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3332 dst = m68k_save_result(inst, dst, opts); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3333 break; |
| 171 | 3334 case M68K_EORI_CCR: |
| 3335 case M68K_EORI_SR: | |
| 3336 dst = cycles(dst, 20); | |
| 3337 //TODO: If ANDI to SR, trap if not in supervisor mode | |
| 3338 if (inst->src.params.immed & 0x1) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3339 dst = xor_flag(dst, 1, FLAG_C, opts); |
| 171 | 3340 } |
| 3341 if (inst->src.params.immed & 0x2) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3342 dst = xor_flag(dst, 1, FLAG_V, opts); |
| 171 | 3343 } |
| 3344 if (inst->src.params.immed & 0x4) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3345 dst = xor_flag(dst, 1, FLAG_Z, opts); |
| 171 | 3346 } |
| 3347 if (inst->src.params.immed & 0x8) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3348 dst = xor_flag(dst, 1, FLAG_N, opts); |
| 171 | 3349 } |
| 3350 if (inst->src.params.immed & 0x10) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3351 dst = xor_flag(dst, 1, FLAG_X, opts); |
| 171 | 3352 } |
| 3353 if (inst->op == M68K_ORI_SR) { | |
| 3354 dst = xor_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); | |
| 3355 if (inst->src.params.immed & 0x700) { | |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3356 dst = call(dst, opts->do_sync); |
| 171 | 3357 } |
| 3358 } | |
| 3359 break; | |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3360 case M68K_EXG: |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3361 dst = cycles(dst, 6); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3362 if (dst_op.mode == MODE_REG_DIRECT) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3363 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3364 if (src_op.mode == MODE_REG_DIRECT) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3365 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3366 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3367 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3368 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3369 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3370 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3371 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3372 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3373 if (src_op.mode == MODE_REG_DIRECT) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3374 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3375 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3376 } else { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3377 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3378 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3379 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3380 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3381 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3382 break; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3383 case M68K_ILLEGAL: |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3384 dst = call(dst, opts->gen.save_context); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3385 #ifdef X86_64 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3386 dst = mov_rr(dst, CONTEXT, RDI, SZ_PTR); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3387 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3388 dst = push_r(dst, CONTEXT); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3389 #endif |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3390 dst = call(dst, (code_ptr)print_regs_exit); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3391 break; |
| 105 | 3392 case M68K_MOVE_FROM_SR: |
| 3393 //TODO: Trap if not in system mode | |
|
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
3394 dst = call(dst, opts->get_sr); |
| 105 | 3395 if (dst_op.mode == MODE_REG_DIRECT) { |
| 3396 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W); | |
| 3397 } else { | |
| 3398 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W); | |
| 3399 } | |
| 3400 dst = m68k_save_result(inst, dst, opts); | |
| 3401 break; | |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3402 case M68K_MOVE_CCR: |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3403 case M68K_MOVE_SR: |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3404 //TODO: Privilege check for MOVE to SR |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3405 if (src_op.mode == MODE_IMMED) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3406 dst = set_flag(dst, src_op.disp & 0x1, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3407 dst = set_flag(dst, (src_op.disp >> 1) & 0x1, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3408 dst = set_flag(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3409 dst = set_flag(dst, (src_op.disp >> 3) & 0x1, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3410 dst = set_flag(dst, (src_op.disp >> 4) & 0x1, FLAG_X, opts); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3411 if (inst->op == M68K_MOVE_SR) { |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3412 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3413 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3414 //leave supervisor mode |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3415 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3416 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3417 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3418 } |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3419 dst = call(dst, opts->do_sync); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3420 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3421 dst = cycles(dst, 12); |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3422 } else { |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3423 if (src_op.base != SCRATCH1) { |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3424 if (src_op.mode == MODE_REG_DIRECT) { |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3425 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3426 } else { |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3427 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W); |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3428 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3429 } |
|
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
3430 dst = call(dst, inst->op == M68K_MOVE_SR ? opts->set_sr : opts->set_ccr); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3431 dst = cycles(dst, 12); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3432 |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3433 } |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
3434 break; |
|
73
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3435 case M68K_MOVE_USP: |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3436 dst = cycles(dst, BUS); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3437 //TODO: Trap if not in supervisor mode |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3438 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3439 if (inst->src.addr_mode == MODE_UNUSED) { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3440 if (dst_op.mode == MODE_REG_DIRECT) { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3441 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3442 } else { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3443 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3444 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3445 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3446 } else { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3447 if (src_op.mode == MODE_REG_DIRECT) { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3448 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3449 } else { |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3450 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3451 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3452 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3453 } |
|
8da611e69b32
Implement a couple of supervisor instructions
Mike Pavone <pavone@retrodev.com>
parents:
71
diff
changeset
|
3454 break; |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3455 //case M68K_MOVEP: |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3456 case M68K_MULS: |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3457 case M68K_MULU: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3458 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3459 if (src_op.mode == MODE_IMMED) { |
|
223
17534fb7c4f5
Fix muls with a negative immediate source.
Mike Pavone <pavone@retrodev.com>
parents:
221
diff
changeset
|
3460 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : ((src_op.disp & 0x8000) ? src_op.disp | 0xFFFF0000 : src_op.disp), SCRATCH1, SZ_D); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3461 } else if (src_op.mode == MODE_REG_DIRECT) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3462 if (inst->op == M68K_MULS) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3463 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3464 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3465 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3466 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3467 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3468 if (inst->op == M68K_MULS) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3469 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3470 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3471 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3472 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3473 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3474 if (dst_op.mode == MODE_REG_DIRECT) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3475 dst_reg = dst_op.base; |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3476 if (inst->op == M68K_MULS) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3477 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3478 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3479 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3480 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3481 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3482 dst_reg = SCRATCH2; |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3483 if (inst->op == M68K_MULS) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3484 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3485 } else { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3486 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3487 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3488 } |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3489 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3490 if (dst_op.mode == MODE_REG_DISPLACE8) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3491 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3492 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3493 dst = set_flag(dst, 0, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3494 dst = set_flag(dst, 0, FLAG_C, opts); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3495 dst = cmp_ir(dst, 0, dst_reg, SZ_D); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3496 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3497 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3498 break; |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
3499 //case M68K_NBCD: |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3500 case M68K_NEG: |
| 173 | 3501 dst = cycles(dst, BUS); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3502 if (dst_op.mode == MODE_REG_DIRECT) { |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3503 dst = neg_r(dst, dst_op.base, inst->extra.size); |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3504 } else { |
|
165
62b152811bae
Fix certain address modes with lea when the destination is not a native register
Mike Pavone <pavone@retrodev.com>
parents:
162
diff
changeset
|
3505 dst = neg_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3506 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3507 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3508 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3509 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3510 dst = set_flag_cond(dst, CC_O, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3511 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3512 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3513 } else { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3514 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3515 } |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3516 dst = m68k_save_result(inst, dst, opts); |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3517 break; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3518 case M68K_NEGX: { |
| 173 | 3519 dst = cycles(dst, BUS); |
| 3520 if (dst_op.mode == MODE_REG_DIRECT) { | |
| 3521 if (dst_op.base == SCRATCH1) { | |
| 3522 dst = push_r(dst, SCRATCH2); | |
| 3523 dst = xor_rr(dst, SCRATCH2, SCRATCH2, inst->extra.size); | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3524 dst = flag_to_carry(dst, FLAG_X, opts); |
| 173 | 3525 dst = sbb_rr(dst, dst_op.base, SCRATCH2, inst->extra.size); |
| 3526 dst = mov_rr(dst, SCRATCH2, dst_op.base, inst->extra.size); | |
| 3527 dst = pop_r(dst, SCRATCH2); | |
| 3528 } else { | |
| 3529 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3530 dst = flag_to_carry(dst, FLAG_X, opts); |
| 173 | 3531 dst = sbb_rr(dst, dst_op.base, SCRATCH1, inst->extra.size); |
| 3532 dst = mov_rr(dst, SCRATCH1, dst_op.base, inst->extra.size); | |
| 3533 } | |
| 3534 } else { | |
| 3535 dst = xor_rr(dst, SCRATCH1, SCRATCH1, inst->extra.size); | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3536 dst = flag_to_carry(dst, FLAG_X, opts); |
| 173 | 3537 dst = sbb_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size); |
| 3538 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3539 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3540 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3541 code_ptr after_flag_set = dst+1; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3542 dst = jcc(dst, CC_Z, dst+2); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3543 dst = set_flag(dst, 0, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3544 *after_flag_set = dst - (after_flag_set+1); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3545 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3546 dst = set_flag_cond(dst, CC_O, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3547 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3548 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3549 } else { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3550 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3551 } |
| 173 | 3552 dst = m68k_save_result(inst, dst, opts); |
| 3553 break; | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3554 } |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3555 case M68K_NOP: |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3556 dst = cycles(dst, BUS); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3557 break; |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3558 case M68K_NOT: |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3559 if (dst_op.mode == MODE_REG_DIRECT) { |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3560 dst = not_r(dst, dst_op.base, inst->extra.size); |
|
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3561 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3562 } else { |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3563 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
|
209
922b59c09259
Flag fixes for div, negx and not
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
3564 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3565 } |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3566 |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3567 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3568 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3569 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3570 dst = set_flag(dst, 0, FLAG_V, opts); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3571 dst = m68k_save_result(inst, dst, opts); |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3572 break; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3573 case M68K_OR: |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3574 dst = cycles(dst, BUS); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3575 if (src_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3576 if (dst_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3577 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3578 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3579 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3580 } |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3581 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3582 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3583 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3584 if (dst_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3585 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3586 } else { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3587 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3588 } |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3589 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3590 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3591 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3592 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3593 dst = set_flag(dst, 0, FLAG_V, opts); |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3594 dst = m68k_save_result(inst, dst, opts); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3595 break; |
| 106 | 3596 case M68K_ORI_CCR: |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3597 case M68K_ORI_SR: |
| 106 | 3598 dst = cycles(dst, 20); |
| 3599 //TODO: If ANDI to SR, trap if not in supervisor mode | |
| 3600 if (inst->src.params.immed & 0x1) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3601 dst = set_flag(dst, 1, FLAG_C, opts); |
| 106 | 3602 } |
| 3603 if (inst->src.params.immed & 0x2) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3604 dst = set_flag(dst, 1, FLAG_V, opts); |
| 106 | 3605 } |
| 3606 if (inst->src.params.immed & 0x4) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3607 dst = set_flag(dst, 1, FLAG_Z, opts); |
| 106 | 3608 } |
| 3609 if (inst->src.params.immed & 0x8) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3610 dst = set_flag(dst, 1, FLAG_N, opts); |
| 106 | 3611 } |
| 3612 if (inst->src.params.immed & 0x10) { | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3613 dst = set_flag(dst, 1, FLAG_X, opts); |
| 106 | 3614 } |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3615 if (inst->op == M68K_ORI_SR) { |
| 106 | 3616 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3617 if (inst->src.params.immed & 0x700) { |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3618 dst = call(dst, opts->do_sync); |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
3619 } |
| 106 | 3620 } |
| 3621 break; | |
|
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3622 case M68K_RESET: |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3623 dst = call(dst, opts->gen.save_context); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3624 #ifdef X86_64 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3625 dst = mov_rr(dst, CONTEXT, RDI, SZ_PTR); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3626 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3627 dst = push_r(dst, CONTEXT); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
3628 #endif |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3629 dst = call(dst, (code_ptr)print_regs_exit); |
|
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
211
diff
changeset
|
3630 break; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3631 case M68K_ROL: |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3632 case M68K_ROR: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3633 dst = set_flag(dst, 0, FLAG_V, opts); |
| 122 | 3634 if (inst->src.addr_mode == MODE_UNUSED) { |
| 3635 dst = cycles(dst, BUS); | |
| 3636 //Memory rotate | |
| 3637 if (inst->op == M68K_ROL) { | |
| 3638 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
| 3639 } else { | |
| 3640 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
| 3641 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3642 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
| 122 | 3643 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3644 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3645 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
| 122 | 3646 dst = m68k_save_result(inst, dst, opts); |
| 3647 } else { | |
| 3648 if (src_op.mode == MODE_IMMED) { | |
| 3649 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); | |
| 3650 if (dst_op.mode == MODE_REG_DIRECT) { | |
| 3651 if (inst->op == M68K_ROL) { | |
| 3652 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
| 3653 } else { | |
| 3654 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size); | |
| 3655 } | |
| 3656 } else { | |
| 3657 if (inst->op == M68K_ROL) { | |
| 3658 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3659 } else { | |
| 3660 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3661 } | |
| 3662 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3663 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
| 122 | 3664 } else { |
| 3665 if (src_op.mode == MODE_REG_DIRECT) { | |
| 3666 if (src_op.base != SCRATCH1) { | |
| 3667 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); | |
| 3668 } | |
| 3669 } else { | |
| 3670 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); | |
| 3671 } | |
| 3672 dst = and_ir(dst, 63, SCRATCH1, SZ_D); | |
| 3673 zero_off = dst+1; | |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3674 dst = jcc(dst, CC_Z, dst+2); |
| 122 | 3675 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
| 3676 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); | |
| 3677 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); | |
| 3678 norm_off = dst+1; | |
| 3679 dst = jcc(dst, CC_L, dst+2); | |
|
442
1a48b31f5316
Fix carry flag on rotate when the register provided rotate bit count is exactly 32
Mike Pavone <pavone@retrodev.com>
parents:
440
diff
changeset
|
3680 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
| 122 | 3681 if (dst_op.mode == MODE_REG_DIRECT) { |
| 3682 if (inst->op == M68K_ROL) { | |
| 3683 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size); | |
| 3684 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size); | |
| 3685 } else { | |
| 3686 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size); | |
| 3687 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size); | |
| 3688 } | |
| 3689 } else { | |
| 3690 if (inst->op == M68K_ROL) { | |
| 3691 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3692 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3693 } else { | |
| 3694 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3695 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3696 } | |
| 3697 } | |
| 3698 *norm_off = dst - (norm_off+1); | |
| 3699 if (dst_op.mode == MODE_REG_DIRECT) { | |
| 3700 if (inst->op == M68K_ROL) { | |
| 3701 dst = rol_clr(dst, dst_op.base, inst->extra.size); | |
| 3702 } else { | |
| 3703 dst = ror_clr(dst, dst_op.base, inst->extra.size); | |
| 3704 } | |
| 3705 } else { | |
| 3706 if (inst->op == M68K_ROL) { | |
| 3707 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3708 } else { | |
| 3709 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3710 } | |
| 3711 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3712 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
| 122 | 3713 end_off = dst + 1; |
| 3714 dst = jmp(dst, dst+2); | |
| 3715 *zero_off = dst - (zero_off+1); | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3716 dst = set_flag(dst, 0, FLAG_C, opts); |
| 122 | 3717 *end_off = dst - (end_off+1); |
| 3718 } | |
| 3719 if (dst_op.mode == MODE_REG_DIRECT) { | |
| 3720 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); | |
| 3721 } else { | |
| 3722 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); | |
| 3723 } | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3724 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3725 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
| 122 | 3726 } |
| 3727 break; | |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3728 case M68K_ROXL: |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3729 case M68K_ROXR: |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3730 dst = set_flag(dst, 0, FLAG_V, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3731 if (inst->src.addr_mode == MODE_UNUSED) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3732 dst = cycles(dst, BUS); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3733 //Memory rotate |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3734 dst = flag_to_carry(dst, FLAG_X, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3735 if (inst->op == M68K_ROXL) { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3736 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3737 } else { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3738 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3739 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3740 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3741 if (opts->flag_regs[FLAG_C] < 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3742 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3743 } |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3744 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3745 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3746 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3747 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3748 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3749 } |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3750 dst = m68k_save_result(inst, dst, opts); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3751 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3752 if (src_op.mode == MODE_IMMED) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3753 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3754 dst = flag_to_carry(dst, FLAG_X, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3755 if (dst_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3756 if (inst->op == M68K_ROXL) { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3757 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3758 } else { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3759 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3760 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3761 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3762 if (inst->op == M68K_ROXL) { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3763 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3764 } else { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3765 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3766 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3767 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3768 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3769 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3770 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3771 } else { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3772 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3773 } |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3774 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3775 if (src_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3776 if (src_op.base != SCRATCH1) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3777 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3778 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3779 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3780 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3781 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3782 dst = and_ir(dst, 63, SCRATCH1, SZ_D); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3783 zero_off = dst+1; |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3784 dst = jcc(dst, CC_Z, dst+2); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3785 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3786 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3787 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3788 norm_off = dst+1; |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3789 dst = jcc(dst, CC_L, dst+2); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3790 dst = flag_to_carry(dst, FLAG_X, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3791 if (dst_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3792 if (inst->op == M68K_ROXL) { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3793 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size); |
|
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3794 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3795 } else { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3796 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size); |
|
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3797 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3798 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3799 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3800 if (inst->op == M68K_ROXL) { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3801 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
|
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3802 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3803 } else { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3804 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size); |
|
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3805 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3806 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3807 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3808 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3809 dst = sub_ir(dst, 32, SCRATCH1, SZ_B); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3810 *norm_off = dst - (norm_off+1); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3811 dst = flag_to_carry(dst, FLAG_X, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3812 if (dst_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3813 if (inst->op == M68K_ROXL) { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3814 dst = rcl_clr(dst, dst_op.base, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3815 } else { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3816 dst = rcr_clr(dst, dst_op.base, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3817 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3818 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3819 if (inst->op == M68K_ROXL) { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3820 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3821 } else { |
|
157
301470eb870b
Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Mike Pavone <pavone@retrodev.com>
parents:
156
diff
changeset
|
3822 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3823 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3824 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3825 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3826 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3827 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3828 } else { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3829 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3830 } |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3831 end_off = dst + 1; |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3832 dst = jmp(dst, dst+2); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3833 *zero_off = dst - (zero_off+1); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3834 //Carry flag is set to X flag when count is 0, this is different from ROR/ROL |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3835 dst = flag_to_flag(dst, FLAG_X, FLAG_C, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3836 *end_off = dst - (end_off+1); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3837 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3838 if (dst_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3839 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3840 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3841 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3842 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3843 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3844 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3845 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3846 break; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3847 case M68K_RTE: |
| 170 | 3848 //TODO: Trap if not in system mode |
|
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3849 //Read saved SR |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3850 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3851 dst = call(dst, opts->read_16); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3852 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
|
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
3853 dst = call(dst, opts->set_sr); |
|
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3854 //Read saved PC |
|
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3855 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3856 dst = call(dst, opts->read_32); |
|
178
48eb62ba63bc
Fix order of reading saved pc and swapping user and system stack pointers
Mike Pavone <pavone@retrodev.com>
parents:
177
diff
changeset
|
3857 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
|
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3858 //Check if we've switched to user mode and swap stack pointers if needed |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3859 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3860 end_off = dst+1; |
|
121
f848aad2abef
Fix logic for switching between USP and SSP
Mike Pavone <pavone@retrodev.com>
parents:
119
diff
changeset
|
3861 dst = jcc(dst, CC_C, dst+2); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3862 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3863 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3864 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3865 *end_off = dst - (end_off+1); |
|
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3866 //Get native address, sync components, recalculate integer points and jump to returned address |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
3867 dst = call(dst, opts->native_addr_and_sync); |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3868 dst = jmp_r(dst, SCRATCH1); |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
3869 break; |
| 170 | 3870 case M68K_RTR: |
|
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3871 //Read saved CCR |
| 170 | 3872 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3873 dst = call(dst, opts->read_16); |
| 170 | 3874 dst = add_ir(dst, 2, opts->aregs[7], SZ_D); |
|
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
3875 dst = call(dst, opts->set_ccr); |
|
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3876 //Read saved PC |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3877 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
3878 dst = call(dst, opts->read_32); |
|
175
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3879 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
|
7504200cac86
Fix order of SR and PC saved in an exception stack frame
Mike Pavone <pavone@retrodev.com>
parents:
174
diff
changeset
|
3880 //Get native address and jump to it |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
3881 dst = call(dst, opts->native_addr); |
| 170 | 3882 dst = jmp_r(dst, SCRATCH1); |
| 3883 break; | |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3884 case M68K_SBCD: { |
|
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3885 if (src_op.base != SCRATCH2) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3886 if (src_op.mode == MODE_REG_DIRECT) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3887 dst = mov_rr(dst, src_op.base, SCRATCH2, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3888 } else { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3889 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3890 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3891 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3892 if (dst_op.base != SCRATCH1) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3893 if (dst_op.mode == MODE_REG_DIRECT) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3894 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3895 } else { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3896 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3897 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3898 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3899 dst = flag_to_carry(dst, FLAG_X, opts); |
|
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3900 dst = jcc(dst, CC_NC, dst+5); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3901 dst = sub_ir(dst, 1, SCRATCH1, SZ_B); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3902 dst = call(dst, (code_ptr)bcd_sub); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3903 dst = reg_to_flag(dst, CH, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3904 dst = reg_to_flag(dst, CH, FLAG_X, opts); |
|
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3905 dst = cmp_ir(dst, 0, SCRATCH1, SZ_B); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3906 code_ptr after_flag_set = dst+1; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3907 dst = jcc(dst, CC_Z, dst+2); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3908 dst = set_flag(dst, 0, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3909 *after_flag_set = dst - (after_flag_set+1); |
|
194
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3910 if (dst_op.base != SCRATCH1) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3911 if (dst_op.mode == MODE_REG_DIRECT) { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3912 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3913 } else { |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3914 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_B); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3915 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3916 } |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3917 dst = m68k_save_result(inst, dst, opts); |
|
811163790e6c
Implement ABCD an SBCD. Fix BTEST with register source.
Mike Pavone <pavone@retrodev.com>
parents:
193
diff
changeset
|
3918 break; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3919 } |
|
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3920 case M68K_STOP: { |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3921 //TODO: Trap if not in system mode |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3922 //manual says 4 cycles, but it has to be at least 8 since it's a 2-word instruction |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3923 //possibly even 12 since that's how long MOVE to SR takes |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3924 dst = cycles(dst, BUS*2); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3925 dst = set_flag(dst, src_op.disp & 0x1, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3926 dst = set_flag(dst, (src_op.disp >> 1) & 0x1, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3927 dst = set_flag(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3928 dst = set_flag(dst, (src_op.disp >> 3) & 0x1, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3929 dst = set_flag(dst, (src_op.disp >> 4) & 0x1, FLAG_X, opts); |
|
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3930 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3931 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3932 //leave supervisor mode |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3933 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3934 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D); |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3935 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3936 } |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3937 code_ptr loop_top = dst; |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
3938 dst = call(dst, opts->do_sync); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3939 dst = cmp_rr(dst, LIMIT, CYCLES, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3940 code_ptr normal_cycle_up = dst + 1; |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3941 dst = jcc(dst, CC_A, dst+2); |
|
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3942 dst = cycles(dst, BUS); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
3943 code_ptr after_cycle_up = dst + 1; |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3944 dst = jmp(dst, dst+2); |
|
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3945 *normal_cycle_up = dst - (normal_cycle_up + 1); |
|
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3946 dst = mov_rr(dst, LIMIT, CYCLES, SZ_D); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
3947 *after_cycle_up = dst - (after_cycle_up+1); |
|
446
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3948 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D); |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3949 dst = jcc(dst, CC_C, loop_top); |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3950 break; |
|
1e828ed04a7c
Implement 68K stop instruction
Mike Pavone <pavone@retrodev.com>
parents:
443
diff
changeset
|
3951 } |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3952 case M68K_SUB: |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3953 size = inst->dst.addr_mode == MODE_AREG ? OPSIZE_LONG : inst->extra.size; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3954 dst = cycles(dst, BUS); |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3955 if (src_op.mode == MODE_REG_DIRECT) { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3956 if (dst_op.mode == MODE_REG_DIRECT) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3957 dst = sub_rr(dst, src_op.base, dst_op.base, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3958 } else { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3959 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3960 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3961 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3962 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3963 } else { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3964 if (dst_op.mode == MODE_REG_DIRECT) { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3965 dst = sub_ir(dst, src_op.disp, dst_op.base, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3966 } else { |
|
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
179
diff
changeset
|
3967 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, size); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3968 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3969 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3970 if (inst->dst.addr_mode != MODE_AREG) { |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3971 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3972 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3973 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3974 dst = set_flag_cond(dst, CC_O, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3975 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3976 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3977 } else { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3978 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3979 } |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
3980 } |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
3981 dst = m68k_save_result(inst, dst, opts); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
3982 break; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3983 case M68K_SUBX: { |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3984 dst = cycles(dst, BUS); |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
3985 dst = flag_to_carry(dst, FLAG_X, opts); |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3986 if (src_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3987 if (dst_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3988 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3989 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3990 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3991 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3992 } else if (src_op.mode == MODE_REG_DISPLACE8) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3993 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3994 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3995 if (dst_op.mode == MODE_REG_DIRECT) { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3996 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3997 } else { |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3998 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
3999 } |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
4000 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4001 dst = set_flag_cond(dst, CC_C, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4002 if (opts->flag_regs[FLAG_C] < 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4003 dst = set_flag_cond(dst, CC_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4004 } |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4005 code_ptr after_flag_set = dst+1; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4006 dst = jcc(dst, CC_Z, dst+2); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4007 dst = set_flag(dst, 0, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4008 *after_flag_set = dst - (after_flag_set+1); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4009 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4010 dst = set_flag_cond(dst, CC_O, FLAG_V, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4011 if (opts->flag_regs[FLAG_C] >= 0) { |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4012 dst = flag_to_flag(dst, FLAG_C, FLAG_X, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4013 } |
|
146
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
4014 dst = m68k_save_result(inst, dst, opts); |
|
5416a5c4628e
Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents:
133
diff
changeset
|
4015 break; |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4016 } |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4017 case M68K_SWAP: |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4018 dst = cycles(dst, BUS); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4019 if (src_op.mode == MODE_REG_DIRECT) { |
| 129 | 4020 dst = rol_ir(dst, 16, src_op.base, SZ_D); |
| 443 | 4021 dst = cmp_ir(dst, 0, src_op.base, SZ_D); |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4022 } else{ |
| 129 | 4023 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D); |
| 443 | 4024 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, SZ_D); |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4025 } |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4026 |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4027 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4028 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4029 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4030 dst = set_flag(dst, 0, FLAG_V, opts); |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4031 break; |
|
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
4032 //case M68K_TAS: |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4033 case M68K_TRAP: |
|
226
28a6697e847b
Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents:
225
diff
changeset
|
4034 dst = mov_ir(dst, src_op.disp + VECTOR_TRAP_0, SCRATCH2, SZ_D); |
|
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
182
diff
changeset
|
4035 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); |
|
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4036 dst = jmp(dst, opts->trap); |
|
152
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
4037 break; |
|
79958b95526f
Implement TRAP (untested)
Mike Pavone <pavone@retrodev.com>
parents:
151
diff
changeset
|
4038 //case M68K_TRAPV: |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4039 case M68K_TST: |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4040 dst = cycles(dst, BUS); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4041 if (src_op.mode == MODE_REG_DIRECT) { |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4042 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4043 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8 |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4044 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size); |
|
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4045 } |
|
546
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4046 dst = set_flag(dst, 0, FLAG_C, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4047 dst = set_flag_cond(dst, CC_Z, FLAG_Z, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4048 dst = set_flag_cond(dst, CC_S, FLAG_N, opts); |
|
90aca661542b
Make references to flags in the M68K core respect the flag_regs options array so that flags can be moved out of registers for the 32-bit port. set/get ccr/sr still need to be updated to support this, but everything else should be done.
Michael Pavone <pavone@retrodev.com>
parents:
545
diff
changeset
|
4049 dst = set_flag(dst, 0, FLAG_V, opts); |
|
49
d2e43d64e999
Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
4050 break; |
|
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4051 case M68K_UNLK: |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4052 dst = cycles(dst, BUS); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4053 if (dst_op.mode == MODE_REG_DIRECT) { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4054 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4055 } else { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4056 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4057 } |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4058 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4059 dst = call(dst, opts->read_32); |
|
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4060 if (dst_op.mode == MODE_REG_DIRECT) { |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4061 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D); |
|
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4062 } else { |
|
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
4063 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); |
|
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4064 } |
|
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
92
diff
changeset
|
4065 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); |
|
78
463641032588
Added untested support for LINK and UNLK
Mike Pavone <pavone@retrodev.com>
parents:
77
diff
changeset
|
4066 break; |
|
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
4067 default: |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
4068 m68k_disasm(inst, disasm_buf); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
150
diff
changeset
|
4069 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op); |
|
70
cebd0b5ac7f0
Make the translator bail out if it hits an instruction I haven't implemented yet
Mike Pavone <pavone@retrodev.com>
parents:
67
diff
changeset
|
4070 exit(1); |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4071 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4072 return dst; |
|
14
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4073 } |
|
2bdad0f52f42
x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
4074 |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4075 uint8_t m68k_is_terminal(m68kinst * inst) |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4076 { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4077 return inst->op == M68K_RTS || inst->op == M68K_RTE || inst->op == M68K_RTR || inst->op == M68K_JMP |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4078 || inst->op == M68K_TRAP || inst->op == M68K_ILLEGAL || inst->op == M68K_INVALID || inst->op == M68K_RESET |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4079 || (inst->op == M68K_BCC && inst->extra.cond == COND_TRUE); |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4080 } |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4081 |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4082 void m68k_handle_deferred(m68k_context * context) |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4083 { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4084 x86_68k_options * opts = context->options; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4085 process_deferred(&opts->gen.deferred, context, (native_addr_func)get_native_from_context); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4086 if (opts->gen.deferred) { |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4087 translate_m68k_stream(opts->gen.deferred->address, context); |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4088 } |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4089 } |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4090 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4091 code_ptr translate_m68k_stream(uint32_t address, m68k_context * context) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4092 { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4093 m68kinst instbuf; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4094 x86_68k_options * opts = context->options; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4095 code_ptr dst = opts->gen.cur_code; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4096 code_ptr dst_end = opts->gen.code_end; |
|
188
062e3aa549eb
Fix movem.w when dest is register list
Mike Pavone <pavone@retrodev.com>
parents:
187
diff
changeset
|
4097 address &= 0xFFFFFF; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4098 if(get_native_address(opts->gen.native_code_map, address)) { |
|
82
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
4099 return dst; |
|
6331ddec228f
Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents:
81
diff
changeset
|
4100 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4101 char disbuf[1024]; |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4102 uint16_t *encoded, *next; |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4103 if ((address & 0xFFFFFF) < 0x400000) { |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4104 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4105 } else if ((address & 0xFFFFFF) > 0xE00000) { |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4106 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4107 } else { |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4108 printf("attempt to translate non-memory address: %X\n", address); |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4109 exit(1); |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4110 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4111 do { |
|
197
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
4112 if (opts->address_log) { |
|
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
4113 fprintf(opts->address_log, "%X\n", address); |
|
7c227a8ec53d
Add instruction address logging to translator and support for reading an address log to the disassembler
Mike Pavone <pavone@retrodev.com>
parents:
196
diff
changeset
|
4114 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4115 do { |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4116 if (dst_end-dst < MAX_NATIVE_SIZE) { |
|
102
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
4117 if (dst_end-dst < 5) { |
|
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
4118 puts("out of code memory, not enough space for jmp to next chunk"); |
|
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
4119 exit(1); |
|
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
4120 } |
|
bfaca67eeb78
allocate a new native code chunk when we run out of space
Mike Pavone <pavone@retrodev.com>
parents:
100
diff
changeset
|
4121 size_t size = 1024*1024; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4122 opts->gen.cur_code = alloc_code(&size); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4123 opts->gen.code_end = opts->gen.cur_code + size; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4124 jmp(dst, opts->gen.cur_code); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4125 dst = opts->gen.cur_code; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4126 dst_end = opts->gen.code_end; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4127 } |
|
159
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
4128 if (address >= 0x400000 && address < 0xE00000) { |
|
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
4129 dst = xor_rr(dst, RDI, RDI, SZ_D); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4130 #ifdef X86_32 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4131 dst = push_r(dst, RDI); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4132 #endif |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4133 dst = call(dst, (code_ptr)exit); |
|
159
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
4134 break; |
|
c1530501c215
FIx movem when src is reg list and dst is not a areg predec mode
Mike Pavone <pavone@retrodev.com>
parents:
158
diff
changeset
|
4135 } |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4136 code_ptr existing = get_native_address(opts->gen.native_code_map, address); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4137 if (existing) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4138 dst = jmp(dst, existing); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4139 break; |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4140 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4141 next = m68k_decode(encoded, &instbuf, address); |
|
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
4142 if (instbuf.op == M68K_INVALID) { |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
4143 instbuf.src.params.immed = *encoded; |
|
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
207
diff
changeset
|
4144 } |
|
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4145 uint16_t m68k_size = (next-encoded)*2; |
|
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4146 address += m68k_size; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4147 encoded = next; |
|
150
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
4148 //m68k_disasm(&instbuf, disbuf); |
|
3e68e517cc01
Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mike Pavone <pavone@retrodev.com>
parents:
146
diff
changeset
|
4149 //printf("%X: %s\n", instbuf.address, disbuf); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4150 code_ptr after = translate_m68k(dst, &instbuf, opts); |
|
192
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4151 map_native_address(context, instbuf.address, dst, m68k_size, after-dst); |
|
1db07e112bf7
Prep work for handling games that modify code in RAM
Mike Pavone <pavone@retrodev.com>
parents:
188
diff
changeset
|
4152 dst = after; |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4153 } while(!m68k_is_terminal(&instbuf)); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4154 process_deferred(&opts->gen.deferred, context, (native_addr_func)get_native_from_context); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4155 if (opts->gen.deferred) { |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4156 address = opts->gen.deferred->address; |
|
124
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4157 if ((address & 0xFFFFFF) < 0x400000) { |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4158 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2; |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4159 } else if ((address & 0xFFFFFF) > 0xE00000) { |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4160 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2; |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4161 } else { |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4162 printf("attempt to translate non-memory address: %X\n", address); |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4163 exit(1); |
|
da95566514f3
Some fixes for translating code in located in RAM
Mike Pavone <pavone@retrodev.com>
parents:
123
diff
changeset
|
4164 } |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4165 } else { |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4166 encoded = NULL; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4167 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4168 } while(encoded != NULL); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4169 opts->gen.cur_code = dst; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4170 return dst; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4171 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4172 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4173 code_ptr get_native_address_trans(m68k_context * context, uint32_t address) |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4174 { |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4175 address &= 0xFFFFFF; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4176 code_ptr ret = get_native_address(context->native_code_map, address); |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4177 if (!ret) { |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4178 translate_m68k_stream(address, context); |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4179 ret = get_native_address(context->native_code_map, address); |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4180 } |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4181 return ret; |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4182 } |
|
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4183 |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4184 void * m68k_retranslate_inst(uint32_t address, m68k_context * context) |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4185 { |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4186 x86_68k_options * opts = context->options; |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4187 uint8_t orig_size = get_native_inst_size(opts, address); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4188 code_ptr orig_start = get_native_address(context->native_code_map, address); |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4189 uint32_t orig = address; |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4190 address &= 0xFFFF; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4191 code_ptr dst = opts->gen.cur_code; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4192 code_ptr dst_end = opts->gen.code_end; |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4193 uint16_t *after, *inst = context->mem_pointers[1] + address/2; |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4194 m68kinst instbuf; |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4195 after = m68k_decode(inst, &instbuf, orig); |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4196 if (orig_size != MAX_NATIVE_SIZE) { |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4197 if (dst_end - dst < 128) { |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4198 size_t size = 1024*1024; |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4199 dst = alloc_code(&size); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4200 opts->gen.code_end = dst_end = dst + size; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4201 opts->gen.cur_code = dst; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4202 } |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4203 deferred_addr * orig_deferred = opts->gen.deferred; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4204 code_ptr native_end = translate_m68k(dst, &instbuf, opts); |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4205 uint8_t is_terminal = m68k_is_terminal(&instbuf); |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4206 if ((native_end - dst) <= orig_size) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4207 code_ptr native_next; |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4208 if (!is_terminal) { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4209 native_next = get_native_address(context->native_code_map, orig + (after-inst)*2); |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4210 } |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4211 if (is_terminal || (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5))) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4212 remove_deferred_until(&opts->gen.deferred, orig_deferred); |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4213 native_end = translate_m68k(orig_start, &instbuf, opts); |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4214 if (!is_terminal) { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4215 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4216 while (native_end < orig_start + orig_size) { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4217 *(native_end++) = 0x90; //NOP |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4218 } |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4219 } else { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4220 jmp(native_end, native_next); |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4221 } |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4222 } |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4223 m68k_handle_deferred(context); |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4224 return orig_start; |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4225 } |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4226 } |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4227 |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4228 map_native_address(context, instbuf.address, dst, (after-inst)*2, MAX_NATIVE_SIZE); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4229 opts->gen.cur_code = dst+MAX_NATIVE_SIZE; |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4230 jmp(orig_start, dst); |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4231 if (!m68k_is_terminal(&instbuf)) { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4232 jmp(native_end, get_native_address_trans(context, orig + (after-inst)*2)); |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4233 } |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4234 m68k_handle_deferred(context); |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4235 return dst; |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4236 } else { |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4237 dst = translate_m68k(orig_start, &instbuf, opts); |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4238 if (!m68k_is_terminal(&instbuf)) { |
|
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4239 dst = jmp(dst, get_native_address_trans(context, orig + (after-inst)*2)); |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4240 } |
|
319
0bcab0475a7f
Port instruction retranslation improvements from Z80 core to M68K core
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
4241 m68k_handle_deferred(context); |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4242 return orig_start; |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4243 } |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4244 } |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4245 |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4246 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context) |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4247 { |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4248 uint32_t inst_start = get_instruction_start(context->native_code_map, address | 0xFF0000); |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4249 if (inst_start) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4250 code_ptr dst = get_native_address(context->native_code_map, inst_start); |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4251 dst = mov_ir(dst, inst_start, SCRATCH2, SZ_D); |
|
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4252 x86_68k_options * options = context->options; |
|
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4253 if (!options->retrans_stub) { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4254 if (options->gen.code_end - options->gen.cur_code < 32) { |
|
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4255 size_t size = 1024*1024; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4256 options->gen.cur_code = alloc_code(&size); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4257 options->gen.code_end = options->gen.cur_code + size; |
|
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4258 } |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4259 code_ptr rdst = options->retrans_stub = options->gen.cur_code; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4260 rdst = call(rdst, options->gen.save_context); |
|
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4261 rdst = push_r(rdst, CONTEXT); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4262 #ifdef X86_32 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4263 rdst = push_r(rdst, CONTEXT); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4264 rdst = push_r(rdst, SCRATCH2); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4265 #endif |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4266 rdst = call(rdst, (code_ptr)m68k_retranslate_inst); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4267 #ifdef X86_32 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4268 rdst = add_ir(rdst, 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4269 #endif |
|
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4270 rdst = pop_r(rdst, CONTEXT); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4271 rdst = mov_rr(rdst, RAX, SCRATCH1, SZ_PTR); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4272 rdst = call(rdst, options->gen.load_context); |
|
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4273 rdst = jmp_r(rdst, SCRATCH1); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4274 options->gen.cur_code = rdst; |
|
543
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4275 } |
|
915a1cb98bac
Generate retrans_stub at runtime so it can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
542
diff
changeset
|
4276 dst = jmp(dst, options->retrans_stub); |
|
193
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4277 } |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4278 return context; |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4279 } |
|
c66e4636f991
Implement support for self-modifying code
Mike Pavone <pavone@retrodev.com>
parents:
192
diff
changeset
|
4280 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4281 void insert_breakpoint(m68k_context * context, uint32_t address, code_ptr bp_handler) |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4282 { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4283 static code_ptr bp_stub = NULL; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4284 code_ptr native = get_native_address_trans(context, address); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4285 code_ptr start_native = native; |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4286 native = mov_ir(native, address, SCRATCH1, SZ_D); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4287 if (!bp_stub) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4288 x86_68k_options * opts = context->options; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4289 code_ptr dst = opts->gen.cur_code; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4290 code_ptr dst_end = opts->gen.code_end; |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4291 if (dst_end - dst < 128) { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4292 size_t size = 1024*1024; |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4293 dst = alloc_code(&size); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4294 opts->gen.code_end = dst_end = dst + size; |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4295 } |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4296 bp_stub = dst; |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4297 native = call(native, bp_stub); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4298 |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4299 //Calculate length of prologue |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4300 dst = check_cycles_int(dst, address, opts); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4301 int check_int_size = dst-bp_stub; |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4302 dst = bp_stub; |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4303 |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4304 //Save context and call breakpoint handler |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4305 dst = call(dst, opts->gen.save_context); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4306 dst = push_r(dst, SCRATCH1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4307 #ifdef X86_64 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4308 dst = mov_rr(dst, CONTEXT, RDI, SZ_PTR); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4309 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4310 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4311 dst = push_r(dst, SCRATCH1); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4312 dst = push_r(dst, CONTEXT); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4313 #endif |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4314 dst = call(dst, bp_handler); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4315 #ifdef X86_32 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4316 dst = add_ir(dst, 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4317 #endif |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4318 dst = mov_rr(dst, RAX, CONTEXT, SZ_PTR); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4319 //Restore context |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4320 dst = call(dst, opts->gen.load_context); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4321 dst = pop_r(dst, SCRATCH1); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4322 //do prologue stuff |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4323 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4324 code_ptr jmp_off = dst+1; |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4325 dst = jcc(dst, CC_NC, dst + 7); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4326 dst = call(dst, opts->gen.handle_cycle_limit_int); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4327 *jmp_off = dst - (jmp_off+1); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4328 //jump back to body of translated instruction |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4329 dst = pop_r(dst, SCRATCH1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4330 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_PTR); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4331 dst = jmp_r(dst, SCRATCH1); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4332 opts->gen.cur_code = dst; |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4333 } else { |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4334 native = call(native, bp_stub); |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4335 } |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4336 } |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4337 |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4338 void remove_breakpoint(m68k_context * context, uint32_t address) |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4339 { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4340 code_ptr native = get_native_address(context->native_code_map, address); |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4341 check_cycles_int(native, address, context->options); |
|
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4342 } |
|
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
4343 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4344 void start_68k_context(m68k_context * context, uint32_t address) |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4345 { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4346 code_ptr addr = get_native_address_trans(context, address); |
|
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4347 x86_68k_options * options = context->options; |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4348 options->start_context(addr, context); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4349 } |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4350 |
|
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4351 void m68k_reset(m68k_context * context) |
|
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4352 { |
|
71
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4353 //TODO: Make this actually use the normal read functions |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4354 context->aregs[7] = context->mem_pointers[0][0] << 16 | context->mem_pointers[0][1]; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4355 uint32_t address = context->mem_pointers[0][2] << 16 | context->mem_pointers[0][3]; |
|
f80fa1776507
Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents:
70
diff
changeset
|
4356 start_68k_context(context, address); |
|
19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4357 } |
|
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
4358 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4359 code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk * memmap, uint32_t num_chunks, ftype fun_type) |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4360 { |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4361 code_ptr dst = opts->cur_code; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4362 code_ptr start = dst; |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4363 dst = check_cycles(dst, opts); |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4364 dst = cycles(dst, BUS); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4365 dst = and_ir(dst, 0xFFFFFF, SCRATCH1, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4366 code_ptr lb_jcc = NULL, ub_jcc = NULL; |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4367 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4368 uint8_t adr_reg = is_write ? SCRATCH2 : SCRATCH1; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4369 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4370 uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4371 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4372 { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4373 if (memmap[chunk].start > 0) { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4374 dst = cmp_ir(dst, memmap[chunk].start, adr_reg, SZ_D); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4375 lb_jcc = dst + 1; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4376 dst = jcc(dst, CC_C, dst+2); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4377 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4378 if (memmap[chunk].end < 0x1000000) { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4379 dst = cmp_ir(dst, memmap[chunk].end, adr_reg, SZ_D); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4380 ub_jcc = dst + 1; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4381 dst = jcc(dst, CC_NC, dst+2); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4382 } |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4383 |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4384 if (memmap[chunk].mask != 0xFFFFFF) { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4385 dst = and_ir(dst, memmap[chunk].mask, adr_reg, SZ_D); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4386 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4387 void * cfun; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4388 switch (fun_type) |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4389 { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4390 case READ_16: |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4391 cfun = memmap[chunk].read_16; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4392 break; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4393 case READ_8: |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4394 cfun = memmap[chunk].read_8; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4395 break; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4396 case WRITE_16: |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4397 cfun = memmap[chunk].write_16; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4398 break; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4399 case WRITE_8: |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4400 cfun = memmap[chunk].write_8; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4401 break; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4402 default: |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4403 cfun = NULL; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4404 } |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4405 if(memmap[chunk].buffer && memmap[chunk].flags & access_flag) { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4406 if (memmap[chunk].flags & MMAP_PTR_IDX) { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4407 if (memmap[chunk].flags & MMAP_FUNC_NULL) { |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4408 dst = cmp_irdisp8(dst, 0, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void*) * memmap[chunk].ptr_index, SZ_PTR); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4409 code_ptr not_null = dst+1; |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4410 dst = jcc(dst, CC_NZ, dst+2); |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4411 dst = call(dst, opts->save_context); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4412 #ifdef X86_64 |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4413 if (is_write) { |
|
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4414 if (SCRATCH2 != RDI) { |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4415 dst = mov_rr(dst, SCRATCH2, RDI, SZ_D); |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4416 } |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4417 dst = mov_rr(dst, SCRATCH1, RDX, size); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4418 } else { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4419 dst = push_r(dst, CONTEXT); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4420 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4421 } |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4422 dst = test_ir(dst, 8, RSP, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4423 code_ptr adjust_rsp = dst+1; |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4424 dst = jcc(dst, CC_NZ, dst+2); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4425 dst = call(dst, cfun); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4426 code_ptr no_adjust = dst+1; |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4427 dst = jmp(dst, dst+2); |
|
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4428 *adjust_rsp = dst - (adjust_rsp + 1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4429 dst = sub_ir(dst, 8, RSP, SZ_PTR); |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4430 dst = call(dst, cfun); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4431 dst = add_ir(dst, 8, RSP, SZ_PTR); |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4432 *no_adjust = dst - (no_adjust + 1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4433 #else |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4434 if (is_write) { |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4435 dst = push_r(dst, SCRATCH1); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4436 } else { |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4437 dst = push_r(dst, CONTEXT);//save CONTEXT for later |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4438 } |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4439 dst = push_r(dst, CONTEXT); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4440 dst = push_r(dst, is_write ? SCRATCH2 : SCRATCH1); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4441 dst = call(dst, cfun); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4442 dst = add_ir(dst, is_write ? 12 : 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4443 #endif |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4444 if (is_write) { |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4445 dst = mov_rr(dst, RAX, CONTEXT, SZ_PTR); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4446 } else { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4447 dst = pop_r(dst, CONTEXT); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4448 dst = mov_rr(dst, RAX, SCRATCH1, size); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4449 } |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4450 dst = jmp(dst, opts->load_context); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4451 |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4452 *not_null = dst - (not_null + 1); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4453 } |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4454 if (size == SZ_B) { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4455 dst = xor_ir(dst, 1, adr_reg, SZ_D); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4456 } |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4457 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, mem_pointers) + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_PTR); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4458 if (is_write) { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4459 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, size); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4460 |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4461 } else { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4462 dst = mov_rindr(dst, SCRATCH1, SCRATCH1, size); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4463 } |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4464 } else { |
|
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4465 uint8_t tmp_size = size; |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4466 if (size == SZ_B) { |
|
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4467 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4468 dst = bt_ir(dst, 0, adr_reg, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4469 code_ptr good_addr = dst + 1; |
|
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4470 dst = jcc(dst, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, dst+2); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4471 if (!is_write) { |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4472 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4473 } |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4474 dst = retn(dst); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4475 *good_addr = dst - (good_addr + 1); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4476 dst = shr_ir(dst, 1, adr_reg, SZ_D); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4477 } else { |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4478 dst = xor_ir(dst, 1, adr_reg, SZ_D); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4479 } |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4480 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4481 tmp_size = SZ_B; |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4482 dst = shr_ir(dst, 1, adr_reg, SZ_D); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4483 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4484 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4485 } |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4486 } |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4487 if ((intptr_t)memmap[chunk].buffer <= 0x7FFFFFFF && (intptr_t)memmap[chunk].buffer >= -2147483648) { |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4488 if (is_write) { |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4489 dst = mov_rrdisp32(dst, SCRATCH1, SCRATCH2, (intptr_t)memmap[chunk].buffer, tmp_size); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4490 } else { |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4491 dst = mov_rdisp32r(dst, SCRATCH1, (intptr_t)memmap[chunk].buffer, SCRATCH1, tmp_size); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4492 } |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4493 } else { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4494 if (is_write) { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4495 dst = push_r(dst, SCRATCH1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4496 dst = mov_ir(dst, (intptr_t)memmap[chunk].buffer, SCRATCH1, SZ_PTR); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4497 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_PTR); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4498 dst = pop_r(dst, SCRATCH1); |
|
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4499 dst = mov_rrind(dst, SCRATCH1, SCRATCH2, tmp_size); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4500 } else { |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4501 dst = mov_ir(dst, (intptr_t)memmap[chunk].buffer, SCRATCH2, SZ_PTR); |
|
352
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4502 dst = mov_rindexr(dst, SCRATCH2, SCRATCH1, 1, SCRATCH1, tmp_size); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4503 } |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4504 } |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4505 if (size != tmp_size && !is_write) { |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4506 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4507 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4508 dst = mov_ir(dst, 0xFF, SCRATCH1, SZ_B); |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4509 } else { |
|
8c3409585130
Finish SRAM support for games without a SEGA mapper
Mike Pavone <pavone@retrodev.com>
parents:
351
diff
changeset
|
4510 dst = or_ir(dst, 0xFF00, SCRATCH1, SZ_W); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4511 } |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4512 } |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4513 } |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4514 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4515 dst = mov_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4516 dst = shr_ir(dst, 11, SCRATCH1, SZ_D); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4517 dst = bt_rrdisp32(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, ram_code_flags), SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4518 code_ptr not_code = dst+1; |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4519 dst = jcc(dst, CC_NC, dst+2); |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4520 dst = call(dst, opts->save_context); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4521 #ifdef X86_32 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4522 dst = push_r(dst, CONTEXT); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4523 dst = push_r(dst, SCRATCH2); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4524 #endif |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4525 dst = call(dst, (code_ptr)m68k_handle_code_write); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4526 #ifdef X86_32 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4527 dst = add_ir(dst, 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4528 #endif |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4529 dst = mov_rr(dst, RAX, CONTEXT, SZ_PTR); |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4530 dst = call(dst, opts->load_context); |
|
351
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4531 *not_code = dst - (not_code+1); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4532 } |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4533 dst = retn(dst); |
|
2f264d2a60c2
Support for SRAM with SEGA mapper. Half-finished support for SRAM without SEGA mapper.
Mike Pavone <pavone@retrodev.com>
parents:
350
diff
changeset
|
4534 } else if (cfun) { |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4535 dst = call(dst, opts->save_context); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4536 #ifdef X86_64 |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4537 if (is_write) { |
|
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4538 if (SCRATCH2 != RDI) { |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4539 dst = mov_rr(dst, SCRATCH2, RDI, SZ_D); |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4540 } |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4541 dst = mov_rr(dst, SCRATCH1, RDX, size); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4542 } else { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4543 dst = push_r(dst, CONTEXT); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4544 dst = mov_rr(dst, SCRATCH1, RDI, SZ_D); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4545 } |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4546 dst = test_ir(dst, 8, RSP, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4547 code_ptr adjust_rsp = dst+1; |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4548 dst = jcc(dst, CC_NZ, dst+2); |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4549 dst = call(dst, cfun); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4550 code_ptr no_adjust = dst+1; |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4551 dst = jmp(dst, dst+2); |
|
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4552 *adjust_rsp = dst - (adjust_rsp + 1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4553 dst = sub_ir(dst, 8, RSP, SZ_PTR); |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4554 dst = call(dst, cfun); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4555 dst = add_ir(dst, 8, RSP, SZ_PTR); |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4556 *no_adjust = dst - (no_adjust+1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4557 #else |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4558 if (is_write) { |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4559 dst = push_r(dst, SCRATCH1); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4560 } else { |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4561 dst = push_r(dst, CONTEXT);//save CONTEXT for later |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4562 } |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4563 dst = push_r(dst, CONTEXT); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4564 dst = push_r(dst, is_write ? SCRATCH2 : SCRATCH1); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4565 dst = call(dst, cfun); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4566 dst = add_ir(dst, is_write ? 12 : 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4567 #endif |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4568 if (is_write) { |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4569 dst = mov_rr(dst, RAX, CONTEXT, SZ_PTR); |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4570 } else { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4571 dst = pop_r(dst, CONTEXT); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4572 dst = mov_rr(dst, RAX, SCRATCH1, size); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4573 } |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4574 dst = jmp(dst, opts->load_context); |
|
350
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4575 } else { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4576 //Not sure the best course of action here |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4577 if (!is_write) { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4578 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4579 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4580 dst = retn(dst); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4581 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4582 if (lb_jcc) { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4583 *lb_jcc = dst - (lb_jcc+1); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4584 lb_jcc = NULL; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4585 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4586 if (ub_jcc) { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4587 *ub_jcc = dst - (ub_jcc+1); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4588 ub_jcc = NULL; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4589 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4590 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4591 if (!is_write) { |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4592 dst = mov_ir(dst, size == SZ_B ? 0xFF : 0xFFFF, SCRATCH1, size); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4593 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4594 dst = retn(dst); |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4595 opts->cur_code = dst; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4596 return start; |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4597 } |
|
91aa2aa05e68
Refactor code gen for read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
348
diff
changeset
|
4598 |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4599 void init_x86_68k_opts(x86_68k_options * opts, memmap_chunk * memmap, uint32_t num_chunks) |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4600 { |
| 440 | 4601 memset(opts, 0, sizeof(*opts)); |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4602 for (int i = 0; i < 8; i++) |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4603 opts->dregs[i] = opts->aregs[i] = -1; |
|
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4604 #ifdef X86_64 |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4605 opts->dregs[0] = R10; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4606 opts->dregs[1] = R11; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4607 opts->dregs[2] = R12; |
|
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
4608 opts->dregs[3] = R8; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4609 opts->aregs[0] = R13; |
|
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4610 opts->aregs[1] = R14; |
|
423
8e136187c0e0
Use the registers that were freed up by the memory map function changes
Mike Pavone <pavone@retrodev.com>
parents:
352
diff
changeset
|
4611 opts->aregs[2] = R9; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
4612 opts->aregs[7] = R15; |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4613 |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4614 opts->flag_regs[0] = -1; |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4615 opts->flag_regs[1] = RBX; |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4616 opts->flag_regs[2] = RDX; |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4617 opts->flag_regs[3] = BH; |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4618 opts->flag_regs[4] = DH; |
|
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4619 #else |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4620 opts->dregs[0] = RDX; |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4621 opts->aregs[7] = RDI; |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4622 |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4623 for (int i = 0; i < 5; i++) |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4624 opts->flag_regs[i] = -1; |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4625 #endif |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4626 |
|
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4627 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4628 opts->gen.native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4629 memset(opts->gen.native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4630 opts->gen.deferred = NULL; |
|
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
4631 size_t size = 1024 * 1024; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4632 opts->gen.cur_code = alloc_code(&size); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4633 opts->gen.code_end = opts->gen.cur_code + size; |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4634 opts->gen.ram_inst_sizes = malloc(sizeof(code_ptr) * 64); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4635 memset(opts->gen.ram_inst_sizes, 0, sizeof(code_ptr) * 64); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4636 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4637 code_ptr dst = opts->gen.cur_code; |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4638 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4639 opts->gen.save_context = dst; |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4640 for (int i = 0; i < 5; i++) |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4641 if (opts->flag_regs[i] >= 0) { |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4642 dst = mov_rrdisp8(dst, opts->flag_regs[i], CONTEXT, offsetof(m68k_context, flags) + i, SZ_B); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4643 } |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4644 for (int i = 0; i < 8; i++) |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4645 { |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4646 if (opts->dregs[i] >= 0) { |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4647 dst = mov_rrdisp8(dst, opts->dregs[i], CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * i, SZ_D); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4648 } |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4649 if (opts->aregs[i] >= 0) { |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4650 dst = mov_rrdisp8(dst, opts->aregs[i], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * i, SZ_D); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4651 } |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4652 } |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4653 dst = mov_rrdisp8(dst, CYCLES, CONTEXT, offsetof(m68k_context, current_cycle), SZ_D); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4654 dst = retn(dst); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4655 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4656 opts->gen.load_context = dst; |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4657 for (int i = 0; i < 5; i++) |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4658 if (opts->flag_regs[i] >= 0) { |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4659 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + i, opts->flag_regs[i], SZ_B); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4660 } |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4661 for (int i = 0; i < 8; i++) |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4662 { |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4663 if (opts->dregs[i] >= 0) { |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4664 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * i, opts->dregs[i], SZ_D); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4665 } |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4666 if (opts->aregs[i] >= 0) { |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4667 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * i, opts->aregs[i], SZ_D); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4668 } |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4669 } |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4670 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, current_cycle), CYCLES, SZ_D); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4671 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, target_cycle), LIMIT, SZ_D); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4672 dst = retn(dst); |
|
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4673 |
|
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4674 opts->start_context = (start_fun)dst; |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4675 #ifdef X86_64 |
|
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4676 if (SCRATCH2 != RDI) { |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4677 dst = mov_rr(dst, RDI, SCRATCH2, SZ_PTR); |
|
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4678 } |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4679 //save callee save registers |
|
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4680 dst = push_r(dst, RBP); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4681 dst = push_r(dst, R12); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4682 dst = push_r(dst, R13); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4683 dst = push_r(dst, R14); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4684 dst = push_r(dst, R15); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4685 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4686 //save callee save registers |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4687 dst = push_r(dst, RBP); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4688 dst = push_r(dst, RBX); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4689 dst = push_r(dst, RSI); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4690 dst = push_r(dst, RDI); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4691 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4692 dst = mov_rdisp8r(dst, RSP, 20, SCRATCH2, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4693 dst = mov_rdisp8r(dst, RSP, 24, CONTEXT, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4694 #endif |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4695 dst = call(dst, opts->gen.load_context); |
|
548
a3afee2271ce
Initial work on the x86-32 target
Michael Pavone <pavone@retrodev.com>
parents:
547
diff
changeset
|
4696 dst = call_r(dst, SCRATCH2); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4697 dst = call(dst, opts->gen.save_context); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4698 #ifdef X86_64 |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4699 //restore callee save registers |
|
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4700 dst = pop_r(dst, R15); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4701 dst = pop_r(dst, R14); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4702 dst = pop_r(dst, R13); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4703 dst = pop_r(dst, R12); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4704 dst = pop_r(dst, RBP); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4705 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4706 dst = pop_r(dst, RDI); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4707 dst = pop_r(dst, RSI); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4708 dst = pop_r(dst, RBX); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4709 dst = pop_r(dst, RBP); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4710 #endif |
|
540
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4711 dst = retn(dst); |
|
4ca826862174
Generate m68k_start_context at runtime so it can use the generated load_context and save_context
Michael Pavone <pavone@retrodev.com>
parents:
539
diff
changeset
|
4712 |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4713 opts->native_addr = dst; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4714 dst = call(dst, opts->gen.save_context); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4715 dst = push_r(dst, CONTEXT); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4716 #ifdef X86_64 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4717 dst = mov_rr(dst, CONTEXT, RDI, SZ_PTR); //move context to 1st arg reg |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4718 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); //move address to 2nd arg reg |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4719 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4720 dst = push_r(dst, SCRATCH1); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4721 dst = push_r(dst, CONTEXT); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4722 #endif |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4723 dst = call(dst, (code_ptr)get_native_address_trans); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4724 #ifdef X86_32 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4725 dst = add_ir(dst, 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4726 #endif |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4727 dst = mov_rr(dst, RAX, SCRATCH1, SZ_PTR); //move result to scratch reg |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4728 dst = pop_r(dst, CONTEXT); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4729 dst = call(dst, opts->gen.load_context); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4730 dst = retn(dst); |
|
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4731 |
|
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4732 opts->native_addr_and_sync = dst; |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4733 dst = call(dst, opts->gen.save_context); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4734 dst = push_r(dst, SCRATCH1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4735 #ifdef X86_64 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4736 dst = mov_rr(dst, CONTEXT, RDI, SZ_PTR); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4737 dst = xor_rr(dst, RSI, RSI, SZ_D); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4738 dst = test_ir(dst, 8, RSP, SZ_PTR); //check stack alignment |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4739 code_ptr do_adjust_rsp = dst+1; |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4740 dst = jcc(dst, CC_NZ, dst+2); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4741 dst = call(dst, (code_ptr)sync_components); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4742 code_ptr no_adjust_rsp = dst+1; |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4743 dst = jmp(dst, dst+2); |
|
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4744 *do_adjust_rsp = dst - (do_adjust_rsp+1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4745 dst = sub_ir(dst, 8, RSP, SZ_PTR); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4746 dst = call(dst, (code_ptr)sync_components); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4747 dst = add_ir(dst, 8, RSP, SZ_PTR); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4748 *no_adjust_rsp = dst - (no_adjust_rsp+1); |
|
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4749 dst = pop_r(dst, RSI); |
|
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4750 dst = push_r(dst, RAX); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4751 dst = mov_rr(dst, RAX, RDI, SZ_PTR); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4752 dst = call(dst, (code_ptr)get_native_address_trans); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4753 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4754 //TODO: Add support for pushing a constant in gen_x86 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4755 dst = xor_rr(dst, RAX, RAX, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4756 dst = push_r(dst, RAX); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4757 dst = push_r(dst, CONTEXT); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4758 dst = call(dst, (code_ptr)sync_components); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4759 dst = add_ir(dst, 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4760 dst = pop_r(dst, RSI); //restore saved address from SCRATCH1 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4761 dst = push_r(dst, RAX); //save context pointer for later |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4762 dst = push_r(dst, RSI); //2nd arg -- address |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4763 dst = push_r(dst, RAX); //1st arg -- context pointer |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4764 dst = call(dst, (code_ptr)get_native_address_trans); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4765 dst = add_ir(dst, 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4766 #endif |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4767 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4768 dst = mov_rr(dst, RAX, SCRATCH1, SZ_PTR); //move result to scratch reg |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4769 dst = pop_r(dst, CONTEXT); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4770 dst = call(dst, opts->gen.load_context); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4771 dst = retn(dst); |
|
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4772 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4773 opts->gen.handle_cycle_limit = dst; |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4774 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), CYCLES, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4775 code_ptr skip_sync = dst+1; |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4776 dst = jcc(dst, CC_C, dst+2); |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4777 opts->do_sync = dst; |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4778 dst = push_r(dst, SCRATCH1); |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4779 dst = push_r(dst, SCRATCH2); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4780 dst = call(dst, opts->gen.save_context); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4781 #ifdef X86_64 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4782 dst = mov_rr(dst, CONTEXT, RDI, SZ_PTR); |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4783 dst = xor_rr(dst, RSI, RSI, SZ_D); |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4784 dst = test_ir(dst, 8, RSP, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4785 code_ptr adjust_rsp = dst+1; |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4786 dst = jcc(dst, CC_NZ, dst+2); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4787 dst = call(dst, (code_ptr)sync_components); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4788 code_ptr no_adjust = dst+1; |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4789 dst = jmp(dst, dst+2); |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4790 *adjust_rsp = dst - (adjust_rsp + 1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4791 dst = sub_ir(dst, 8, RSP, SZ_PTR); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4792 dst = call(dst, (code_ptr)sync_components); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4793 dst = add_ir(dst, 8, RSP, SZ_PTR); |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4794 *no_adjust = dst - (no_adjust+1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4795 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4796 //TODO: Add support for pushing a constant in gen_x86 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4797 dst = xor_rr(dst, RAX, RAX, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4798 dst = push_r(dst, RAX); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4799 dst = push_r(dst, CONTEXT); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4800 dst = call(dst, (code_ptr)sync_components); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4801 dst = add_ir(dst, 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4802 #endif |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4803 dst = mov_rr(dst, RAX, CONTEXT, SZ_PTR); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4804 dst = call(dst, opts->gen.load_context); |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4805 dst = pop_r(dst, SCRATCH2); |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4806 dst = pop_r(dst, SCRATCH1); |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4807 *skip_sync = dst - (skip_sync+1); |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4808 dst = retn(dst); |
|
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4809 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4810 opts->gen.cur_code = dst; |
|
539
c2716b502a81
Generate save_context and load_context functions at runtime
Michael Pavone <pavone@retrodev.com>
parents:
516
diff
changeset
|
4811 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4812 opts->read_16 = gen_mem_fun(&opts->gen, memmap, num_chunks, READ_16); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4813 opts->read_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, READ_8); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4814 opts->write_16 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_16); |
|
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4815 opts->write_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_8); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4816 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4817 dst = opts->gen.cur_code; |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4818 |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4819 opts->read_32 = dst; |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4820 dst = push_r(dst, SCRATCH1); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4821 dst = call(dst, opts->read_16); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4822 dst = mov_rr(dst, SCRATCH1, SCRATCH2, SZ_W); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4823 dst = pop_r(dst, SCRATCH1); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4824 dst = push_r(dst, SCRATCH2); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4825 dst = add_ir(dst, 2, SCRATCH1, SZ_D); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4826 dst = call(dst, opts->read_16); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4827 dst = pop_r(dst, SCRATCH2); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4828 dst = movzx_rr(dst, SCRATCH1, SCRATCH1, SZ_W, SZ_D); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4829 dst = shl_ir(dst, 16, SCRATCH2, SZ_D); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4830 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_D); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4831 dst = retn(dst); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4832 |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4833 opts->write_32_lowfirst = dst; |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4834 dst = push_r(dst, SCRATCH2); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4835 dst = push_r(dst, SCRATCH1); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4836 dst = add_ir(dst, 2, SCRATCH2, SZ_D); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4837 dst = call(dst, opts->write_16); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4838 dst = pop_r(dst, SCRATCH1); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4839 dst = pop_r(dst, SCRATCH2); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4840 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4841 dst = jmp(dst, opts->write_16); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4842 |
|
343
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4843 opts->write_32_highfirst = dst; |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4844 dst = push_r(dst, SCRATCH1); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4845 dst = push_r(dst, SCRATCH2); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4846 dst = shr_ir(dst, 16, SCRATCH1, SZ_D); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4847 dst = call(dst, opts->write_16); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4848 dst = pop_r(dst, SCRATCH2); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4849 dst = pop_r(dst, SCRATCH1); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4850 dst = add_ir(dst, 2, SCRATCH2, SZ_D); |
|
467bfa17004a
Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents:
324
diff
changeset
|
4851 dst = jmp(dst, opts->write_16); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4852 |
|
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4853 opts->get_sr = dst; |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4854 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, status), SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4855 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4856 if (opts->flag_regs[FLAG_X] >= 0) { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4857 dst = mov_rr(dst, opts->flag_regs[FLAG_X], SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4858 } else { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4859 int8_t offset = offsetof(m68k_context, flags); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4860 if (offset) { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4861 dst = mov_rdisp8r(dst, CONTEXT, offset, SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4862 } else { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4863 dst = mov_rindr(dst, CONTEXT, SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4864 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4865 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4866 for (int flag = FLAG_N; flag <= FLAG_C; flag++) |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4867 { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4868 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4869 if (opts->flag_regs[flag] >= 0) { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4870 dst = or_rr(dst, opts->flag_regs[flag], SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4871 } else { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4872 dst = or_rdisp8r(dst, CONTEXT, offsetof(m68k_context, flags) + flag, SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4873 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4874 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4875 dst = retn(dst); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4876 |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4877 opts->set_sr = dst; |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4878 for (int flag = FLAG_C; flag >= FLAG_X; flag--) |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4879 { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4880 dst = rcr_ir(dst, 1, SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4881 if (opts->flag_regs[flag] >= 0) { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4882 dst = setcc_r(dst, CC_C, opts->flag_regs[flag]); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4883 } else { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4884 int8_t offset = offsetof(m68k_context, flags) + flag; |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4885 if (offset) { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4886 dst = setcc_rdisp8(dst, CC_C, CONTEXT, offset); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4887 } else { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4888 dst = setcc_rind(dst, CC_C, CONTEXT); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4889 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4890 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4891 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4892 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4893 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4894 dst = retn(dst); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4895 |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4896 opts->set_ccr = dst; |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4897 for (int flag = FLAG_C; flag >= FLAG_X; flag--) |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4898 { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4899 dst = rcr_ir(dst, 1, SCRATCH1, SZ_B); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4900 if (opts->flag_regs[flag] >= 0) { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4901 dst = setcc_r(dst, CC_C, opts->flag_regs[flag]); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4902 } else { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4903 int8_t offset = offsetof(m68k_context, flags) + flag; |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4904 if (offset) { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4905 dst = setcc_rdisp8(dst, CC_C, CONTEXT, offset); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4906 } else { |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4907 dst = setcc_rind(dst, CC_C, CONTEXT); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4908 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4909 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4910 } |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4911 dst = retn(dst); |
|
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4912 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4913 opts->gen.handle_cycle_limit_int = dst; |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4914 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_cycle), CYCLES, SZ_D); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4915 code_ptr do_int = dst+1; |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4916 dst = jcc(dst, CC_NC, dst+2); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4917 dst = cmp_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), CYCLES, SZ_D); |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4918 skip_sync = dst+1; |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4919 dst = jcc(dst, CC_C, dst+2); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4920 dst = call(dst, opts->gen.save_context); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4921 #ifdef X86_64 |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4922 dst = mov_rr(dst, CONTEXT, RDI, SZ_PTR); |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4923 dst = mov_rr(dst, SCRATCH1, RSI, SZ_D); |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4924 dst = test_ir(dst, 8, RSP, SZ_D); |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4925 adjust_rsp = dst+1; |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4926 dst = jcc(dst, CC_NZ, dst+2); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4927 dst = call(dst, (code_ptr)sync_components); |
|
545
67cf0ce57d8d
Generate handle_cycle_limit at runtime so it can use the generated save/load_context functions. Since the hand written versions of save/load are no longer used they have been removed.
Michael Pavone <pavone@retrodev.com>
parents:
544
diff
changeset
|
4928 no_adjust = dst+1; |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4929 dst = jmp(dst, dst+2); |
|
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4930 *adjust_rsp = dst - (adjust_rsp + 1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4931 dst = sub_ir(dst, 8, RSP, SZ_PTR); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4932 dst = call(dst, (code_ptr)sync_components); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4933 dst = add_ir(dst, 8, RSP, SZ_PTR); |
|
485
b449af228c63
Follow amd64 ABI stack alignment requirements in places it matters so we can call sprintf with floating point arguments without crashing
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
4934 *no_adjust = dst - (no_adjust+1); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4935 #else |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4936 dst = push_r(dst, SCRATCH1); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4937 dst = push_r(dst, CONTEXT); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4938 dst = call(dst, (code_ptr)sync_components); |
|
550
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4939 dst = add_ir(dst, 8, RSP, SZ_D); |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4940 #endif |
|
96489fb27dbf
Apart from the Z80 core, BlastEm now supports 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents:
548
diff
changeset
|
4941 dst = mov_rr(dst, RAX, CONTEXT, SZ_PTR); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4942 dst = jmp(dst, opts->gen.load_context); |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4943 *skip_sync = dst - (skip_sync+1); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4944 dst = retn(dst); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4945 *do_int = dst - (do_int+1); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4946 //set target cycle to sync cycle |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4947 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, sync_cycle), LIMIT, SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4948 //swap USP and SSP if not already in supervisor mode |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4949 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
4950 code_ptr already_supervisor = dst+1; |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4951 dst = jcc(dst, CC_C, dst+2); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4952 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4953 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4954 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4955 *already_supervisor = dst - (already_supervisor+1); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4956 //save PC |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4957 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4958 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4959 dst = call(dst, opts->write_32_lowfirst); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4960 //save status register |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4961 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D); |
|
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4962 dst = call(dst, opts->get_sr); |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4963 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4964 dst = call(dst, opts->write_16); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4965 //update status register |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4966 dst = and_irdisp8(dst, 0xF8, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4967 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_B); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4968 dst = or_ir(dst, 0x20, SCRATCH1, SZ_B); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4969 dst = or_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4970 //calculate interrupt vector address |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4971 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, int_num), SCRATCH1, SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4972 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, int_ack), SZ_W); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4973 dst = shl_ir(dst, 2, SCRATCH1, SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4974 dst = add_ir(dst, 0x60, SCRATCH1, SZ_D); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4975 dst = call(dst, opts->read_32); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
4976 dst = call(dst, opts->native_addr_and_sync); |
|
347
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4977 dst = cycles(dst, 24); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4978 //discard function return address |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4979 dst = pop_r(dst, SCRATCH2); |
|
b24556b45d1e
Generate handle_cycle_limit_int at runtime so it can refer to the runtime generated memory map functions
Mike Pavone <pavone@retrodev.com>
parents:
343
diff
changeset
|
4980 dst = jmp_r(dst, SCRATCH1); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
4981 |
|
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4982 opts->trap = dst; |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4983 dst = push_r(dst, SCRATCH2); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4984 //swap USP and SSP if not already in supervisor mode |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4985 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4986 already_supervisor = dst+1; |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4987 dst = jcc(dst, CC_C, dst+2); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4988 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4989 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4990 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4991 *already_supervisor = dst - (already_supervisor+1); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4992 //save PC |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4993 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4994 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4995 dst = call(dst, opts->write_32_lowfirst); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4996 //save status register |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4997 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D); |
|
547
3090d016c9e9
Generate get_sr, set_sr and set_ccr at runtime so they can respect the flag_regs setting
Michael Pavone <pavone@retrodev.com>
parents:
546
diff
changeset
|
4998 dst = call(dst, opts->get_sr); |
|
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
4999 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5000 dst = call(dst, opts->write_16); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5001 //set supervisor bit |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5002 dst = or_irdisp8(dst, 0x20, CONTEXT, offsetof(m68k_context, status), SZ_B); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5003 //calculate vector address |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5004 dst = pop_r(dst, SCRATCH1); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5005 dst = shl_ir(dst, 2, SCRATCH1, SZ_D); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5006 dst = call(dst, opts->read_32); |
|
544
8a26567852b7
Generate native_addr and native_addr_and_sync at runtime so they can use the generated save/load_context functions
Michael Pavone <pavone@retrodev.com>
parents:
543
diff
changeset
|
5007 dst = call(dst, opts->native_addr_and_sync); |
|
348
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5008 dst = cycles(dst, 18); |
|
3923dbc2dcc4
m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
Mike Pavone <pavone@retrodev.com>
parents:
347
diff
changeset
|
5009 dst = jmp_r(dst, SCRATCH1); |
|
447
e730fc040169
Fix performance regression from stop instruction work
Mike Pavone <pavone@retrodev.com>
parents:
446
diff
changeset
|
5010 |
|
558
dc9f178085a0
Use a typedef code_ptr in place of uint8_t * in 68K core to better support host instruction sets with different instruction word sizes. Make x86_68k_options contain a cpu_options so that gen_mem_fun can eventually be shared with the Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
557
diff
changeset
|
5011 opts->gen.cur_code = dst; |
|
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
14
diff
changeset
|
5012 } |
|
3e7bfde7606e
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5013 |
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5014 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) |
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5015 { |
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5016 memset(context, 0, sizeof(m68k_context)); |
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5017 context->native_code_map = native_code_map; |
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5018 context->options = opts; |
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Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
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5019 context->int_cycle = 0xFFFFFFFF; |
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Initialize status register to proper value on startup
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5020 context->status = 0x27; |
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5021 } |
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5022 |