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annotate z80_to_x86.c @ 1045:e0489abfdab0

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Implement half-carry for INC, DEC and NEG
author Michael Pavone <pavone@retrodev.com>
date Tue, 26 Jul 2016 00:11:33 -0700
parents 1625555e346e
children a27fdf43f1a7
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1 /*
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2 Copyright 2013 Michael Pavone
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b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include "z80inst.h"
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7 #include "z80_to_x86.h"
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8 #include "gen_x86.h"
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9 #include "mem.h"
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10 #include "util.h"
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11 #include <stdio.h>
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12 #include <stdlib.h>
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13 #include <stddef.h>
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14 #include <string.h>
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15
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16 #define MODE_UNUSED (MODE_IMMED-1)
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17 #define MAX_MCYCLE_LENGTH 6
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18
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19 //#define DO_DEBUG_PRINT
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20
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21 #ifdef DO_DEBUG_PRINT
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22 #define dprintf printf
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23 #else
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24 #define dprintf
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25 #endif
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26
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27 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst);
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28 void z80_handle_deferred(z80_context * context);
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29
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30 uint8_t z80_size(z80inst * inst)
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31 {
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32 uint8_t reg = (inst->reg & 0x1F);
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33 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
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34 return reg < Z80_BC ? SZ_B : SZ_W;
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35 }
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36 //TODO: Handle any necessary special cases
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37 return SZ_B;
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38 }
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39
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40 uint8_t zf_off(uint8_t flag)
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41 {
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42 return offsetof(z80_context, flags) + flag;
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43 }
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44
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45 uint8_t zaf_off(uint8_t flag)
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46 {
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47 return offsetof(z80_context, alt_flags) + flag;
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48 }
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49
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50 uint8_t zr_off(uint8_t reg)
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51 {
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52 if (reg > Z80_A) {
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53 reg = z80_low_reg(reg);
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54 }
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55 return offsetof(z80_context, regs) + reg;
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56 }
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57
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58 uint8_t zar_off(uint8_t reg)
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59 {
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60 if (reg > Z80_A) {
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61 reg = z80_low_reg(reg);
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62 }
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63 return offsetof(z80_context, alt_regs) + reg;
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64 }
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65
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66 void zreg_to_native(z80_options *opts, uint8_t reg, uint8_t native_reg)
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67 {
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68 if (opts->regs[reg] >= 0) {
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69 mov_rr(&opts->gen.code, opts->regs[reg], native_reg, reg > Z80_A ? SZ_W : SZ_B);
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70 } else {
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71 mov_rdispr(&opts->gen.code, opts->gen.context_reg, zr_off(reg), native_reg, reg > Z80_A ? SZ_W : SZ_B);
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72 }
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73 }
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74
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75 void native_to_zreg(z80_options *opts, uint8_t native_reg, uint8_t reg)
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76 {
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77 if (opts->regs[reg] >= 0) {
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78 mov_rr(&opts->gen.code, native_reg, opts->regs[reg], reg > Z80_A ? SZ_W : SZ_B);
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79 } else {
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80 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, zr_off(reg), reg > Z80_A ? SZ_W : SZ_B);
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81 }
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82 }
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83
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84 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts)
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85 {
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86 code_info *code = &opts->gen.code;
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87 if (inst->reg == Z80_USE_IMMED) {
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88 ea->mode = MODE_IMMED;
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89 ea->disp = inst->immed;
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90 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
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91 ea->mode = MODE_UNUSED;
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92 } else {
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93 ea->mode = MODE_REG_DIRECT;
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94 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
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95 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
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96 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
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97 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
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98 ea->base = opts->gen.scratch1;
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99 } else {
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100 ea->base = opts->regs[Z80_IYL];
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101 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
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102 }
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103 } else if(opts->regs[inst->reg] >= 0) {
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104 ea->base = opts->regs[inst->reg];
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105 if (ea->base >= AH && ea->base <= BH) {
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106 if ((inst->addr_mode & 0x1F) == Z80_REG) {
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107 uint8_t other_reg = opts->regs[inst->ea_reg];
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108 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
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109 //we can't mix an *H reg with a register that requires the REX prefix
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110 ea->base = opts->regs[z80_low_reg(inst->reg)];
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111 ror_ir(code, 8, ea->base, SZ_W);
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112 }
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113 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
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114 //temp regs require REX prefix too
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115 ea->base = opts->regs[z80_low_reg(inst->reg)];
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116 ror_ir(code, 8, ea->base, SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
117 }
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
118 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
119 } else {
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
120 ea->mode = MODE_REG_DISPLACE8;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
121 ea->base = opts->gen.context_reg;
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
122 ea->disp = zr_off(inst->reg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
123 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
124 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
125 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
126
590
ea80559c67cb WIP effort to update z80 core for code gen changes
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parents: 506
diff changeset
127 void z80_save_reg(z80inst * inst, z80_options * opts)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
128 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
129 code_info *code = &opts->gen.code;
716
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
130 if (inst->reg == Z80_USE_IMMED || inst->reg == Z80_UNUSED) {
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
131 return;
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
132 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
133 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
134 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
135 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
136 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
137 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
138 } else {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
139 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
140 }
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
141 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
142 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
143 uint8_t other_reg = opts->regs[inst->ea_reg];
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
144 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
145 //we can't mix an *H reg with a register that requires the REX prefix
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
146 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
147 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
148 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
149 //temp regs require REX prefix too
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
150 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
151 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
152 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
153 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
154
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
155 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
156 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
157 code_info *code = &opts->gen.code;
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
158 uint8_t size, areg;
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
159 int8_t reg;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
160 ea->mode = MODE_REG_DIRECT;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
161 areg = read ? opts->gen.scratch1 : opts->gen.scratch2;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
162 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
163 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
164 case Z80_REG:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
165 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
166 if (inst->reg == Z80_IYL) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
167 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
168 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
169 ea->base = opts->gen.scratch1;
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
170 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
171 ea->base = opts->regs[Z80_IYL];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
172 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
173 }
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
174 } else if(opts->regs[inst->ea_reg] >= 0) {
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
175 ea->base = opts->regs[inst->ea_reg];
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
176 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
177 uint8_t other_reg = opts->regs[inst->reg];
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
178 #ifdef X86_64
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
179 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
180 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
181 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
182 ror_ir(code, 8, ea->base, SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
183 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
184 #endif
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
185 }
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
186 } else {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
187 ea->mode = MODE_REG_DISPLACE8;
659
759c38bf97f8 Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents: 657
diff changeset
188 ea->base = opts->gen.context_reg;
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
189 ea->disp = zr_off(inst->ea_reg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
190 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
191 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 case Z80_REG_INDIRECT:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
193 zreg_to_native(opts, inst->ea_reg, areg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
195 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 if (modify) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
197 //push_r(code, opts->gen.scratch1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
198 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
199 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
200 if (size == SZ_B) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
201 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
203 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
205 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
206 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
208 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 case Z80_IMMED_INDIRECT:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
213 mov_ir(code, inst->immed, areg, SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
215 if (read) {
277
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller
Mike Pavone <pavone@retrodev.com>
parents: 275
diff changeset
216 /*if (modify) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
217 push_r(code, opts->gen.scratch1);
277
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller
Mike Pavone <pavone@retrodev.com>
parents: 275
diff changeset
218 }*/
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
219 if (size == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
220 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 } else {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
222 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
224 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
225 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226 break;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
227 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
228 case Z80_IY_DISPLACE:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
229 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, areg);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
230 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
231 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
232 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 if (modify) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
234 //push_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
235 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237 if (size == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
238 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 } else {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
240 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
243 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
245 case Z80_UNUSED:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
246 ea->mode = MODE_UNUSED;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
247 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
248 default:
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
249 fatal_error("Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
251 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
252
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
253 void z80_save_ea(code_info *code, z80inst * inst, z80_options * opts)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
254 {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
255 if ((inst->addr_mode & 0x1F) == Z80_REG) {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
256 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
257 if (inst->reg == Z80_IYL) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
258 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
259 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
260 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
261 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
262 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
263 }
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
264 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
265 uint8_t other_reg = opts->regs[inst->reg];
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
266 #ifdef X86_64
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
267 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
268 //we can't mix an *H reg with a register that requires the REX prefix
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
269 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
270 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
271 #endif
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
272 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
273 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
274 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
275
593
5ef3fe516da9 Z80 core is sort of working again
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parents: 592
diff changeset
276 void z80_save_result(z80_options *opts, z80inst * inst)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
277 {
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
278 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
279 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
280 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
281 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
282 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
283 case Z80_IY_DISPLACE:
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
284 if (inst->op != Z80_LD) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
285 mov_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
286 }
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
287 if (z80_size(inst) == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
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parents: 592
diff changeset
288 call(&opts->gen.code, opts->write_8);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
289 } else {
593
5ef3fe516da9 Z80 core is sort of working again
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parents: 592
diff changeset
290 call(&opts->gen.code, opts->write_16_lowfirst);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
291 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
292 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
293 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
294
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
295 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
296 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
297 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
298 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
299
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
300 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
301 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
303 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
305 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
306 {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
307 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
308 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
309 context->regs[Z80_D], context->regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
310 (context->regs[Z80_H] << 8) | context->regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
311 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
312 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL],
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
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parents: 242
diff changeset
313 context->sp, context->im, context->iff1, context->iff2);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
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parents: 239
diff changeset
314 puts("--Alternate Regs--");
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
315 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
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parents: 239
diff changeset
316 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
317 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
318 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
319 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL],
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
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parents: 239
diff changeset
320 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]);
235
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parents: 213
diff changeset
321 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
322 }
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
323
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
324 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
325 {
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
326 uint32_t num_cycles;
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
327 host_ea src_op, dst_op;
235
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
328 uint8_t size;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
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parents: 506
diff changeset
329 z80_options *opts = context->options;
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
330 uint8_t * start = opts->gen.code.cur;
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parents: 590
diff changeset
331 code_info *code = &opts->gen.code;
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
332 if (!interp) {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
333 check_cycles_int(&opts->gen, address);
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
334 if (context->breakpoint_flags[address / 8] & (1 << (address % 8))) {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
335 zbreakpoint_patch(context, address, start);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
336 }
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
337 num_cycles = 4 * inst->opcode_bytes;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
338 //TODO: increment R register once for every opcode byte
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
339 #ifdef Z80_LOG_ADDRESS
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
340 log_address(&opts->gen, address, "Z80: %X @ %d\n");
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
341 #endif
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
342 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
344 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 case Z80_LD:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
346 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
347 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
348 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
349 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
350 case Z80_REG_INDIRECT:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
351 if (size != SZ_B) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
352 num_cycles += 2;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
353 }
841
58606d16d35c Fix timing of certain variants of LD
Michael Pavone <pavone@retrodev.com>
parents: 840
diff changeset
354 if (inst->reg == Z80_I || inst->ea_reg == Z80_I || inst->reg == Z80_R || inst->ea_reg == Z80_R) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
355 num_cycles += 1;
506
a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
356 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
357 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
358 case Z80_IMMED:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
359 num_cycles += size == SZ_B ? 3 : 6;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
360 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
361 case Z80_IMMED_INDIRECT:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
362 num_cycles += 6;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
363 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
364 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
365 case Z80_IY_DISPLACE:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
366 num_cycles = 8; //3 for displacement, 5 for address addition
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
367 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
368 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
369 cycles(&opts->gen, num_cycles);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
370 if (inst->addr_mode & Z80_DIR) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
371 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
372 translate_z80_reg(inst, &src_op, opts);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
373 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
374 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
375 translate_z80_reg(inst, &dst_op, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
376 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
377 if (src_op.mode == MODE_REG_DIRECT) {
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
378 if(dst_op.mode == MODE_REG_DISPLACE8) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
379 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
380 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
381 mov_rr(code, src_op.base, dst_op.base, size);
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
382 }
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
383 } else if(src_op.mode == MODE_IMMED) {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
384 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
385 mov_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
386 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
387 mov_ir(code, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
388 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
390 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
391 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
392 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
393 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
394 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
395 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
396 }
842
ba93a3941300 Set flags for ld a, r
Michael Pavone <pavone@retrodev.com>
parents: 841
diff changeset
397 if ((inst->ea_reg == Z80_I || inst->ea_reg == Z80_R) && inst->addr_mode == Z80_REG) {
ba93a3941300 Set flags for ld a, r
Michael Pavone <pavone@retrodev.com>
parents: 841
diff changeset
398 //ld a, i and ld a, r sets some flags
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
399 cmp_ir(code, 0, dst_op.base, SZ_B);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
400 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
401 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
821
21a69dfb6ee7 Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents: 819
diff changeset
402 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
403 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);;
659
759c38bf97f8 Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents: 657
diff changeset
404 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
405 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
406 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
407 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
408 z80_save_ea(code, inst, opts);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
409 if (inst->addr_mode & Z80_DIR) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
410 z80_save_result(opts, inst);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
411 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
412 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413 case Z80_PUSH:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
414 cycles(&opts->gen, num_cycles + 1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
415 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
416 if (inst->reg == Z80_AF) {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
417 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
418 shl_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
419 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
420 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
421 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
422 shl_ir(code, 2, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
423 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
424 shl_ir(code, 2, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
425 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
426 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
427 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
428 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
429 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
430 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
431 zreg_to_native(opts, inst->reg, opts->gen.scratch1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
432 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
433 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
434 call(code, opts->write_16_highfirst);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
435 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
436 //the upper half of a register pair
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
437 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
438 case Z80_POP:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
439 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
440 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
441 call(code, opts->read_16);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
442 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
443 if (inst->reg == Z80_AF) {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
444
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
445 bt_ir(code, 0, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
446 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
447 bt_ir(code, 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
448 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
449 bt_ir(code, 2, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
450 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
451 bt_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
452 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
453 bt_ir(code, 6, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
454 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
455 bt_ir(code, 7, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
456 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
457 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
458 native_to_zreg(opts, opts->gen.scratch1, Z80_A);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
459 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
460 native_to_zreg(opts, opts->gen.scratch1, inst->reg);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
461 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
462 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
463 //the upper half of a register pair
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
464 break;
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
465 case Z80_EX:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
466 cycles(&opts->gen, num_cycles);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
467 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
468 if(inst->reg == Z80_AF) {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
469 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
470 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->gen.scratch2, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
471 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
472 native_to_zreg(opts, opts->gen.scratch2, Z80_A);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
473
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
474 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
475 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
476 for (int f = ZF_C; f < ZF_NUM; f+=2) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
477 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
478 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
479 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
480 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
481 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
482 } else {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
483 if (opts->regs[Z80_DE] >= 0 && opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
484 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
485 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
486 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
487 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
488 native_to_zreg(opts, opts->gen.scratch1, Z80_HL);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
489 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
490 }
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
491 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
492 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
493 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
494 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
495 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
496 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
497 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
498 zreg_to_native(opts, inst->reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
499 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
500 native_to_zreg(opts, opts->gen.scratch2, inst->reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
501 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
502 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
503 call(code, opts->write_8);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
504 cycles(&opts->gen, 1);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
505 uint8_t high_reg = z80_high_reg(inst->reg);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
506 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
507 add_ir(code, 1, opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
508 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
509 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
510 //even though some of the upper halves can be used directly
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
511 //the limitations on mixing *H regs with the REX prefix
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
512 //prevent us from taking advantage of it
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
513 uint8_t use_reg = opts->regs[inst->reg];
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
514 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
515 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
516 //restore reg to normal rotation
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
517 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
518 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
519 zreg_to_native(opts, high_reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
520 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
521 native_to_zreg(opts, opts->gen.scratch2, high_reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
522 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
523 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
524 add_ir(code, 1, opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
525 call(code, opts->write_8);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
526 cycles(&opts->gen, 2);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
527 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
528 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
529 case Z80_EXX:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
530 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
531 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
532 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
533 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
534 native_to_zreg(opts, opts->gen.scratch2, Z80_BC);
840
5822c6e5642f Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents: 828
diff changeset
535
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
536 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
537 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
538 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
539 native_to_zreg(opts, opts->gen.scratch2, Z80_HL);
840
5822c6e5642f Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents: 828
diff changeset
540
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
541 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
542 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
543 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
544 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
545 break;
272
9b04b57434b5 Implement LDI
Mike Pavone <pavone@retrodev.com>
parents: 269
diff changeset
546 case Z80_LDI: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
547 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
548 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
549 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
550 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
551 call(code, opts->write_8);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
552 cycles(&opts->gen, 2);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
553 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
554 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
555 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
556 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
557 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
558 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
559 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
560 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
561 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
562 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
563 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
564 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
565 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
566 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
567 }
821
21a69dfb6ee7 Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents: 819
diff changeset
568 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
569 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
570 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
272
9b04b57434b5 Implement LDI
Mike Pavone <pavone@retrodev.com>
parents: 269
diff changeset
571 break;
9b04b57434b5 Implement LDI
Mike Pavone <pavone@retrodev.com>
parents: 269
diff changeset
572 }
261
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
573 case Z80_LDIR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
574 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
575 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
576 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
577 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
578 call(code, opts->write_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
579 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
580 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
581 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
582 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
583 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
584 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
585 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
586 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
587 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
588 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
589 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
590 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
591 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
592 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
593 }
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
594 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
595 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
596 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
597 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
598 cycles(&opts->gen, 7);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
599 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
600 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
601 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
602 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
603 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
261
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
604 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
605 }
273
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
606 case Z80_LDD: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
607 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
608 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
609 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
610 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
611 call(code, opts->write_8);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
612 cycles(&opts->gen, 2);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
613 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
614 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
615 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
616 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
617 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
618 if (opts->regs[Z80_HL] >= 0) {
828
22c3c52b9871 Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions.
Michael Pavone <pavone@retrodev.com>
parents: 821
diff changeset
619 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
620 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
621 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
622 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
623 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
624 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
625 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
626 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
627 }
821
21a69dfb6ee7 Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents: 819
diff changeset
628 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
629 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
630 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
273
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
631 break;
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
632 }
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
633 case Z80_LDDR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
634 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
635 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
636 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
637 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
638 call(code, opts->write_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
639 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
640 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
641 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
642 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
643 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
644 if (opts->regs[Z80_HL] >= 0) {
828
22c3c52b9871 Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions.
Michael Pavone <pavone@retrodev.com>
parents: 821
diff changeset
645 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
646 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
647 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
648 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
649 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
650 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
651 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
652 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
653 }
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
654 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
655 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
656 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
657 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
658 cycles(&opts->gen, 7);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
659 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
660 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
661 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
662 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
663 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
273
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
664 break;
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
665 }
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
666 case Z80_CPI:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
667 cycles(&opts->gen, num_cycles);//T-States 4,4
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
668 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
669 call(code, opts->read_8);//T-States 3
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
670 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
671 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
672 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
673 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
674 //TODO: Implement half-carry flag
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
675 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
676 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
677 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
678 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
679 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
680 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
681 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
682 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
683 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
684 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
685 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
686 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
687 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
688 case Z80_CPIR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
689 cycles(&opts->gen, num_cycles);//T-States 4,4
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
690 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
691 call(code, opts->read_8);//T-States 3
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
692 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
693 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
694 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
695 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
696 //TODO: Implement half-carry flag
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
697 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
698 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
699 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
700 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
701 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
702 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
703 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
704 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
705 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
706 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
707 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
708 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
709 uint8_t * cont = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
710 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
711 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
712 uint8_t * cont2 = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
713 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
714 //repeat case
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
715 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
716 jmp(code, start);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
717 *cont = code->cur - (cont + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
718 *cont2 = code->cur - (cont2 + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
719 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
720 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
721 case Z80_CPD:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
722 cycles(&opts->gen, num_cycles);//T-States 4,4
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
723 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
724 call(code, opts->read_8);//T-States 3
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
725 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
726 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
727 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
728 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
729 //TODO: Implement half-carry flag
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
730 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
731 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
732 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
733 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
734 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
735 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
736 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
737 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
738 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
739 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
740 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
741 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
742 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
743 case Z80_CPDR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
744 cycles(&opts->gen, num_cycles);//T-States 4,4
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
745 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
746 call(code, opts->read_8);//T-States 3
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
747 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
748 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
749 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
750 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
751 //TODO: Implement half-carry flag
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
752 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
753 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
754 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
755 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
756 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
757 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
758 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
759 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
760 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
761 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
762 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
763 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
764 uint8_t * cont = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
765 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
766 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
767 uint8_t * cont2 = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
768 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
769 //repeat case
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
770 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
771 jmp(code, start);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
772 *cont = code->cur - (cont + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
773 *cont2 = code->cur - (cont2 + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
774 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
775 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
776 case Z80_ADD:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
777 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
778 num_cycles += 8;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
779 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
780 num_cycles += 3;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
781 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
782 num_cycles += 4;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
783 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
784 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
785 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
786 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
787 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
788 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
789 add_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
790 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
791 add_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
792 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
793 add_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
794 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
795 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
796 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
797 add_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
798 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
799 add_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
800 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
801 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
802 add_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
803 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
804 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
805 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
806 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
807 //TODO: Implement half-carry flag
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
808 if (z80_size(inst) == SZ_B) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
809 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
810 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
811 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
812 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
813 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
814 z80_save_ea(code, inst, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
815 break;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
816 case Z80_ADC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
817 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
818 num_cycles += 8;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
819 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
820 num_cycles += 3;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
821 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
822 num_cycles += 4;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
823 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
824 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
825 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
826 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
827 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
828 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
829 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
830 adc_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
831 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
832 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
833 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
834 adc_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
835 }
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
836 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
837 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
838 adc_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
839 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
840 adc_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
841 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
842 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
843 adc_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
844 }
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
845 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
846 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
847 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
848 //TODO: Implement half-carry flag
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
849 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
850 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
851 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
852 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
853 z80_save_ea(code, inst, opts);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
854 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
855 case Z80_SUB:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
856 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
857 num_cycles += 8;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
858 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
859 num_cycles += 3;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
860 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
861 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
862 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
863 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
864 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
865 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
866 sub_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
867 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
868 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
869 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
870 sub_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
871 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
872 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
873 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
874 sub_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
875 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
876 sub_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
877 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
878 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
879 sub_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
880 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
881 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
882 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
883 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
884 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
885 //TODO: Implement half-carry flag
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
886 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
887 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
888 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
889 z80_save_ea(code, inst, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
890 break;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
891 case Z80_SBC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
892 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
893 num_cycles += 8;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
894 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
895 num_cycles += 3;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
896 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
897 num_cycles += 4;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
898 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
899 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
900 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
901 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
902 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
903 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
904 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
905 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
906 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
907 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
908 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
909 sbb_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
910 }
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
911 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
912 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
913 sbb_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
914 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
915 sbb_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
916 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
917 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
918 sbb_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
919 }
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
920 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
921 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
922 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
923 //TODO: Implement half-carry flag
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
924 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
925 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
926 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
927 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
928 z80_save_ea(code, inst, opts);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
929 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
930 case Z80_AND:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
931 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
932 num_cycles += 8;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
933 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
934 num_cycles += 3;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
935 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
936 num_cycles += 4;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
937 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
938 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
939 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
940 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
941 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
942 and_rr(code, src_op.base, dst_op.base, z80_size(inst));
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
943 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
944 and_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
945 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
946 and_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
947 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
948 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
949 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
950 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
951 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
952 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
953 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
954 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
955 z80_save_ea(code, inst, opts);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
956 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
957 case Z80_OR:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
958 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
959 num_cycles += 8;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
960 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
961 num_cycles += 3;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
962 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
963 num_cycles += 4;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
964 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
965 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
966 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
967 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
968 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
969 or_rr(code, src_op.base, dst_op.base, z80_size(inst));
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
970 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
971 or_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
972 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
973 or_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
974 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
975 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
976 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
977 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
978 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
979 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
980 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
981 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
982 z80_save_ea(code, inst, opts);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
983 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
984 case Z80_XOR:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
985 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
986 num_cycles += 8;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
987 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
988 num_cycles += 3;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
989 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
990 num_cycles += 4;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
991 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
992 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
993 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
994 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
995 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
996 xor_rr(code, src_op.base, dst_op.base, z80_size(inst));
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
997 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
998 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
999 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1000 xor_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1001 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1002 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1003 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1004 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1005 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1006 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1007 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1008 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1009 z80_save_ea(code, inst, opts);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1010 break;
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1011 case Z80_CP:
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1012 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1013 num_cycles += 8;
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1014 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1015 num_cycles += 3;
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1016 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1017 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1018 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1019 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1020 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1021 cmp_rr(code, src_op.base, dst_op.base, z80_size(inst));
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1022 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1023 cmp_ir(code, src_op.disp, dst_op.base, z80_size(inst));
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1024 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1025 cmp_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1026 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1027 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1028 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1029 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1030 //TODO: Implement half-carry flag
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1031 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1032 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1033 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1034 z80_save_ea(code, inst, opts);
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1035 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1036 case Z80_INC:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1037 case Z80_DEC:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1038 if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1039 num_cycles += 2;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1040 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1041 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1042 translate_z80_reg(inst, &dst_op, opts);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1043 if (dst_op.mode == MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1044 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1045 }
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1046 if (z80_size(inst) == SZ_B) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1047 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1048 if (dst_op.base >= AH && dst_op.base <= BH) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1049 mov_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1050 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1051 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1052 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1053 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1054 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1055 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1056 }
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1057 if (inst->op == Z80_INC) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1058 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1059 add_ir(code, 1, dst_op.base, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1060 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1061 add_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1062 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1063 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1064 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1065 sub_ir(code, 1, dst_op.base, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1066 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1067 sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1068 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1069 }
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1070 if (z80_size(inst) == SZ_B) {
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1071 mov_irdisp(code, inst->op == Z80_DEC, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1072 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1073 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1074 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1075 int bit = 4;
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1076 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1077 if (dst_op.base >= AH && dst_op.base <= BH) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1078 bit = 12;
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1079 xor_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1080 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1081 xor_rr(code, dst_op.base, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1082 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1083 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1084 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1085 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1086 bt_ir(code, bit, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1087 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1088 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1089 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1090 z80_save_ea(code, inst, opts);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1091 z80_save_result(opts, inst);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1092 break;
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1093 case Z80_DAA:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1094 cycles(&opts->gen, num_cycles);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1095 xor_rr(code, opts->gen.scratch2, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1096 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1097 code_ptr corf_low = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1098 jcc(code, CC_NZ, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1099 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1100 and_ir(code, 0xF, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1101 cmp_ir(code, 0xA, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1102
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1103 code_ptr no_corf_low = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1104 jcc(code, CC_C, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1105 *corf_low = code->cur - (corf_low + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1106 mov_ir(code, 6, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1107 mov_ir(code, 0x90, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1108 code_ptr after_cmp_set = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1109 jmp(code, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1110
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1111 *no_corf_low = code->cur - (no_corf_low + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1112 mov_ir(code, 0xA0, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1113 *after_cmp_set = code->cur - (after_cmp_set + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1114 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1115 code_ptr corf_high = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1116 jcc(code, CC_NZ, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1117 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1118 code_ptr no_corf_high = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1119 jcc(code, CC_C, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1120 *corf_high = code->cur - (corf_high + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1121 or_ir(code, 0x60, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1122 *no_corf_high = code->cur - (no_corf_high + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1123
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1124 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1125 code_ptr not_sub = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1126 jcc(code, CC_Z, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1127 neg_r(code, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1128 *not_sub = code->cur - (not_sub + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1129 add_rr(code, opts->gen.scratch2, opts->regs[Z80_A], SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1130 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1131 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1132 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1133 code_ptr no_carry = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1134 jcc(code, CC_NC, code->cur+2);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
1135 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1136 *no_carry = code->cur - (no_carry + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1137 //TODO: Implement half-carry flag
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1138 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1139 case Z80_CPL:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1140 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1141 not_r(code, opts->regs[Z80_A], SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1142 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1143 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274
be2b845d3e94 Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents: 273
diff changeset
1144 break;
be2b845d3e94 Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents: 273
diff changeset
1145 case Z80_NEG:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1146 cycles(&opts->gen, num_cycles);
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1147 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1148 neg_r(code, opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1149 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1150 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1151 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1152 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1153 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1154 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1155 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1156 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
274
be2b845d3e94 Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents: 273
diff changeset
1157 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1158 case Z80_CCF:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1159 cycles(&opts->gen, num_cycles);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1160 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1161 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1162 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1163 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
257
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
1164 break;
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
1165 case Z80_SCF:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1166 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1167 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1168 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1169 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
257
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
1170 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1171 case Z80_NOP:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1172 cycles(&opts->gen, num_cycles);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1173 break;
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1174 case Z80_HALT: {
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1175 code_ptr loop_top = code->cur;
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1176 //this isn't terribly efficient, but it's good enough for now
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1177 cycles(&opts->gen, num_cycles);
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1178 check_cycles_int(&opts->gen, address);
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1179 jmp(code, loop_top);
285
021aeb6df19b Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents: 284
diff changeset
1180 break;
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1181 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1182 case Z80_DI:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1183 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1184 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1185 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1186 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.limit, SZ_D);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1187 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D);
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
1188 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1189 case Z80_EI:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1190 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1191 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1192 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1193 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
335
14a937097c2b Some Z80 interrupt fixes
Mike Pavone <pavone@retrodev.com>
parents: 315
diff changeset
1194 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1195 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1196 call(code, opts->do_sync);
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
1197 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1198 case Z80_IM:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1199 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1200 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
1201 break;
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1202 case Z80_RLC:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1203 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1204 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1205 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1206 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1207 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1208 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1209 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1210 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1211 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1212 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1213 translate_z80_reg(inst, &dst_op, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1214 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1215 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1216 rol_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1217 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1218 rol_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1219 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1220 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1221 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1222 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1223 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1224 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1225 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1226 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1227 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1228 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1229 //rlca does not set these flags
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1230 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1231 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1232 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1233 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1234 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1235 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1236 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1237 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1238 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1239 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1240 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1241 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1242 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1243 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1244 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1245 z80_save_reg(inst, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1246 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1247 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1248 case Z80_RL:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1249 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1250 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1251 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1252 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1253 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1254 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1255 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1256 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1257 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1258 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1259 translate_z80_reg(inst, &dst_op, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1260 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1261 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1262 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1263 rcl_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1264 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1265 rcl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1266 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1267 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1268 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1269 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1270 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1271 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1272 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1273 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1274 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1275 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1276 //rla does not set these flags
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1277 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1278 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1279 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1280 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1281 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1282 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1283 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1284 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1285 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1286 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1287 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1288 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1289 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1290 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1291 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1292 z80_save_reg(inst, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1293 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1294 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1295 case Z80_RRC:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1296 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1297 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1298 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1299 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1300 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1301 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1302 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1303 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1304 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1305 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1306 translate_z80_reg(inst, &dst_op, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1307 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1308 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1309 ror_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1310 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1311 ror_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1312 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1313 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1314 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1315 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1316 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1317 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1318 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1319 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1320 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1321 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1322 //rrca does not set these flags
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1323 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1324 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1325 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1326 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1327 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1328 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1329 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1330 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1331 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1332 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1333 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1334 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1335 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1336 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1337 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1338 z80_save_reg(inst, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1339 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1340 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1341 case Z80_RR:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1342 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1343 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1344 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1345 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1346 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1347 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1348 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1349 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1350 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1351 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1352 translate_z80_reg(inst, &dst_op, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1353 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1354 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1355 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1356 rcr_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1357 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1358 rcr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1359 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1360 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1361 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1362 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1363 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1364 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1365 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1366 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1367 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1368 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1369 //rra does not set these flags
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1370 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1371 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1372 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1373 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1374 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1375 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1376 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1377 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1378 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1379 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1380 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1381 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1382 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1383 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1384 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1385 z80_save_reg(inst, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1386 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1387 break;
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1388 case Z80_SLA:
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1389 case Z80_SLL:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1390 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1391 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1392 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1393 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1394 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1395 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1396 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1397 cycles(&opts->gen, 1);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1398 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1399 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1400 translate_z80_reg(inst, &dst_op, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1401 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1402 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1403 shl_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1404 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1405 shl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1406 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1407 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
310
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents: 309
diff changeset
1408 if (inst->op == Z80_SLL) {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1409 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1410 or_ir(code, 1, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1411 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1412 or_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1413 }
310
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents: 309
diff changeset
1414 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1415 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1416 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1417 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1418 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1419 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1420 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1421 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1422 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1423 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1424 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1425 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1426 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1427 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1428 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1429 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1430 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1431 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1432 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1433 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1434 }
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1435 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1436 z80_save_reg(inst, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1437 }
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1438 break;
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1439 case Z80_SRA:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1440 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1441 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1442 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1443 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1444 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1445 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1446 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1447 cycles(&opts->gen, 1);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1448 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1449 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1450 translate_z80_reg(inst, &dst_op, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1451 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1452 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1453 sar_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1454 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1455 sar_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1456 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1457 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1458 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1459 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1460 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1461 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1462 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1463 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1464 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1465 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1466 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1467 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1468 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1469 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1470 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1471 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1472 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1473 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1474 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1475 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1476 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1477 }
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1478 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1479 z80_save_reg(inst, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1480 }
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1481 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1482 case Z80_SRL:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1483 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1484 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1485 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1486 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1487 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1488 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1489 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1490 cycles(&opts->gen, 1);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1491 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1492 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1493 translate_z80_reg(inst, &dst_op, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1494 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1495 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1496 shr_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1497 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1498 shr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1499 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1500 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1501 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1502 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1503 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1504 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1505 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1506 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1507 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1508 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1509 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1510 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1511 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1512 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1513 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1514 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1515 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1516 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1517 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1518 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1519 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1520 }
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1521 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1522 z80_save_reg(inst, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1523 }
310
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents: 309
diff changeset
1524 break;
286
872a8911e0f4 Implemente RLD
Mike Pavone <pavone@retrodev.com>
parents: 285
diff changeset
1525 case Z80_RLD:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1526 cycles(&opts->gen, num_cycles);
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1527 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1528 call(code, opts->read_8);
286
872a8911e0f4 Implemente RLD
Mike Pavone <pavone@retrodev.com>
parents: 285
diff changeset
1529 //Before: (HL) = 0x12, A = 0x34
872a8911e0f4 Implemente RLD
Mike Pavone <pavone@retrodev.com>
parents: 285
diff changeset
1530 //After: (HL) = 0x24, A = 0x31
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1531 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1532 shl_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1533 and_ir(code, 0xF, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1534 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1535 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1536 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
1537 //opts->gen.scratch1 = 0x0124
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1538 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1539 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1540 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1541 //set flags
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1542 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1543 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1544 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1545 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1546 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1547
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1548 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1549 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1550 call(code, opts->write_8);
286
872a8911e0f4 Implemente RLD
Mike Pavone <pavone@retrodev.com>
parents: 285
diff changeset
1551 break;
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1552 case Z80_RRD:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1553 cycles(&opts->gen, num_cycles);
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1554 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1555 call(code, opts->read_8);
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1556 //Before: (HL) = 0x12, A = 0x34
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1557 //After: (HL) = 0x41, A = 0x32
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1558 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1559 ror_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1560 shl_ir(code, 4, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1561 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1562 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
967
1eb616b8cbe9 Fix bug in Z80 rrd implementation. This fixes the annoying high pitched wine in Afterburner II.
Michael Pavone <pavone@retrodev.com>
parents: 966
diff changeset
1563 and_ir(code, 0xF0, opts->gen.scratch2, SZ_W);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
1564 //opts->gen.scratch1 = 0x2001
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
1565 //opts->gen.scratch2 = 0x0040
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1566 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
1567 //opts->gen.scratch1 = 0x2041
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1568 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1569 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1570 shr_ir(code, 4, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1571 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1572 //set flags
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1573 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1574 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1575 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1576 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1577 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1578
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1579 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1580 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1581 call(code, opts->write_8);
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1582 break;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1583 case Z80_BIT: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1584 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1585 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1586 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1587 cycles(&opts->gen, num_cycles);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1588 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1589 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1590 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737
043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents: 735
diff changeset
1591 src_op.mode = MODE_REG_DIRECT;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1592 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1593 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1594 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1595 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1596 bit = inst->immed;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1597 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1598 }
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1599 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1600 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1601 cycles(&opts->gen, 1);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1602 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1603 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1604 bt_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1605 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1606 bt_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1607 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1608 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1609 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1610 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1611 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
307
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents: 306
diff changeset
1612 if (inst->immed == 7) {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1613 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1614 cmp_ir(code, 0, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1615 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1616 cmp_irdisp(code, 0, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1617 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1618 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
307
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents: 306
diff changeset
1619 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1620 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
307
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents: 306
diff changeset
1621 }
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1622 break;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1623 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1624 case Z80_SET: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1625 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1626 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1627 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1628 cycles(&opts->gen, num_cycles);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1629 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1630 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1631 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737
043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents: 735
diff changeset
1632 src_op.mode = MODE_REG_DIRECT;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1633 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1634 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1635 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1636 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1637 bit = inst->immed;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1638 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1639 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1640 if (inst->reg != Z80_USE_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1641 translate_z80_reg(inst, &dst_op, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1642 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1643 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1644 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1645 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1646 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1647 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1648 bts_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1649 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1650 bts_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1651 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1652 if (inst->reg != Z80_USE_IMMED) {
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1653 if (size == SZ_W) {
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1654 #ifdef X86_64
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1655 if (dst_op.base >= R8) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1656 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1657 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1658 ror_ir(code, 8, src_op.base, SZ_W);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1659 } else {
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1660 #endif
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1661 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1662 zreg_to_native(opts, inst->ea_reg, dst_op.base);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1663 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1664 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1665 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1666 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1667 #ifdef X86_64
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1668 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1669 #endif
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1670 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1671 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1672 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1673 mov_rr(code, src_op.base, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1674 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1675 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1676 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1677 } else if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1678 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1679 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1680 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1681 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1682 }
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1683 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1684 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1685 if ((inst->addr_mode & 0x1F) != Z80_REG) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1686 z80_save_result(opts, inst);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1687 if (inst->reg != Z80_USE_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1688 z80_save_reg(inst, opts);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1689 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1690 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1691 break;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1692 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1693 case Z80_RES: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1694 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1695 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1696 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1697 cycles(&opts->gen, num_cycles);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1698 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1699 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1700 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737
043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents: 735
diff changeset
1701 src_op.mode = MODE_REG_DIRECT;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1702 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1703 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1704 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1705 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1706 bit = inst->immed;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1707 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1708 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1709 if (inst->reg != Z80_USE_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1710 translate_z80_reg(inst, &dst_op, opts);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1711 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1712 if (inst->addr_mode != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1713 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1714 cycles(&opts->gen, 1);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1715 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1716 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1717 btr_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1718 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1719 btr_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1720 }
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1721 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1722 if (size == SZ_W) {
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1723 #ifdef X86_64
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1724 if (dst_op.base >= R8) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1725 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1726 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1727 ror_ir(code, 8, src_op.base, SZ_W);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1728 } else {
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1729 #endif
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1730 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1731 zreg_to_native(opts, inst->ea_reg, dst_op.base);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1732 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1733 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1734 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1735 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1736 #ifdef X86_64
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1737 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1738 #endif
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1739 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1740 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1741 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1742 mov_rr(code, src_op.base, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1743 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1744 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1745 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1746 } else if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1747 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1748 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1749 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1750 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1751 }
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1752 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1753 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1754 if (inst->addr_mode != Z80_REG) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1755 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1756 if (inst->reg != Z80_USE_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1757 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1758 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1759 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1760 break;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1761 }
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1762 case Z80_JP: {
506
a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
1763 if (inst->addr_mode != Z80_REG_INDIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1764 num_cycles += 6;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1765 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1766 cycles(&opts->gen, num_cycles);
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1767 if (inst->addr_mode != Z80_REG_INDIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1768 code_ptr call_dst = z80_get_native_address(context, inst->immed);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1769 if (!call_dst) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1770 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1771 //fake address to force large displacement
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
1772 call_dst = code->cur + 256;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1773 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1774 jmp(code, call_dst);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1775 } else {
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1776 if (inst->addr_mode == Z80_REG_INDIRECT) {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
1777 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1778 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1779 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1780 }
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1781 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1782 jmp_r(code, opts->gen.scratch1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1783 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1784 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1785 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1786 case Z80_JPCC: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1787 cycles(&opts->gen, num_cycles + 3);//T States: 4,3
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1788 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1789 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1790 {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1791 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1792 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1793 case Z80_CC_Z:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1794 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1795 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1796 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1797 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1798 case Z80_CC_C:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1799 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1800 break;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1801 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1802 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1803 case Z80_CC_PE:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1804 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1805 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1806 case Z80_CC_P:
367
f20562f2a570 Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 366
diff changeset
1807 cond = CC_NZ;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1808 case Z80_CC_M:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1809 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1810 break;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1811 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1812 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1813 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1814 cycles(&opts->gen, 5);//T States: 5
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1815 uint16_t dest_addr = inst->immed;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1816 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1817 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1818 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1819 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1820 call_dst = code->cur + 256;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1821 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1822 jmp(code, call_dst);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1823 *no_jump_off = code->cur - (no_jump_off+1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1824 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1825 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1826 case Z80_JR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1827 cycles(&opts->gen, num_cycles + 8);//T States: 4,3,5
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1828 uint16_t dest_addr = address + inst->immed + 2;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1829 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1830 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1831 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1832 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1833 call_dst = code->cur + 256;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1834 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1835 jmp(code, call_dst);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1836 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1837 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1838 case Z80_JRCC: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1839 cycles(&opts->gen, num_cycles + 3);//T States: 4,3
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1840 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1841 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1842 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1843 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1844 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1845 case Z80_CC_Z:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1846 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1847 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1848 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1849 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1850 case Z80_CC_C:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1851 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1852 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1853 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1854 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1855 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1856 cycles(&opts->gen, 5);//T States: 5
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1857 uint16_t dest_addr = address + inst->immed + 2;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1858 code_ptr call_dst = z80_get_native_address(context, dest_addr);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1859 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1860 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1861 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1862 call_dst = code->cur + 256;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1863 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1864 jmp(code, call_dst);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1865 *no_jump_off = code->cur - (no_jump_off+1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1866 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1867 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1868 case Z80_DJNZ: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1869 cycles(&opts->gen, num_cycles + 4);//T States: 5,3
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1870 if (opts->regs[Z80_B] >= 0) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1871 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1872 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1873 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1874 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1875 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1876 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1877 cycles(&opts->gen, 5);//T States: 5
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1878 uint16_t dest_addr = address + inst->immed + 2;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1879 code_ptr call_dst = z80_get_native_address(context, dest_addr);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1880 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1881 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1882 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1883 call_dst = code->cur + 256;
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1884 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1885 jmp(code, call_dst);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1886 *no_jump_off = code->cur - (no_jump_off+1);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1887 break;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1888 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1889 case Z80_CALL: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1890 cycles(&opts->gen, num_cycles + 7);//T States: 4,3,4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1891 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1892 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1893 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1894 call(code, opts->write_16_highfirst);//T States: 3, 3
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1895 code_ptr call_dst = z80_get_native_address(context, inst->immed);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1896 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1897 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1898 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1899 call_dst = code->cur + 256;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1900 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1901 jmp(code, call_dst);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1902 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1903 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1904 case Z80_CALLCC: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1905 cycles(&opts->gen, num_cycles + 6);//T States: 4,3,3 (false case)
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1906 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1907 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1908 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1909 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1910 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1911 case Z80_CC_Z:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1912 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1913 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1914 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1915 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1916 case Z80_CC_C:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1917 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1918 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1919 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1920 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1921 case Z80_CC_PE:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1922 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1923 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1924 case Z80_CC_P:
367
f20562f2a570 Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 366
diff changeset
1925 cond = CC_NZ;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1926 case Z80_CC_M:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1927 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1928 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1929 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1930 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1931 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1932 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1933 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1934 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1935 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1936 call(code, opts->write_16_highfirst);//T States: 3, 3
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1937 code_ptr call_dst = z80_get_native_address(context, inst->immed);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1938 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1939 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1940 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1941 call_dst = code->cur + 256;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1942 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
1943 jmp(code, call_dst);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1944 *no_call_off = code->cur - (no_call_off+1);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
1945 break;
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
1946 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1947 case Z80_RET:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1948 cycles(&opts->gen, num_cycles);//T States: 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1949 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1950 call(code, opts->read_16);//T STates: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1951 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1952 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1953 jmp_r(code, opts->gen.scratch1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1954 break;
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1955 case Z80_RETCC: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1956 cycles(&opts->gen, num_cycles + 1);//T States: 5
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1957 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1958 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1959 {
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1960 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1961 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1962 case Z80_CC_Z:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1963 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1964 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1965 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1966 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1967 case Z80_CC_C:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1968 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1969 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1970 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1971 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1972 case Z80_CC_PE:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1973 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1974 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1975 case Z80_CC_P:
367
f20562f2a570 Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 366
diff changeset
1976 cond = CC_NZ;
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1977 case Z80_CC_M:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1978 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1979 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1980 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1981 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1982 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1983 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1984 call(code, opts->read_16);//T STates: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1985 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1986 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1987 jmp_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1988 *no_call_off = code->cur - (no_call_off+1);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1989 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
1990 }
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
1991 case Z80_RETI:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
1992 //For some systems, this may need a callback for signalling interrupt routine completion
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1993 cycles(&opts->gen, num_cycles);//T States: 4, 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1994 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1995 call(code, opts->read_16);//T STates: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1996 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1997 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1998 jmp_r(code, opts->gen.scratch1);
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
1999 break;
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2000 case Z80_RETN:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2001 cycles(&opts->gen, num_cycles);//T States: 4, 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2002 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2003 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2004 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2005 call(code, opts->read_16);//T STates: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2006 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2007 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2008 jmp_r(code, opts->gen.scratch1);
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2009 break;
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2010 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2011 //RST is basically CALL to an address in page 0
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2012 cycles(&opts->gen, num_cycles + 1);//T States: 5
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2013 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2014 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2015 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2016 call(code, opts->write_16_highfirst);//T States: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2017 code_ptr call_dst = z80_get_native_address(context, inst->immed);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2018 if (!call_dst) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2019 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2020 //fake address to force large displacement
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
2021 call_dst = code->cur + 256;
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2022 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2023 jmp(code, call_dst);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2024 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2025 }
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2026 case Z80_IN:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2027 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2028 num_cycles += 3;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2029 }
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2030 cycles(&opts->gen, num_cycles);//T States: 4 3/4
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2031 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2032 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2033 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2034 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2035 }
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2036 call(code, opts->read_io);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2037 if (inst->addr_mode != Z80_IMMED_INDIRECT) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2038 or_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2039 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2040 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2041 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2042 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2043 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2044 }
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2045 if (inst->reg != Z80_UNUSED) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2046 translate_z80_reg(inst, &dst_op, opts);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2047 if (dst_op.mode == MODE_REG_DIRECT) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2048 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2049 } else {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2050 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2051 }
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2052 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2053 z80_save_reg(inst, opts);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2054 break;
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2055 /*case Z80_INI:
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2056 case Z80_INIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2057 case Z80_IND:
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2058 case Z80_INDR:*/
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2059 case Z80_OUT:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2060 if (inst->reg == Z80_A) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2061 num_cycles += 3;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2062 }
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2063 cycles(&opts->gen, num_cycles);//T States: 4 3/4
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2064 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2065 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2066 } else {
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2067 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2068 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2069 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2070 translate_z80_reg(inst, &src_op, opts);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2071 if (src_op.mode == MODE_REG_DIRECT) {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2072 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2073 } else if (src_op.mode == MODE_IMMED) {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2074 mov_ir(code, src_op.disp, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2075 } else {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2076 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2077 }
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2078 call(code, opts->write_io);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2079 z80_save_reg(inst, opts);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2080 break;
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2081 case Z80_OUTI:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2082 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2083 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2084 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2085 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2086 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2087 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2088 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2089 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2090 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2091 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2092 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2093 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2094 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2095 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2096 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2097 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2098 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2099 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2100 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2101 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2102 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2103 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2104 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2105 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2106 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2107 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2108 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2109 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2110 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2111 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2112 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2113 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2114 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2115 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2116 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2117 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2118 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2119 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2120 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2121 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2122 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2123 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2124 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2125 case Z80_OTIR: {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2126 code_ptr start = code->cur;
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2127 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2128 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2129 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2130 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2131 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2132 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2133 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2134 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2135 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2136 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2137 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2138 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2139 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2140 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2141 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2142 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2143 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2144 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2145 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2146 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2147 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2148 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2149 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2150 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2151 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2152 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2153 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2154 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2155 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2156 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2157 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2158 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2159 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2160 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2161 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2162 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2163 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2164 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2165 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2166 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2167 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2168 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2169 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2170 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2171 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2172 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2173 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2174 code_ptr done = code->cur+1;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2175 jcc(code, CC_Z, code->cur+2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2176 cycles(&opts->gen, 5);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2177 jmp(code, start);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2178 *done = code->cur - (done + 1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2179 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2180 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2181 case Z80_OUTD:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2182 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2183 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2184 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2185 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2186 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2187 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2188 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2189 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2190 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2191 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2192 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2193 //decrement HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2194 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2195 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2196 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2197 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2198 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2199 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2200 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2201 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2202 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2203 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2204 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2205 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2206 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2207 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2208 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2209 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2210 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2211 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2212 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2213 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2214 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2215 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2216 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2217 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2218 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2219 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2220 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2221 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2222 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2223 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2224 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2225 case Z80_OTDR: {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2226 code_ptr start = code->cur;
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2227 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2228 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2229 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2230 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2231 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2232 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2233 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2234 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2235 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2236 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2237 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2238 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2239 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2240 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2241 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2242 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2243 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2244 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2245 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2246 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2247 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2248 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2249 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2250 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2251 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2252 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2253 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2254 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2255 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2256 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2257 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2258 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2259 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2260 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2261 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2262 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2263 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2264 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2265 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2266 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2267 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2268 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2269 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2270 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2271 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2272 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2273 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2274 code_ptr done = code->cur+1;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2275 jcc(code, CC_Z, code->cur+2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2276 cycles(&opts->gen, 5);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2277 jmp(code, start);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2278 *done = code->cur - (done + 1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2279 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2280 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2281 default: {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2282 char disbuf[80];
314
54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents: 313
diff changeset
2283 z80_disasm(inst, disbuf, address);
259
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
2284 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
2285 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
2286 fclose(f);
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
2287 fatal_error("unimplemented Z80 instruction: %s at %X\nZ80 RAM has been saved to zram.bin for debugging", disbuf, address);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2288 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2289 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2290 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2291
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2292 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context)
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2293 {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2294 if (!context->interp_code[opcode]) {
755
7306b3967c51 Cleanup some warnings under clang through a combination of code fixes and supressing specific warnings
Michael Pavone <pavone@retrodev.com>
parents: 737
diff changeset
2295 if (opcode == 0xCB || (opcode >= 0xDD && (opcode & 0xF) == 0xD)) {
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
2296 fatal_error("Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2297 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2298 uint8_t codebuf[8];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2299 memset(codebuf, 0, sizeof(codebuf));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2300 codebuf[0] = opcode;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2301 z80inst inst;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2302 uint8_t * after = z80_decode(codebuf, &inst);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2303 if (after - codebuf > 1) {
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
2304 fatal_error("Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2305 }
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2306
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2307 z80_options * opts = context->options;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2308 code_info *code = &opts->gen.code;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2309 check_alloc_code(code, ZMAX_NATIVE_SIZE);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2310 context->interp_code[opcode] = code->cur;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2311 translate_z80inst(&inst, context, 0, 1);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2312 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2313 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2314 call(code, opts->native_addr);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2315 jmp_r(code, opts->gen.scratch1);
715
1c2020d3e275 Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly
Michael Pavone <pavone@retrodev.com>
parents: 712
diff changeset
2316 z80_handle_deferred(context);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2317 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2318 return context->interp_code[opcode];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2319 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2320
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2321 code_info z80_make_interp_stub(z80_context * context, uint16_t address)
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2322 {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2323 z80_options *opts = context->options;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2324 code_info * code = &opts->gen.code;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2325 check_alloc_code(code, 32);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2326 code_info stub = {code->cur, NULL};
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2327 //TODO: make this play well with the breakpoint code
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2328 mov_ir(code, address, opts->gen.scratch1, SZ_W);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2329 call(code, opts->read_8);
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2330 //opcode fetch M-cycles have one extra T-state
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2331 cycles(&opts->gen, 1);
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2332 //TODO: increment R
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2333 check_cycles_int(&opts->gen, address);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2334 call(code, opts->gen.save_context);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2335 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2336 push_r(code, opts->gen.context_reg);
712
382a2b5b70c0 Fix crash bug in Z80 interpreter
Michael Pavone <pavone@retrodev.com>
parents: 702
diff changeset
2337 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.context_reg);
664
bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents: 663
diff changeset
2338 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2339 pop_r(code, opts->gen.context_reg);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2340 call(code, opts->gen.load_context);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2341 jmp_r(code, opts->gen.scratch1);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2342 stub.last = code->cur;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2343 return stub;
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2344 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2345
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2346
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2347 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2348 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2349 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2350 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2351 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2352 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2353 } else {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2354 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2355 map = context->banked_code_map;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2356 }
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
2357 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) {
313
a13329645ea3 Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents: 312
diff changeset
2358 //dprintf("z80_get_native_address: %X NULL\n", address);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2359 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2360 }
313
a13329645ea3 Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents: 312
diff changeset
2361 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2362 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2363 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2364
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2365 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2366 {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2367 //TODO: Fix for addresses >= 0x4000
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2368 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2369 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2370 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2371 return opts->gen.ram_inst_sizes[0][address & 0x1FFF];
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2372 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2373
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2374 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2375 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2376 uint32_t orig_address = address;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2377 native_map_slot *map;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2378 z80_options * opts = context->options;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2379 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2380 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2381 map = context->static_code_map;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2382 opts->gen.ram_inst_sizes[0][address] = native_size;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2383 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2384 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2385 } else {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2386 //HERE
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2387 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2388 map = context->banked_code_map;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2389 if (!map->offsets) {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2390 map->offsets = malloc(sizeof(int32_t) * 0xC000);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2391 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2392 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2393 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2394 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2395 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2396 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2397 map->offsets[address] = native_address - map->base;
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
2398 for(--size, orig_address++; size; --size, orig_address++) {
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2399 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2400 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2401 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2402 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2403 } else {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2404 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2405 map = context->banked_code_map;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2406 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2407 if (!map->offsets) {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2408 map->offsets = malloc(sizeof(int32_t) * 0xC000);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2409 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2410 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2411 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2412 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2413 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2414
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2415 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2416
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2417 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2418 {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2419 //TODO: Fixme for address >= 0x4000
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2420 if (!static_code_map->base || address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2421 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2422 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2423 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2424 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2425 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2426 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2427 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2428 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2429 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2430 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2431 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2432 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2433
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2434 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2435 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2436 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2437 if (inst_start != INVALID_INSTRUCTION_START) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2438 code_ptr dst = z80_get_native_address(context, inst_start);
899
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2439 code_info code = {dst, dst+32, 0};
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2440 z80_options * opts = context->options;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2441 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code.cur, inst_start, address);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2442 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2443 call(&code, opts->retrans_stub);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2444 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2445 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2446 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2447
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2448 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2449 {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2450 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2451 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2452 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2453 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2454 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2455 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2456 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2457 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2458 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2459 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2460
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2461 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2462 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2463 z80_options * opts = context->options;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2464 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2465 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2466 translate_z80_stream(context, opts->gen.deferred->address);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2467 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2468 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2469
559
6b248602ab84 blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2470 extern void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) asm("z80_retranslate_inst");
390
561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents: 389
diff changeset
2471 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start)
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2472 {
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2473 char disbuf[80];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2474 z80_options * opts = context->options;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2475 uint8_t orig_size = z80_get_native_inst_size(opts, address);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2476 code_info *code = &opts->gen.code;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2477 uint8_t *after, *inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2478 z80inst instbuf;
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
2479 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2480 after = z80_decode(inst, &instbuf);
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
2481 #ifdef DO_DEBUG_PRINT
314
54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents: 313
diff changeset
2482 z80_disasm(&instbuf, disbuf, address);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2483 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2484 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2485 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2486 printf("%X\t%s\n", address, disbuf);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
2487 }
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
2488 #endif
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2489 if (orig_size != ZMAX_NATIVE_SIZE) {
597
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents: 594
diff changeset
2490 check_alloc_code(code, ZMAX_NATIVE_SIZE);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2491 code_ptr start = code->cur;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2492 deferred_addr * orig_deferred = opts->gen.deferred;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2493 translate_z80inst(&instbuf, context, address, 0);
644
2d7e84ae818c Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one
Michael Pavone <pavone@retrodev.com>
parents: 628
diff changeset
2494 /*
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2495 if ((native_end - dst) <= orig_size) {
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2496 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2497 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2498 remove_deferred_until(&opts->gen.deferred, orig_deferred);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2499 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2500 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2501 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2502 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2503 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2504 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2505 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2506 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2507 z80_handle_deferred(context);
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2508 return orig_start;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2509 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2510 }*/
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2511 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2512 code_info tmp_code = {orig_start, orig_start + 16};
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2513 jmp(&tmp_code, start);
597
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents: 594
diff changeset
2514 tmp_code = *code;
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents: 594
diff changeset
2515 code->cur = start + ZMAX_NATIVE_SIZE;
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2516 if (!z80_is_terminal(&instbuf)) {
597
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents: 594
diff changeset
2517 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst));
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
2518 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2519 z80_handle_deferred(context);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2520 return start;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2521 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2522 code_info tmp_code = *code;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2523 code->cur = orig_start;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2524 code->last = orig_start + ZMAX_NATIVE_SIZE;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2525 translate_z80inst(&instbuf, context, address, 0);
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
2526 code_info tmp2 = *code;
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
2527 *code = tmp_code;
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2528 if (!z80_is_terminal(&instbuf)) {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2529
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
2530 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst));
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2531 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
2532 z80_handle_deferred(context);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2533 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2534 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2535 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2536
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2537 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2538 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2539 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2540 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2541 return;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2542 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2543 z80_options * opts = context->options;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2544 uint32_t start_address = address;
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2545
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2546 do
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2547 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2548 z80inst inst;
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
2549 dprintf("translating Z80 code at address %X\n", address);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2550 do {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2551 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2552 if (existing) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2553 jmp(&opts->gen.code, existing);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2554 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2555 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2556 uint8_t * encoded, *next;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2557 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2558 if (!encoded) {
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2559 code_info stub = z80_make_interp_stub(context, address);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2560 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2561 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2562 }
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
2563 //make sure prologue is in a contiguous chunk of code
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
2564 check_code_prologue(&opts->gen.code);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2565 next = z80_decode(encoded, &inst);
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
2566 #ifdef DO_DEBUG_PRINT
314
54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents: 313
diff changeset
2567 z80_disasm(&inst, disbuf, address);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2568 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2569 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2570 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2571 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2572 }
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
2573 #endif
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2574 code_ptr start = opts->gen.code.cur;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2575 translate_z80inst(&inst, context, address, 0);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2576 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2577 address += next-encoded;
255
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
2578 address &= 0xFFFF;
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2579 } while (!z80_is_terminal(&inst));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2580 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2581 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2582 address = opts->gen.deferred->address;
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
2583 dprintf("defferred address: %X\n", address);
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
2584 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2585 } while (opts->gen.deferred);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2586 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2587
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
2588 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2589 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2590 memset(options, 0, sizeof(*options));
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2591
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2592 options->gen.memmap = chunks;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2593 options->gen.memmap_chunks = num_chunks;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2594 options->gen.address_size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2595 options->gen.address_mask = 0xFFFF;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2596 options->gen.max_address = 0x10000;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2597 options->gen.bus_cycles = 3;
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
2598 options->gen.clock_divider = clock_divider;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2599 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2600 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags);
620
9d6fed6501ba Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.
Michael Pavone <pavone@retrodev.com>
parents: 601
diff changeset
2601 options->gen.ram_flags_shift = 7;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2602
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2603 options->flags = 0;
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2604 #ifdef X86_64
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2605 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2606 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2607 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2608 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2609 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2610 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2611 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2612 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2613 options->regs[Z80_IYH] = -1;
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
2614 options->regs[Z80_IYL] = R8;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2615 options->regs[Z80_I] = -1;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2616 options->regs[Z80_R] = -1;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2617 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2618 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2619 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2620 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2621 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2622 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2623 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2624 options->regs[Z80_IY] = R8;
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
2625
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2626 options->gen.scratch1 = R13;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2627 options->gen.scratch2 = R14;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2628 #else
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2629 memset(options->regs, -1, sizeof(options->regs));
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2630 options->regs[Z80_A] = RAX;
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
2631 options->regs[Z80_SP] = RBX;
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
2632
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2633 options->gen.scratch1 = RCX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2634 options->gen.scratch2 = RDX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2635 #endif
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
2636
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2637 options->gen.context_reg = RSI;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2638 options->gen.cycles = RBP;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2639 options->gen.limit = RDI;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2640
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2641 options->gen.native_code_map = malloc(sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2642 memset(options->gen.native_code_map, 0, sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2643 options->gen.deferred = NULL;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2644 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2645 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2646 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2647
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2648 code_info *code = &options->gen.code;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2649 init_code_info(code);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2650
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2651 options->save_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2652 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2653 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2654
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2655 options->gen.save_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2656 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2657 {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2658 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2659 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2660 if (i < Z80_I) {
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2661 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2662 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2663 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2664 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2665 size = SZ_B;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2666 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2667 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2668 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, offsetof(z80_context, regs) + i, size);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2669 }
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2670 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2671 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2672 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2673 }
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2674 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2675 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2676 }
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2677 mov_rrdisp(code, options->gen.limit, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2678 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2679 retn(code);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2680
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2681 options->load_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2682 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2683 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2684 options->gen.load_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2685 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2686 {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2687 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2688 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2689 if (i < Z80_I) {
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2690 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2691 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2692 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2693 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2694 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2695 }
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2696 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2697 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2698 }
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2699 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2700 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2701 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2702 }
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2703 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2704 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2705 }
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2706 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2707 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2708 retn(code);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2709
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2710 options->native_addr = code->cur;
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2711 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2712 push_r(code, options->gen.context_reg);
657
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
2713 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D);
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
2714 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2715 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2716 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2717 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2718 retn(code);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2719
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2720 uint32_t tmp_stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2721
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2722 options->gen.handle_cycle_limit = code->cur;
900
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2723 //calculate call/stack adjust size
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2724 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2725 call_noalign(code, options->gen.handle_cycle_limit);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2726 uint32_t call_adjust_size = code->cur - options->gen.handle_cycle_limit;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2727 code->cur = options->gen.handle_cycle_limit;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2728
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2729 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2730 code_ptr no_sync = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2731 jcc(code, CC_B, no_sync);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2732 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2733 call(code, options->save_context_scratch);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2734 tmp_stack_off = code->stack_off;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2735 pop_r(code, RAX); //return address in read/write func
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2736 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2737 pop_r(code, RBX); //return address in translated code
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2738 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
900
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2739 sub_ir(code, call_adjust_size, RAX, SZ_PTR); //adjust return address to point to the call + stack adjust that got us here
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2740 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2741 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
665
d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents: 664
diff changeset
2742 restore_callee_save_regs(code);
598
faad1927d836 Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80
Michael Pavone <pavone@retrodev.com>
parents: 597
diff changeset
2743 *no_sync = code->cur - (no_sync + 1);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2744 //return to caller of z80_run
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2745 retn(code);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2746 code->stack_off = tmp_stack_off;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2747
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2748 options->gen.handle_code_write = (code_ptr)z80_handle_code_write;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2749
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2750 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2751 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2752
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2753 code_ptr skip_int = code->cur;
900
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2754 //calculate adjust size
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2755 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2756 uint32_t adjust_size = code->cur - skip_int;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2757 code->cur = skip_int;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2758
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2759 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2760 code_ptr skip_sync = code->cur + 1;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2761 jcc(code, CC_B, skip_sync);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2762 //save PC
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2763 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, pc), SZ_D);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2764 options->do_sync = code->cur;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2765 call(code, options->gen.save_context);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2766 tmp_stack_off = code->stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2767 //pop return address off the stack and save for resume later
898
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
2768 //pop_rind(code, options->gen.context_reg);
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
2769 pop_r(code, RAX);
900
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
2770 add_ir(code, adjust_size, RAX, SZ_PTR);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2771 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
898
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
2772 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
2773
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2774 //restore callee saved registers
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2775 restore_callee_save_regs(code);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2776 //return to caller of z80_run
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2777 *skip_sync = code->cur - (skip_sync+1);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2778 retn(code);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2779 code->stack_off = tmp_stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2780
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2781 options->gen.handle_cycle_limit_int = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2782 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2783 jcc(code, CC_B, skip_int);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2784 //set limit to the cycle limit
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2785 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2786 //disable interrupts
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2787 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2788 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2789 cycles(&options->gen, 7);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2790 //save return address (in scratch1) to Z80 stack
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2791 sub_ir(code, 2, options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2792 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2793 //we need to do check_cycles and cycles outside of the write_8 call
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2794 //so that the stack has the correct depth if we need to return to C
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2795 //for a synchronization
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2796 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2797 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2798 //save word to write before call to write_8_noinc
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2799 push_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2800 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2801 //restore word to write
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2802 pop_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2803 //write high byte to SP+1
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2804 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2805 add_ir(code, 1, options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2806 shr_ir(code, 8, options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2807 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2808 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2809 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2810 //dispose of return address as we'll be jumping somewhere else
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2811 add_ir(code, 16, RSP, SZ_PTR);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2812 //TODO: Support interrupt mode 0 and 2
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2813 mov_ir(code, 0x38, options->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2814 call(code, options->native_addr);
663
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents: 662
diff changeset
2815 mov_rrind(code, options->gen.scratch1, options->gen.context_reg, SZ_PTR);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2816 tmp_stack_off = code->stack_off;
665
d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents: 664
diff changeset
2817 restore_callee_save_regs(code);
663
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents: 662
diff changeset
2818 //return to caller of z80_run to sync
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents: 662
diff changeset
2819 retn(code);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2820 code->stack_off = tmp_stack_off;
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2821
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
2822 //HACK
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
2823 options->gen.address_size = SZ_D;
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
2824 options->gen.address_mask = 0xFF;
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
2825 options->read_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, READ_8, NULL);
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
2826 options->write_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, WRITE_8, NULL);
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
2827 options->gen.address_size = SZ_W;
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
2828 options->gen.address_mask = 0xFFFF;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2829
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2830 options->read_16 = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2831 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2832 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2833 //TODO: figure out how to handle the extra wait state for word reads to bank area
657
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
2834 //may also need special handling to avoid too much stack depth when access is blocked
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2835 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2836 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2837 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2838 #ifndef X86_64
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2839 //scratch 2 is a caller save register in 32-bit builds and may be clobbered by something called from the read8 fun
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2840 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2841 #endif
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2842 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2843 add_ir(code, 1, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2844 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2845 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2846 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2847 shl_ir(code, 8, options->gen.scratch1, SZ_W);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2848 #ifdef X86_64
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2849 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2850 #else
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2851 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2852 #endif
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2853 retn(code);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2854
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2855 options->write_16_highfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2856 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2857 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2858 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2859 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2860 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2861 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2862 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2863 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2864 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2865 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2866 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2867 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2868 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2869 retn(code);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2870
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2871 options->write_16_lowfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2872 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2873 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2874 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2875 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2876 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2877 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2878 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2879 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2880 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2881 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2882 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2883 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2884 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2885 retn(code);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2886
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2887 options->retrans_stub = code->cur;
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2888 tmp_stack_off = code->stack_off;
899
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2889 //calculate size of patch
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2890 mov_ir(code, 0x7FFF, options->gen.scratch1, SZ_D);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2891 code->stack_off += sizeof(void *);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2892 if (code->stack_off & 0xF) {
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2893 sub_ir(code, 16 - (code->stack_off & 0xF), RSP, SZ_PTR);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2894 }
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2895 call_noalign(code, options->retrans_stub);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2896 uint32_t patch_size = code->cur - options->retrans_stub;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2897 code->cur = options->retrans_stub;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2898 code->stack_off = tmp_stack_off;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2899
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2900 //pop return address
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2901 pop_r(code, options->gen.scratch2);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2902 add_ir(code, 16-sizeof(void*), RSP, SZ_PTR);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2903 code->stack_off = tmp_stack_off;
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2904 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2905 //adjust pointer before move and call instructions that got us here
899
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
2906 sub_ir(code, patch_size, options->gen.scratch2, SZ_PTR);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2907 push_r(code, options->gen.context_reg);
657
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
2908 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2909 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2910 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2911 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2912 jmp_r(code, options->gen.scratch1);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2913
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2914 options->run = (z80_run_fun)code->cur;
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2915 tmp_stack_off = code->stack_off;
665
d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents: 664
diff changeset
2916 save_callee_save_regs(code);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
2917 #ifdef X86_64
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2918 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
2919 #else
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
2920 mov_rdispr(code, RSP, 5 * sizeof(int32_t), options->gen.context_reg, SZ_PTR);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
2921 #endif
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
2922 call(code, options->load_context_scratch);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2923 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2924 code_ptr no_extra = code->cur+1;
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2925 jcc(code, CC_Z, no_extra);
898
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
2926 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2927 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc));
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2928 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2929 *no_extra = code->cur - (no_extra + 1);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2930 jmp_rind(code, options->gen.context_reg);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
2931 code->stack_off = tmp_stack_off;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2932 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2933
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2934 void init_z80_context(z80_context * context, z80_options * options)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2935 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2936 memset(context, 0, sizeof(*context));
360
c42fae88d346 Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error
Mike Pavone <pavone@retrodev.com>
parents: 335
diff changeset
2937 context->static_code_map = malloc(sizeof(*context->static_code_map));
259
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
2938 context->static_code_map->base = NULL;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2939 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2940 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2941 context->banked_code_map = malloc(sizeof(native_map_slot));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2942 memset(context->banked_code_map, 0, sizeof(native_map_slot));
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2943 context->options = options;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2944 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2945 context->int_pulse_start = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2946 context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2947 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2948
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2949 void z80_run(z80_context * context, uint32_t target_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2950 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2951 if (context->reset || context->busack) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2952 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2953 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2954 if (context->current_cycle < target_cycle) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2955 //busreq is sampled at the end of an m-cycle
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2956 //we can approximate that by running for a single m-cycle after a bus request
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2957 context->sync_cycle = context->busreq ? context->current_cycle + 3*context->options->gen.clock_divider : target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2958 if (!context->native_pc) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2959 context->native_pc = z80_get_native_address_trans(context, context->pc);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2960 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2961 while (context->current_cycle < context->sync_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2962 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2963 if (context->int_pulse_end < context->current_cycle || context->int_pulse_end == CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2964 z80_next_int_pulse(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2965 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2966 if (context->iff1) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2967 context->int_cycle = context->int_pulse_start < context->int_enable_cycle ? context->int_enable_cycle : context->int_pulse_start;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2968 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2969 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2970 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2971 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
670
f4f3e74b0ce6 Restore Z80 interrupt pulse duration and make a small improvement to debug print output
Michael Pavone <pavone@retrodev.com>
parents: 668
diff changeset
2972 dprintf("Running Z80 from cycle %d to cycle %d. Int cycle: %d (%d - %d)\n", context->current_cycle, context->sync_cycle, context->int_cycle, context->int_pulse_start, context->int_pulse_end);
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2973 context->options->run(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2974 dprintf("Z80 ran to cycle %d\n", context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2975 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2976 if (context->busreq) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2977 context->busack = 1;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2978 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2979 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2980 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2981 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2982 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2983
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
2984 void z80_options_free(z80_options *opts)
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
2985 {
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
2986 free(opts->gen.native_code_map);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
2987 free(opts->gen.ram_inst_sizes);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
2988 free(opts);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
2989 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
2990
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2991 void z80_assert_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2992 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2993 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2994 context->reset = 1;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2995 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2996
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2997 void z80_clear_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2998 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
2999 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3000 if (context->reset) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3001 //TODO: Handle case where reset is not asserted long enough
701
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents: 697
diff changeset
3002 context->im = 0;
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents: 697
diff changeset
3003 context->iff1 = context->iff2 = 0;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3004 context->native_pc = NULL;
701
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents: 697
diff changeset
3005 context->extra_pc = NULL;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3006 context->pc = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3007 context->reset = 0;
676
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents: 670
diff changeset
3008 if (context->busreq) {
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents: 670
diff changeset
3009 //TODO: Figure out appropriate delay
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents: 670
diff changeset
3010 context->busack = 1;
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents: 670
diff changeset
3011 }
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3012 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3013 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3014
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3015 void z80_assert_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3016 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3017 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3018 context->busreq = 1;
854
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3019 //this is an imperfect aproximation since most M-cycles take less tstates than the max
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3020 //and a short 3-tstate m-cycle can take an unbounded number due to wait states
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3021 if (context->current_cycle - cycle > MAX_MCYCLE_LENGTH * context->options->gen.clock_divider) {
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3022 context->busack = 1;
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3023 }
701
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents: 697
diff changeset
3024 }
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3025
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3026 void z80_clear_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3027 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3028 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3029 context->busreq = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3030 context->busack = 0;
844
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 842
diff changeset
3031 //there appears to be at least a 1 Z80 cycle delay between busreq
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 842
diff changeset
3032 //being released and resumption of execution
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 842
diff changeset
3033 context->current_cycle += context->options->gen.clock_divider;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3034 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3035
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3036 uint8_t z80_get_busack(z80_context * context, uint32_t cycle)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3037 {
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3038 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3039 return context->busack;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3040 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3041
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3042 void z80_adjust_cycles(z80_context * context, uint32_t deduction)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3043 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3044 if (context->current_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3045 fprintf(stderr, "WARNING: Deduction of %u cycles when Z80 cycle counter is only %u\n", deduction, context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3046 context->current_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3047 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3048 context->current_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3049 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3050 if (context->int_enable_cycle != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3051 if (context->int_enable_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3052 context->int_enable_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3053 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3054 context->int_enable_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3055 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3056 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3057 if (context->int_pulse_start != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3058 if (context->int_pulse_end < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3059 context->int_pulse_start = context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3060 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3061 context->int_pulse_end -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3062 if (context->int_pulse_start < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3063 context->int_pulse_start = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3064 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3065 context->int_pulse_start -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3066 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3067 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3068 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3069 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3070
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3071 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3072 {
966
f765c2fc7508 Fix crash bug in Z80 debugger introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 900
diff changeset
3073 code_info code = {dst, dst+32};
659
759c38bf97f8 Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents: 657
diff changeset
3074 mov_ir(&code, address, context->options->gen.scratch1, SZ_W);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3075 call(&code, context->bp_stub);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3076 return code.cur-dst;
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3077 }
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3078
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3079 void zcreate_stub(z80_context * context)
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3080 {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3081 z80_options * opts = context->options;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3082 code_info *code = &opts->gen.code;
894
a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
3083 uint32_t start_stack_off = code->stack_off;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3084 check_code_prologue(code);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3085 context->bp_stub = code->cur;
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3086
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
3087 //Calculate length of prologue
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3088 check_cycles_int(&opts->gen, 0);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3089 int check_int_size = code->cur-context->bp_stub;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3090 code->cur = context->bp_stub;
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3091
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3092 //Calculate length of patch
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3093 int patch_size = zbreakpoint_patch(context, 0, code->cur);
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3094
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
3095 //Save context and call breakpoint handler
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3096 call(code, opts->gen.save_context);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3097 push_r(code, opts->gen.scratch1);
657
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
3098 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1);
664
bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents: 663
diff changeset
3099 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR);
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
3100 //Restore context
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3101 call(code, opts->gen.load_context);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3102 pop_r(code, opts->gen.scratch1);
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
3103 //do prologue stuff
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3104 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3105 uint8_t * jmp_off = code->cur+1;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3106 jcc(code, CC_NC, code->cur + 7);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3107 pop_r(code, opts->gen.scratch1);
664
bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents: 663
diff changeset
3108 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3109 push_r(code, opts->gen.scratch1);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3110 jmp(code, opts->gen.handle_cycle_limit_int);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3111 *jmp_off = code->cur - (jmp_off+1);
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
3112 //jump back to body of translated instruction
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3113 pop_r(code, opts->gen.scratch1);
664
bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents: 663
diff changeset
3114 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3115 jmp_r(code, opts->gen.scratch1);
894
a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
3116 code->stack_off = start_stack_off;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3117 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3118
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3119 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler)
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3120 {
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3121 context->bp_handler = bp_handler;
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3122 uint8_t bit = 1 << (address % 8);
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3123 if (!(bit & context->breakpoint_flags[address / 8])) {
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3124 context->breakpoint_flags[address / 8] |= bit;
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3125 if (!context->bp_stub) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3126 zcreate_stub(context);
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3127 }
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3128 uint8_t * native = z80_get_native_address(context, address);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3129 if (native) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3130 zbreakpoint_patch(context, address, native);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3131 }
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3132 }
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3133 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3134
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3135 void zremove_breakpoint(z80_context * context, uint16_t address)
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3136 {
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3137 context->breakpoint_flags[address / 8] &= ~(1 << (address % 8));
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3138 uint8_t * native = z80_get_native_address(context, address);
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3139 if (native) {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3140 z80_options * opts = context->options;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3141 code_info tmp_code = opts->gen.code;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3142 opts->gen.code.cur = native;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3143 opts->gen.code.last = native + 16;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3144 check_cycles_int(&opts->gen, address);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3145 opts->gen.code = tmp_code;
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
3146 }
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3147 }
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3148