annotate z80_to_x86.c @ 1856:be1da0a68d1e

Added "sharp" shader
author Michael Pavone <pavone@retrodev.com>
date Sat, 27 Apr 2019 17:37:12 -0700
parents 37afb9cf58be
children 62166274e6c0
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1 /*
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2 Copyright 2013 Michael Pavone
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b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include "z80inst.h"
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7 #include "z80_to_x86.h"
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8 #include "gen_x86.h"
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9 #include "mem.h"
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10 #include "util.h"
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11 #include <stdio.h>
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12 #include <stdlib.h>
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13 #include <stddef.h>
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14 #include <string.h>
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15
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16 #define MODE_UNUSED (MODE_IMMED-1)
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17 #define MAX_MCYCLE_LENGTH 6
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18 #define NATIVE_CHUNK_SIZE 1024
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19 #define NATIVE_MAP_CHUNKS (0x10000 / NATIVE_CHUNK_SIZE)
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20
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21 //#define DO_DEBUG_PRINT
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22
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23 #ifdef DO_DEBUG_PRINT
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24 #define dprintf printf
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25 #else
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26 #define dprintf
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27 #endif
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28
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29 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst);
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30 void z80_handle_deferred(z80_context * context);
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31
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32 uint8_t z80_size(z80inst * inst)
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33 {
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34 uint8_t reg = (inst->reg & 0x1F);
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35 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
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36 return reg < Z80_BC ? SZ_B : SZ_W;
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37 }
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38 //TODO: Handle any necessary special cases
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39 return SZ_B;
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40 }
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41
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42 uint8_t zf_off(uint8_t flag)
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43 {
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44 return offsetof(z80_context, flags) + flag;
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45 }
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46
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47 uint8_t zaf_off(uint8_t flag)
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48 {
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49 return offsetof(z80_context, alt_flags) + flag;
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50 }
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51
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52 uint8_t zr_off(uint8_t reg)
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53 {
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54 if (reg > Z80_A) {
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55 reg = z80_low_reg(reg);
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56 }
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57 return offsetof(z80_context, regs) + reg;
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58 }
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59
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60 uint8_t zar_off(uint8_t reg)
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61 {
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62 if (reg > Z80_A) {
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63 reg = z80_low_reg(reg);
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64 }
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65 return offsetof(z80_context, alt_regs) + reg;
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66 }
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67
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68 void zreg_to_native(z80_options *opts, uint8_t reg, uint8_t native_reg)
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69 {
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70 if (opts->regs[reg] >= 0) {
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71 mov_rr(&opts->gen.code, opts->regs[reg], native_reg, reg > Z80_A ? SZ_W : SZ_B);
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72 } else {
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73 mov_rdispr(&opts->gen.code, opts->gen.context_reg, zr_off(reg), native_reg, reg > Z80_A ? SZ_W : SZ_B);
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74 }
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75 }
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76
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77 void native_to_zreg(z80_options *opts, uint8_t native_reg, uint8_t reg)
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78 {
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79 if (opts->regs[reg] >= 0) {
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80 mov_rr(&opts->gen.code, native_reg, opts->regs[reg], reg > Z80_A ? SZ_W : SZ_B);
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81 } else {
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82 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, zr_off(reg), reg > Z80_A ? SZ_W : SZ_B);
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83 }
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84 }
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85
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86 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts)
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87 {
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88 code_info *code = &opts->gen.code;
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89 if (inst->reg == Z80_USE_IMMED) {
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90 ea->mode = MODE_IMMED;
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91 ea->disp = inst->immed;
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92 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
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93 ea->mode = MODE_UNUSED;
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94 } else {
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95 ea->mode = MODE_REG_DIRECT;
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96 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
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97 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
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98 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
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99 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
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100 ea->base = opts->gen.scratch1;
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101 } else {
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102 ea->base = opts->regs[Z80_IYL];
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103 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
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104 }
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105 } else if(opts->regs[inst->reg] >= 0) {
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106 ea->base = opts->regs[inst->reg];
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107 if (ea->base >= AH && ea->base <= BH) {
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108 if ((inst->addr_mode & 0x1F) == Z80_REG) {
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109 uint8_t other_reg = opts->regs[inst->ea_reg];
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110 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
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111 //we can't mix an *H reg with a register that requires the REX prefix
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112 ea->base = opts->regs[z80_low_reg(inst->reg)];
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113 ror_ir(code, 8, ea->base, SZ_W);
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114 }
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115 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
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116 //temp regs require REX prefix too
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
117 ea->base = opts->regs[z80_low_reg(inst->reg)];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
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parents: 506
diff changeset
118 ror_ir(code, 8, ea->base, SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
119 }
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
120 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
121 } else {
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
122 ea->mode = MODE_REG_DISPLACE8;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
123 ea->base = opts->gen.context_reg;
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
124 ea->disp = zr_off(inst->reg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
125 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
126 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
127 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
128
590
ea80559c67cb WIP effort to update z80 core for code gen changes
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parents: 506
diff changeset
129 void z80_save_reg(z80inst * inst, z80_options * opts)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
130 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
131 code_info *code = &opts->gen.code;
716
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
132 if (inst->reg == Z80_USE_IMMED || inst->reg == Z80_UNUSED) {
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
133 return;
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
134 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
135 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
136 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
137 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
138 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
139 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
140 } else {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
141 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
142 }
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
143 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
144 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
145 uint8_t other_reg = opts->regs[inst->ea_reg];
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
146 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
147 //we can't mix an *H reg with a register that requires the REX prefix
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
148 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
149 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
150 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
151 //temp regs require REX prefix too
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
152 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
153 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
154 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
155 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
156
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
157 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
158 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
159 code_info *code = &opts->gen.code;
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
160 uint8_t size, areg;
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
161 int8_t reg;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
162 ea->mode = MODE_REG_DIRECT;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
163 areg = read ? opts->gen.scratch1 : opts->gen.scratch2;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
164 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
165 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
166 case Z80_REG:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
167 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
168 if (inst->reg == Z80_IYL) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
169 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
170 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
171 ea->base = opts->gen.scratch1;
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
172 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
173 ea->base = opts->regs[Z80_IYL];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
174 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
175 }
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
176 } else if(opts->regs[inst->ea_reg] >= 0) {
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 ea->base = opts->regs[inst->ea_reg];
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
178 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
179 uint8_t other_reg = opts->regs[inst->reg];
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
180 #ifdef X86_64
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
181 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
182 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
183 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
184 ror_ir(code, 8, ea->base, SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
185 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
186 #endif
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
187 }
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
188 } else {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
189 ea->mode = MODE_REG_DISPLACE8;
659
759c38bf97f8 Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents: 657
diff changeset
190 ea->base = opts->gen.context_reg;
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
191 ea->disp = zr_off(inst->ea_reg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
193 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 case Z80_REG_INDIRECT:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
195 zreg_to_native(opts, inst->ea_reg, areg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
197 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
198 if (modify) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
199 //push_r(code, opts->gen.scratch1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
200 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
201 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 if (size == SZ_B) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
203 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
205 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
206 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
208 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 case Z80_IMMED_INDIRECT:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
215 mov_ir(code, inst->immed, areg, SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 if (read) {
277
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller
Mike Pavone <pavone@retrodev.com>
parents: 275
diff changeset
218 /*if (modify) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
219 push_r(code, opts->gen.scratch1);
277
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller
Mike Pavone <pavone@retrodev.com>
parents: 275
diff changeset
220 }*/
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 if (size == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
222 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 } else {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
224 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
225 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
227 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 break;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
229 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
230 case Z80_IY_DISPLACE:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
231 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, areg);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
232 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
234 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 if (modify) {
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
236 //push_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
237 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 if (size == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
240 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 } else {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
242 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
243 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
245 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
246 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
247 case Z80_UNUSED:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
248 ea->mode = MODE_UNUSED;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
249 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250 default:
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
251 fatal_error("Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
252 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
253 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
254
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
255 void z80_save_ea(code_info *code, z80inst * inst, z80_options * opts)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
256 {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
257 if ((inst->addr_mode & 0x1F) == Z80_REG) {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
258 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
259 if (inst->reg == Z80_IYL) {
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
260 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
261 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
262 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
263 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
264 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
265 }
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
266 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
267 uint8_t other_reg = opts->regs[inst->reg];
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
268 #ifdef X86_64
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
269 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
270 //we can't mix an *H reg with a register that requires the REX prefix
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
271 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
272 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
273 #endif
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
274 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
275 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
276 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
277
593
5ef3fe516da9 Z80 core is sort of working again
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parents: 592
diff changeset
278 void z80_save_result(z80_options *opts, z80inst * inst)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
279 {
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
280 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
281 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
282 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
283 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
284 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
285 case Z80_IY_DISPLACE:
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
286 if (inst->op != Z80_LD) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
287 mov_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
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parents: 1044
diff changeset
288 }
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
289 if (z80_size(inst) == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
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parents: 592
diff changeset
290 call(&opts->gen.code, opts->write_8);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
291 } else {
593
5ef3fe516da9 Z80 core is sort of working again
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parents: 592
diff changeset
292 call(&opts->gen.code, opts->write_16_lowfirst);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
293 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
294 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
295 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
296
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
297 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
298 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
299 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
300 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
301
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
303 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
305 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
306
235
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
307 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
308 {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
309 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
310 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
311 context->regs[Z80_D], context->regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
312 (context->regs[Z80_H] << 8) | context->regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
313 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
314 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL],
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
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parents: 242
diff changeset
315 context->sp, context->im, context->iff1, context->iff2);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
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parents: 239
diff changeset
316 puts("--Alternate Regs--");
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
317 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
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parents: 239
diff changeset
318 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
319 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
320 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
321 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL],
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
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parents: 239
diff changeset
322 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]);
235
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parents: 213
diff changeset
323 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
324 }
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parents: 213
diff changeset
325
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
326 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp)
213
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parents:
diff changeset
327 {
591
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parents: 590
diff changeset
328 uint32_t num_cycles;
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parents: 590
diff changeset
329 host_ea src_op, dst_op;
235
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
330 uint8_t size;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
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parents: 506
diff changeset
331 z80_options *opts = context->options;
591
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parents: 590
diff changeset
332 uint8_t * start = opts->gen.code.cur;
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parents: 590
diff changeset
333 code_info *code = &opts->gen.code;
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
334 if (!interp) {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
335 check_cycles_int(&opts->gen, address);
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
336 if (context->breakpoint_flags[address / 8] & (1 << (address % 8))) {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
337 zbreakpoint_patch(context, address, start);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
338 }
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
339 num_cycles = 4 * inst->opcode_bytes;
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
340 add_ir(code, inst->opcode_bytes > 1 ? 2 : 1, opts->regs[Z80_R], SZ_B);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
341 #ifdef Z80_LOG_ADDRESS
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
342 log_address(&opts->gen, address, "Z80: %X @ %d\n");
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
343 #endif
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
344 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
346 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
347 case Z80_LD:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
348 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
349 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
350 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
351 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
352 case Z80_REG_INDIRECT:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
353 if (size != SZ_B) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
354 num_cycles += 2;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
355 }
841
58606d16d35c Fix timing of certain variants of LD
Michael Pavone <pavone@retrodev.com>
parents: 840
diff changeset
356 if (inst->reg == Z80_I || inst->ea_reg == Z80_I || inst->reg == Z80_R || inst->ea_reg == Z80_R) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
357 num_cycles += 1;
1767
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
358 } else if (inst->reg == Z80_USE_IMMED) {
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
359 num_cycles += 3;
506
a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
360 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
361 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
362 case Z80_IMMED:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
363 num_cycles += size == SZ_B ? 3 : 6;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
364 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
365 case Z80_IMMED_INDIRECT:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
366 num_cycles += 6;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
367 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
368 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
369 case Z80_IY_DISPLACE:
1110
d1eed3b1121c Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1062
diff changeset
370 num_cycles += 8; //3 for displacement, 5 for address addition
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
371 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
372 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
373 cycles(&opts->gen, num_cycles);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
374 if (inst->addr_mode & Z80_DIR) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
375 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
376 translate_z80_reg(inst, &src_op, opts);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
377 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
378 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
379 translate_z80_reg(inst, &dst_op, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380 }
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
381 if (inst->reg == Z80_R) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
382 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
383 mov_rr(code, opts->regs[Z80_A], opts->regs[Z80_R], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
384 and_ir(code, 0x80, opts->gen.scratch1, SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
385 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zr_off(Z80_R), SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
386 } else if (inst->ea_reg == Z80_R && inst->addr_mode == Z80_REG) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
387 mov_rr(code, opts->regs[Z80_R], opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
388 and_ir(code, 0x7F, opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
389 or_rdispr(code, opts->gen.context_reg, zr_off(Z80_R), opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
390 } else if (src_op.mode == MODE_REG_DIRECT) {
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
391 if(dst_op.mode == MODE_REG_DISPLACE8) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
392 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
393 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
394 mov_rr(code, src_op.base, dst_op.base, size);
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
395 }
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
396 } else if(src_op.mode == MODE_IMMED) {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
397 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
398 mov_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
399 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
400 mov_ir(code, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
401 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
402 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
403 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
404 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
405 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
406 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
407 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
408 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409 }
842
ba93a3941300 Set flags for ld a, r
Michael Pavone <pavone@retrodev.com>
parents: 841
diff changeset
410 if ((inst->ea_reg == Z80_I || inst->ea_reg == Z80_R) && inst->addr_mode == Z80_REG) {
ba93a3941300 Set flags for ld a, r
Michael Pavone <pavone@retrodev.com>
parents: 841
diff changeset
411 //ld a, i and ld a, r sets some flags
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
412 cmp_ir(code, 0, dst_op.base, SZ_B);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
413 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
414 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
821
21a69dfb6ee7 Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents: 819
diff changeset
415 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
416 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);;
659
759c38bf97f8 Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents: 657
diff changeset
417 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
418 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
419 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
420 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
421 z80_save_ea(code, inst, opts);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
422 if (inst->addr_mode & Z80_DIR) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
423 z80_save_result(opts, inst);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
424 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
425 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
426 case Z80_PUSH:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
427 cycles(&opts->gen, num_cycles + 1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
428 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
429 if (inst->reg == Z80_AF) {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
430 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
431 shl_ir(code, 8, opts->gen.scratch1, SZ_W);
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
432 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
433 and_ir(code, 0x28, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
434 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
435 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
436 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
437 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
438 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
439 ror_ir(code, 2, opts->gen.scratch1, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
440 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B);
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
441 ror_ir(code, 2, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
442 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
443 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
444 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
445 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
446 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
447 zreg_to_native(opts, inst->reg, opts->gen.scratch1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
448 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
449 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
450 call(code, opts->write_16_highfirst);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
451 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
452 //the upper half of a register pair
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
453 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
454 case Z80_POP:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
455 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
456 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
457 call(code, opts->read_16);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
458 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
459 if (inst->reg == Z80_AF) {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
460
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
461 bt_ir(code, 0, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
462 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
463 bt_ir(code, 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
464 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
465 bt_ir(code, 2, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
466 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
467 bt_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
468 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
469 bt_ir(code, 6, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
470 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
471 bt_ir(code, 7, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
472 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
473 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
474 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
475 native_to_zreg(opts, opts->gen.scratch1, Z80_A);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
476 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
477 native_to_zreg(opts, opts->gen.scratch1, inst->reg);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
478 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
479 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
480 //the upper half of a register pair
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
481 break;
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
482 case Z80_EX:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
483 cycles(&opts->gen, num_cycles);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
484 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
485 if(inst->reg == Z80_AF) {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
486 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
487 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->gen.scratch2, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
488 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
489 native_to_zreg(opts, opts->gen.scratch2, Z80_A);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
490
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
491 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
492 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
493 for (int f = ZF_C; f < ZF_NUM; f+=2) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
494 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
495 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
496 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
497 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
498 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
499 } else {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
500 if (opts->regs[Z80_DE] >= 0 && opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
501 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
502 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
503 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
504 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
505 native_to_zreg(opts, opts->gen.scratch1, Z80_HL);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
506 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
507 }
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
508 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
509 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
510 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
511 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
512 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
513 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
514 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
515 zreg_to_native(opts, inst->reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
516 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
517 native_to_zreg(opts, opts->gen.scratch2, inst->reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
518 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
519 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
520 call(code, opts->write_8);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
521 cycles(&opts->gen, 1);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
522 uint8_t high_reg = z80_high_reg(inst->reg);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
523 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
524 add_ir(code, 1, opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
525 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
526 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
527 //even though some of the upper halves can be used directly
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
528 //the limitations on mixing *H regs with the REX prefix
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
529 //prevent us from taking advantage of it
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
530 uint8_t use_reg = opts->regs[inst->reg];
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
531 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
532 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
533 //restore reg to normal rotation
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
534 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
535 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
536 zreg_to_native(opts, high_reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
537 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
538 native_to_zreg(opts, opts->gen.scratch2, high_reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
539 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
540 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
541 add_ir(code, 1, opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
542 call(code, opts->write_8);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
543 cycles(&opts->gen, 2);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
544 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
545 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 case Z80_EXX:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
547 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
548 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
549 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
550 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
551 native_to_zreg(opts, opts->gen.scratch2, Z80_BC);
840
5822c6e5642f Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents: 828
diff changeset
552
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
553 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
554 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
555 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
556 native_to_zreg(opts, opts->gen.scratch2, Z80_HL);
840
5822c6e5642f Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents: 828
diff changeset
557
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
558 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
559 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
560 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
561 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
562 break;
272
9b04b57434b5 Implement LDI
Mike Pavone <pavone@retrodev.com>
parents: 269
diff changeset
563 case Z80_LDI: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
564 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
565 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
566 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
567 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
568 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
569 call(code, opts->write_8);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
570 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
571 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
572 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
573 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
574 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
575 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
576 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
577 cycles(&opts->gen, 2);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
578 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
579 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
580 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
581 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
582 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
583 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
584 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
585 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
586 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
587 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
588 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
589 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
590 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
591 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
592 }
821
21a69dfb6ee7 Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents: 819
diff changeset
593 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
594 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
595 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
272
9b04b57434b5 Implement LDI
Mike Pavone <pavone@retrodev.com>
parents: 269
diff changeset
596 break;
9b04b57434b5 Implement LDI
Mike Pavone <pavone@retrodev.com>
parents: 269
diff changeset
597 }
261
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
598 case Z80_LDIR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
599 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
600 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
601 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
602 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
603 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
604 call(code, opts->write_8);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
605 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
606 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
607 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
608 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
609 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
610 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
611 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
612 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
613 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
614 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
615 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
616 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
617 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
618 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
619 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
620 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
621 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
622 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
623 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
624 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
625 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
626 }
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
627 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
628 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
629 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
630 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
631 cycles(&opts->gen, 7);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
632 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
633 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
634 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
635 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
636 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
261
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
637 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents: 259
diff changeset
638 }
273
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
639 case Z80_LDD: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
640 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
641 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
642 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
643 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
644 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
645 call(code, opts->write_8);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
646 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
647 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
648 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
649 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
650 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
651 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
652 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
653 cycles(&opts->gen, 2);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
654 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
655 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
656 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
657 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
658 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
659 if (opts->regs[Z80_HL] >= 0) {
828
22c3c52b9871 Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions.
Michael Pavone <pavone@retrodev.com>
parents: 821
diff changeset
660 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
661 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
662 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
663 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
664 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
665 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
666 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
667 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
668 }
821
21a69dfb6ee7 Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents: 819
diff changeset
669 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
670 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
671 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
273
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
672 break;
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
673 }
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
674 case Z80_LDDR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
675 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
676 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
677 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
678 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
679 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
680 call(code, opts->write_8);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
681 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
682 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
683 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
684 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
685 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
686 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
687 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
688 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
689 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
690 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
691 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
692 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
693 if (opts->regs[Z80_HL] >= 0) {
828
22c3c52b9871 Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions.
Michael Pavone <pavone@retrodev.com>
parents: 821
diff changeset
694 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
695 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
696 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
697 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
698 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
699 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
700 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
701 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
702 }
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
703 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
704 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
705 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
706 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
707 cycles(&opts->gen, 7);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
708 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
709 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
710 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
711 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
712 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
273
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
713 break;
719b9fea2fe9 Implement LDD and LDDR
Mike Pavone <pavone@retrodev.com>
parents: 272
diff changeset
714 }
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
715 case Z80_CPI:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
716 cycles(&opts->gen, num_cycles);//T-States 4,4
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
717 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
718 call(code, opts->read_8);//T-States 3
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
719 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
720 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
721 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
722 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
723 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
724 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
725 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
726 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
727 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
728 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
729 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
730 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
731 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
732 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
733 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
734 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
735 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
736 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
737 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
738 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
739 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
1051
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
740 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
741 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
742 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
743 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
744 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
745 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
746 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
747 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
748 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
749 case Z80_CPIR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
750 cycles(&opts->gen, num_cycles);//T-States 4,4
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
751 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
752 call(code, opts->read_8);//T-States 3
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
753 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
754 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
755 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
756 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
757 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
758 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
759 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
760 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
761 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
762 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
763 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
764 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
765 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
766 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
767 }
1051
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
768 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
769 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
770 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
771 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
772 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
773 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
774 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
775 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
776 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
777 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
778 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
779 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
780 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
781 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
782 uint8_t * cont = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
783 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
784 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
785 uint8_t * cont2 = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
786 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
787 //repeat case
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
788 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
789 jmp(code, start);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
790 *cont = code->cur - (cont + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
791 *cont2 = code->cur - (cont2 + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
792 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
793 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
794 case Z80_CPD:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
795 cycles(&opts->gen, num_cycles);//T-States 4,4
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
796 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
797 call(code, opts->read_8);//T-States 3
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
798 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
799 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
800 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
801 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
802 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
803 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
804 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
805 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
806 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
807 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
808 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
809 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
810 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
811 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
812 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
813 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
814 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
815 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
816 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
817 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
818 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
1051
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
819 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
820 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
821 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
822 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
823 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
824 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
825 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
826 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
827 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
828 case Z80_CPDR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
829 cycles(&opts->gen, num_cycles);//T-States 4,4
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
830 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
831 call(code, opts->read_8);//T-States 3
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
832 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
833 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
834 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
835 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
836 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
837 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
838 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
839 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
840 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
841 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
842 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
843 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
844 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
845 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
846 }
1051
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
847 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
848 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
849 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
850 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
851 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
852 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
853 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents: 1050
diff changeset
854 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1043
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
855 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
856 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
857 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
858 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
859 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
860 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
861 uint8_t * cont = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
862 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
863 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
864 uint8_t * cont2 = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
865 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
866 //repeat case
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
867 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
868 jmp(code, start);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
869 *cont = code->cur - (cont + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
870 *cont2 = code->cur - (cont2 + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
871 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents: 1042
diff changeset
872 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
873 case Z80_ADD:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
874 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
875 num_cycles += 8;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
876 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
877 num_cycles += 3;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
878 } else if(z80_size(inst) == SZ_W) {
1761
873a1330c3a9 Fix cycle counts of a few instructions in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1592
diff changeset
879 num_cycles += 7;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
880 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
881 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
882 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
883 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
884 if (dst_op.mode == MODE_REG_DIRECT) {
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
885 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
886 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
887 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
888 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
889 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
890 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
891 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
892 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
893 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
894 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
895 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
896 if (dst_op.mode == MODE_REG_DIRECT) {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
897 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
898 add_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
899 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
900 add_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
901 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
902 add_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
903 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
904 if (z80_size(inst) == SZ_B) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
905 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
906 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
907 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
908 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
909 add_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
910 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
911 add_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
912 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
913 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
914 add_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
915 }
1057
ff46d8fc2de8 Fix handling of undocumented flag bits for ADD in 32-bit builds
Michael Pavone <pavone@retrodev.com>
parents: 1056
diff changeset
916 mov_rdispr(code, dst_op.base, dst_op.disp + (z80_size(inst) == SZ_B ? 0 : 1), opts->gen.scratch1, SZ_B);
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
917 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
918 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
919 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
920 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
921 if (z80_size(inst) == SZ_B) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
922 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
923 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
924 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
925 }
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
926 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
927 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
928 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
929 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
930 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
931 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
932 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
933 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
934 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
935 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
936 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
937 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
938 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
939 z80_save_ea(code, inst, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
940 break;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
941 case Z80_ADC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
942 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
943 num_cycles += 8;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
944 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
945 num_cycles += 3;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
946 } else if(z80_size(inst) == SZ_W) {
1767
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
947 num_cycles += 7;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
948 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
949 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
950 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
951 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
952 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
953 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
954 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
955 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
956 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
957 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
958 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
959 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
960 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
961 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
962 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
963 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
964 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
965 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
966 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
967 adc_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
968 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
969 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
970 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
971 adc_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
972 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
973 if (z80_size(inst) == SZ_B) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
974 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
975 }
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
976 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
977 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
978 adc_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
979 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
980 adc_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
981 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
982 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
983 adc_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
984 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
985 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
986 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
987 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
988 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
989 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
990 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
991 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
992 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
993 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
994 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
995 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
996 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
997 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
998 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
999 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1000 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1001 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1002 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1003 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1004 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1005 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1006 z80_save_ea(code, inst, opts);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1007 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1008 case Z80_SUB:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
1009 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1010 num_cycles += 8;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1011 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1012 num_cycles += 3;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1013 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1014 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1015 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1016 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1017 if (dst_op.mode == MODE_REG_DIRECT) {
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1018 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1019 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1020 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1021 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1022 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1023 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1024 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1025 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1026 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1027 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1028 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1029 if (dst_op.mode == MODE_REG_DIRECT) {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1030 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1031 sub_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1032 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1033 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1034 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1035 sub_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1036 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1037 if (z80_size(inst) == SZ_B) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1038 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1039 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1040 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1041 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1042 sub_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1043 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1044 sub_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1045 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1046 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1047 sub_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1048 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1049 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1050 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1051 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1052 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1053 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1054 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1055 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1056 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1057 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1058 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1059 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1060 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1061 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1062 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1063 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1064 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1065 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1066 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1067 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1068 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1069 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1070 z80_save_ea(code, inst, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1071 break;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1072 case Z80_SBC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1073 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1074 num_cycles += 8;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1075 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1076 num_cycles += 3;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1077 } else if(z80_size(inst) == SZ_W) {
1767
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
1078 num_cycles += 7;
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1079 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1080 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1081 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1082 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1083 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1084 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1085 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1086 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1087 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1088 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1089 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1090 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1091 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1092 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1093 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1094 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1095 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1096 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1097 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1098 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1099 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1100 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1101 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1102 sbb_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1103 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1104 if (z80_size(inst) == SZ_B) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1105 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1106 }
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1107 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1108 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1109 sbb_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1110 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1111 sbb_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1112 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1113 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1114 sbb_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1115 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1116 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1117 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1118 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1119 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1120 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1121 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1122 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1123 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1124 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1125 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1126 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1127 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1128 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1129 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1130 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1131 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1132 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1133 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1134 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1135 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1136 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1137 z80_save_ea(code, inst, opts);
248
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents: 247
diff changeset
1138 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1139 case Z80_AND:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1140 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1141 num_cycles += 8;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1142 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1143 num_cycles += 3;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1144 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1145 num_cycles += 4;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1146 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1147 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1148 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1149 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1150 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1151 and_rr(code, src_op.base, dst_op.base, z80_size(inst));
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1152 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1153 and_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1154 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1155 and_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1156 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1157 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1158 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1159 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1160 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1161 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1162 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1163 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1164 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1165 z80_save_ea(code, inst, opts);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1166 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1167 case Z80_OR:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1168 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1169 num_cycles += 8;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1170 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1171 num_cycles += 3;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1172 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1173 num_cycles += 4;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1174 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1175 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1176 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1177 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1178 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1179 or_rr(code, src_op.base, dst_op.base, z80_size(inst));
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1180 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1181 or_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1182 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1183 or_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1184 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1185 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1186 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1187 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1188 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1189 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1190 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1191 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1192 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1193 z80_save_ea(code, inst, opts);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1194 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1195 case Z80_XOR:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1196 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1197 num_cycles += 8;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1198 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1199 num_cycles += 3;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1200 } else if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1201 num_cycles += 4;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1202 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1203 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1204 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1205 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1206 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1207 xor_rr(code, src_op.base, dst_op.base, z80_size(inst));
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1208 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1209 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1210 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1211 xor_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1212 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1213 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1214 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1215 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1216 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1217 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1218 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1219 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1220 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1221 z80_save_ea(code, inst, opts);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1222 break;
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1223 case Z80_CP:
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1224 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1225 num_cycles += 8;
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1226 } else if(inst->addr_mode == Z80_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1227 num_cycles += 3;
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1228 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1229 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1230 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1231 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1232 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1233 if (src_op.mode == MODE_REG_DIRECT) {
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1234 sub_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1235 mov_rrdisp(code, src_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1236 } else if (src_op.mode == MODE_IMMED) {
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1237 sub_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1238 mov_irdisp(code, src_op.disp, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1239 } else {
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1240 sub_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1241 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1242 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1243 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1244 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1245 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1246 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1247 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1248 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1249 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1250 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1251 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1252 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1253 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1254 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1255 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1256 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1257 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1258 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1259 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1260 z80_save_ea(code, inst, opts);
242
d3b84b2a4397 Implemente CP (untested)
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
1261 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1262 case Z80_INC:
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1263 case Z80_DEC:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1264 if(z80_size(inst) == SZ_W) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1265 num_cycles += 2;
1767
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
1266 } else if (inst->addr_mode == Z80_REG_INDIRECT) {
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
1267 num_cycles += 1;
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
1268 } else if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
1269 num_cycles += 9;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1270 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1271 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1272 translate_z80_reg(inst, &dst_op, opts);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1273 if (dst_op.mode == MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1274 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1275 }
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1276 if (z80_size(inst) == SZ_B) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1277 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1278 if (dst_op.base >= AH && dst_op.base <= BH) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1279 mov_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1280 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1281 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1282 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1283 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1284 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1285 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1286 }
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1287 if (inst->op == Z80_INC) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1288 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1289 add_ir(code, 1, dst_op.base, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1290 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1291 add_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1292 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1293 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1294 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1295 sub_ir(code, 1, dst_op.base, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1296 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1297 sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1298 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1299 }
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1300 if (z80_size(inst) == SZ_B) {
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1301 mov_irdisp(code, inst->op == Z80_DEC, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1302 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1303 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1304 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1305 int bit = 4;
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1306 if (dst_op.mode == MODE_REG_DIRECT) {
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1307 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1308 if (dst_op.base >= AH && dst_op.base <= BH) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1309 bit = 12;
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1310 xor_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1311 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1312 xor_rr(code, dst_op.base, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1313 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1314 } else {
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1315 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1316 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B);
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1317 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1318 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1319 bt_ir(code, bit, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1320 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
1321 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1322 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1323 z80_save_ea(code, inst, opts);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1324 z80_save_result(opts, inst);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1325 break;
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1326 case Z80_DAA: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1327 cycles(&opts->gen, num_cycles);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1328 xor_rr(code, opts->gen.scratch2, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1329 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1330 and_ir(code, 0xF, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1331 cmp_ir(code, 0xA, opts->gen.scratch1, SZ_B);
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1332 mov_ir(code, 0xA0, opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1333 code_ptr corf_low_range = code->cur + 1;
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1334 jcc(code, CC_NC, code->cur+2);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1335 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1336 code_ptr corf_low = code->cur + 1;
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1337 jcc(code, CC_NZ, code->cur+2);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1338 code_ptr no_corf_low = code->cur + 1;
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1339 jmp(code, code->cur + 2);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1340
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1341 *corf_low_range = code->cur - (corf_low_range + 1);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1342 mov_ir(code, 0x90, opts->gen.scratch1, SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1343 *corf_low = code->cur - (corf_low + 1);
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1344 mov_ir(code, 0x06, opts->gen.scratch2, SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1345
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1346 *no_corf_low = code->cur - (no_corf_low + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1347 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1348 code_ptr corf_high = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1349 jcc(code, CC_NZ, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1350 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1351 code_ptr no_corf_high = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1352 jcc(code, CC_C, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1353 *corf_high = code->cur - (corf_high + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1354 or_ir(code, 0x60, opts->gen.scratch2, SZ_B);
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1355 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1356 *no_corf_high = code->cur - (no_corf_high + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1357
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1358 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1359 xor_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1360
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1361 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1362 code_ptr not_sub = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1363 jcc(code, CC_Z, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1364 neg_r(code, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1365 *not_sub = code->cur - (not_sub + 1);
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1366
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1367 add_rr(code, opts->gen.scratch2, opts->regs[Z80_A], SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1368 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1369 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1370 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1371 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1372 bt_ir(code, 4, opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1373 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1050
d06c947a9a77 Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents: 1049
diff changeset
1374 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1375 break;
1046
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents: 1045
diff changeset
1376 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1377 case Z80_CPL:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1378 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1379 not_r(code, opts->regs[Z80_A], SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1380 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1381 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1050
d06c947a9a77 Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents: 1049
diff changeset
1382 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
274
be2b845d3e94 Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents: 273
diff changeset
1383 break;
be2b845d3e94 Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents: 273
diff changeset
1384 case Z80_NEG:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1385 cycles(&opts->gen, num_cycles);
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1386 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1387 neg_r(code, opts->regs[Z80_A], SZ_B);
1056
47c748455365 Fixed bug introduced in NEG with addition of undocumented flags
Michael Pavone <pavone@retrodev.com>
parents: 1055
diff changeset
1388 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1389 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1390 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1391 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1392 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1393 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1394 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1395 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
1396 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
274
be2b845d3e94 Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents: 273
diff changeset
1397 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1398 case Z80_CCF:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1399 cycles(&opts->gen, num_cycles);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1400 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1401 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1402 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1403 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1050
d06c947a9a77 Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents: 1049
diff changeset
1404 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
257
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
1405 break;
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
1406 case Z80_SCF:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1407 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1408 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1409 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1410 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1050
d06c947a9a77 Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents: 1049
diff changeset
1411 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
257
4c7933444df4 Implement CCF and SCF
Mike Pavone <pavone@retrodev.com>
parents: 255
diff changeset
1412 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1413 case Z80_NOP:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1414 cycles(&opts->gen, num_cycles);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1415 break;
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1416 case Z80_HALT: {
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1417 code_ptr loop_top = code->cur;
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1418 //this isn't terribly efficient, but it's good enough for now
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1419 cycles(&opts->gen, num_cycles);
1147
06468b25a543 Fix implementation of Z80 HALT instruction
Michael Pavone <pavone@retrodev.com>
parents: 1142
diff changeset
1420 check_cycles_int(&opts->gen, address+1);
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1421 jmp(code, loop_top);
285
021aeb6df19b Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents: 284
diff changeset
1422 break;
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1423 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1424 case Z80_DI:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1425 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1426 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1427 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
1110
d1eed3b1121c Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1062
diff changeset
1428 //turn cycles remaining into current cycle
d1eed3b1121c Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1062
diff changeset
1429 neg_r(code, opts->gen.cycles, SZ_D);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
1430 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D);
1110
d1eed3b1121c Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1062
diff changeset
1431 //set interrupt cycle to never and fetch the new target cycle from sync_cycle
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
1432 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.scratch1, SZ_D);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1433 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
1434 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
1110
d1eed3b1121c Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1062
diff changeset
1435 //turn current cycle back into cycles remaining
d1eed3b1121c Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1062
diff changeset
1436 neg_r(code, opts->gen.cycles, SZ_D);
d1eed3b1121c Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1062
diff changeset
1437 add_rr(code, opts->gen.scratch1, opts->gen.cycles, SZ_D);
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
1438 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1439 case Z80_EI:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1440 cycles(&opts->gen, num_cycles);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
1441 neg_r(code, opts->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
1442 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1443 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
1444 neg_r(code, opts->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
1445 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1446 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1447 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
335
14a937097c2b Some Z80 interrupt fixes
Mike Pavone <pavone@retrodev.com>
parents: 315
diff changeset
1448 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
1449 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1450 call(code, opts->do_sync);
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
1451 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1452 case Z80_IM:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1453 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1454 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
1455 break;
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1456 case Z80_RLC:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1457 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1458 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1459 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1460 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1461 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1462 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1463 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1464 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1465 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1466 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1467 translate_z80_reg(inst, &dst_op, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1468 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1469 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1470 rol_ir(code, 1, dst_op.base, SZ_B);
1053
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1471 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1472 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1473 rol_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1053
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1474 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1475 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1476 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1477 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1478 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1479 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1480 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1481 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1482 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1483 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1484 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1485 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1486 //rlca does not set these flags
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1487 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1488 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1489 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1490 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1491 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1492 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1493 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1494 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1495 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1496 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1497 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1498 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1499 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1500 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1501 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1502 z80_save_reg(inst, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1503 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1504 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1505 case Z80_RL:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1506 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1507 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1508 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1509 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1510 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1511 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1512 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1513 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1514 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1515 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1516 translate_z80_reg(inst, &dst_op, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1517 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1518 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1519 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1520 rcl_ir(code, 1, dst_op.base, SZ_B);
1053
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1521 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1522 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1523 rcl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1053
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1524 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1525 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1526 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1527 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1528 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1529 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1530 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1531 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1532 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1533 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1534 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1535 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1536 //rla does not set these flags
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1537 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1538 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1539 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1540 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1541 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1542 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1543 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1544 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1545 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1546 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1547 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1548 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1549 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1550 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1551 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1552 z80_save_reg(inst, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1553 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1554 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1555 case Z80_RRC:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1556 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1557 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1558 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1559 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1560 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1561 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1562 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1563 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1564 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1565 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1566 translate_z80_reg(inst, &dst_op, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1567 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1568 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1569 ror_ir(code, 1, dst_op.base, SZ_B);
1053
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1570 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1571 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1572 ror_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1053
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1573 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1574 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1575 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1576 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1577 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1578 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1579 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1580 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1581 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1582 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1583 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1584 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1585 //rrca does not set these flags
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1586 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1587 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1588 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1589 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1590 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1591 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1592 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1593 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1594 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1595 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1596 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1597 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1598 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1599 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1600 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1601 z80_save_reg(inst, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1602 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1603 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1604 case Z80_RR:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1605 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1606 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1607 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1608 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1609 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1610 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1611 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1612 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1613 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1614 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1615 translate_z80_reg(inst, &dst_op, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1616 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1617 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1618 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1619 rcr_ir(code, 1, dst_op.base, SZ_B);
1053
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1620 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1621 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1622 rcr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1053
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1623 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents: 1052
diff changeset
1624 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1625 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1626 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1627 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1628 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1629 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1630 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1631 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1632 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1633 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1634 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1635 //rra does not set these flags
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1636 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1637 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1638 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1639 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1640 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1641 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1642 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1643 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
1644 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1645 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1646 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1647 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1648 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1649 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1650 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1651 z80_save_reg(inst, opts);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1652 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1653 break;
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1654 case Z80_SLA:
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1655 case Z80_SLL:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1656 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1657 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1658 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1659 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1660 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1661 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1662 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1663 cycles(&opts->gen, 1);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1664 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1665 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1666 translate_z80_reg(inst, &dst_op, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1667 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1668 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1669 shl_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1670 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1671 shl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1672 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1673 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
310
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents: 309
diff changeset
1674 if (inst->op == Z80_SLL) {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1675 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1676 or_ir(code, 1, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1677 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1678 or_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1679 }
310
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents: 309
diff changeset
1680 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1681 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1682 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1683 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1684 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1685 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1686 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1687 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1688 if (dst_op.mode == MODE_REG_DIRECT) {
1055
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1689 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1690 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1691 } else {
1055
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1692 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1693 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1694 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1695 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1696 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1697 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1698 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1699 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1700 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1701 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1702 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1703 }
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1704 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1705 z80_save_reg(inst, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1706 }
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1707 break;
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1708 case Z80_SRA:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1709 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1710 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1711 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1712 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1713 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1714 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1715 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1716 cycles(&opts->gen, 1);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1717 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1718 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1719 translate_z80_reg(inst, &dst_op, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1720 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1721 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1722 sar_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1723 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1724 sar_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1725 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1726 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1727 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1728 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1729 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1730 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1731 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1732 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1733 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1734 if (dst_op.mode == MODE_REG_DIRECT) {
1055
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1735 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1736 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1737 } else {
1055
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1738 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1739 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1740 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1741 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1742 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1743 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1744 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1745 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1746 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1747 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1748 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1749 }
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1750 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1751 z80_save_reg(inst, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1752 }
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1753 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1754 case Z80_SRL:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1755 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1756 num_cycles += 8;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1757 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1758 cycles(&opts->gen, num_cycles);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1759 if (inst->addr_mode != Z80_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1760 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1761 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1762 cycles(&opts->gen, 1);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1763 } else {
302
3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents: 301
diff changeset
1764 src_op.mode = MODE_UNUSED;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1765 translate_z80_reg(inst, &dst_op, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1766 }
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1767 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1768 shr_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1769 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1770 shr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1771 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1772 if (src_op.mode == MODE_REG_DIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1773 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1774 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
1775 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1776 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1777 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1778 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1779 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1780 if (dst_op.mode == MODE_REG_DIRECT) {
1055
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1781 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1782 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1783 } else {
1055
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1784 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
ac4615d16226 Implement undocumented flag bits for shift instructions
Michael Pavone <pavone@retrodev.com>
parents: 1054
diff changeset
1785 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1786 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1787 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1788 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1789 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1790 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1791 if (inst->addr_mode != Z80_UNUSED) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1792 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1793 if (src_op.mode != MODE_UNUSED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1794 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1795 }
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1796 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1797 z80_save_reg(inst, opts);
275
1a7d0a964ad2 Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 274
diff changeset
1798 }
310
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents: 309
diff changeset
1799 break;
286
872a8911e0f4 Implemente RLD
Mike Pavone <pavone@retrodev.com>
parents: 285
diff changeset
1800 case Z80_RLD:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1801 cycles(&opts->gen, num_cycles);
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1802 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1803 call(code, opts->read_8);
286
872a8911e0f4 Implemente RLD
Mike Pavone <pavone@retrodev.com>
parents: 285
diff changeset
1804 //Before: (HL) = 0x12, A = 0x34
872a8911e0f4 Implemente RLD
Mike Pavone <pavone@retrodev.com>
parents: 285
diff changeset
1805 //After: (HL) = 0x24, A = 0x31
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1806 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1807 shl_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1808 and_ir(code, 0xF, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1809 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1810 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1811 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
1812 //opts->gen.scratch1 = 0x0124
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1813 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1814 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1815 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1816 //set flags
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1817 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1818 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1819 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1820 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1821 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1054
ca38a29d2d76 Implement undocumented flag bits for RLD and RRD
Michael Pavone <pavone@retrodev.com>
parents: 1053
diff changeset
1822 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1823
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1824 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1825 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1826 call(code, opts->write_8);
286
872a8911e0f4 Implemente RLD
Mike Pavone <pavone@retrodev.com>
parents: 285
diff changeset
1827 break;
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1828 case Z80_RRD:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1829 cycles(&opts->gen, num_cycles);
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1830 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1831 call(code, opts->read_8);
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1832 //Before: (HL) = 0x12, A = 0x34
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1833 //After: (HL) = 0x41, A = 0x32
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1834 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1835 ror_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1836 shl_ir(code, 4, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1837 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1838 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
967
1eb616b8cbe9 Fix bug in Z80 rrd implementation. This fixes the annoying high pitched wine in Afterburner II.
Michael Pavone <pavone@retrodev.com>
parents: 966
diff changeset
1839 and_ir(code, 0xF0, opts->gen.scratch2, SZ_W);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
1840 //opts->gen.scratch1 = 0x2001
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
1841 //opts->gen.scratch2 = 0x0040
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1842 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
1843 //opts->gen.scratch1 = 0x2041
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1844 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1845 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1846 shr_ir(code, 4, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1847 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1848 //set flags
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1849 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1850 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1851 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1852 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1853 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1054
ca38a29d2d76 Implement undocumented flag bits for RLD and RRD
Michael Pavone <pavone@retrodev.com>
parents: 1053
diff changeset
1854 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1855
734
e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents: 731
diff changeset
1856 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1857 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1858 call(code, opts->write_8);
287
fb840e0a48cd Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents: 286
diff changeset
1859 break;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1860 case Z80_BIT: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1861 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1761
873a1330c3a9 Fix cycle counts of a few instructions in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1592
diff changeset
1862 num_cycles += 4;
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1863 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1864 cycles(&opts->gen, num_cycles);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1865 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1866 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1867 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737
043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents: 735
diff changeset
1868 src_op.mode = MODE_REG_DIRECT;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1869 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1870 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1871 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1872 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1873 bit = inst->immed;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1874 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1875 }
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1876 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1877 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1878 cycles(&opts->gen, 1);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1879 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1880 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1881 bt_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1882 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1883 bt_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1884 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1885 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1886 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1887 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
1888 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
307
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents: 306
diff changeset
1889 if (inst->immed == 7) {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1890 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1891 cmp_ir(code, 0, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1892 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1893 cmp_irdisp(code, 0, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1894 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1895 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
307
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents: 306
diff changeset
1896 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1897 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
307
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents: 306
diff changeset
1898 }
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1899
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1900 if ((inst->addr_mode & 0x1F) == Z80_REG) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1901 if (src_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1902 if (size == SZ_W) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1903 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1904 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1905 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1906 } else {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1907 mov_rrdisp(code, src_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1908 }
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1909 } else {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1910 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1911 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1912 }
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1913 } else if((inst->addr_mode & 0x1F) != Z80_REG_INDIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1914 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, opts->gen.scratch2);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1915 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1916 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1917 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
1918 }
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
1919 break;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1920 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1921 case Z80_SET: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1922 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1767
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
1923 num_cycles += 4;
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1924 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1925 cycles(&opts->gen, num_cycles);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1926 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1927 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1928 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737
043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents: 735
diff changeset
1929 src_op.mode = MODE_REG_DIRECT;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1930 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1931 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1932 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1933 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1934 bit = inst->immed;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1935 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1936 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1937 if (inst->reg != Z80_USE_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1938 translate_z80_reg(inst, &dst_op, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1939 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1940 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1941 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1942 cycles(&opts->gen, 1);
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
1943 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1944 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1945 bts_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1946 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1947 bts_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1948 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
1949 if (inst->reg != Z80_USE_IMMED) {
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1950 if (size == SZ_W) {
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1951 #ifdef X86_64
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1952 if (dst_op.base >= R8) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1953 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1954 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1955 ror_ir(code, 8, src_op.base, SZ_W);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1956 } else {
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1957 #endif
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1958 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1959 zreg_to_native(opts, inst->ea_reg, dst_op.base);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1960 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1961 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1962 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1963 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1964 #ifdef X86_64
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1965 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
1966 #endif
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1967 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1968 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1969 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1970 mov_rr(code, src_op.base, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1971 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1972 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1973 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1974 } else if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1975 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1976 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1977 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1978 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
1979 }
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1980 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1981 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1982 if ((inst->addr_mode & 0x1F) != Z80_REG) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
1983 z80_save_result(opts, inst);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1984 if (inst->reg != Z80_USE_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1985 z80_save_reg(inst, opts);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1986 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1987 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1988 break;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1989 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1990 case Z80_RES: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1991 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1767
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
1992 num_cycles += 4;
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
1993 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
1994 cycles(&opts->gen, num_cycles);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1995 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1996 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1997 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737
043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents: 735
diff changeset
1998 src_op.mode = MODE_REG_DIRECT;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
1999 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2000 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2001 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2002 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2003 bit = inst->immed;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2004 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2005 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2006 if (inst->reg != Z80_USE_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2007 translate_z80_reg(inst, &dst_op, opts);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2008 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2009 if (inst->addr_mode != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2010 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2011 cycles(&opts->gen, 1);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2012 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2013 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2014 btr_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2015 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2016 btr_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2017 }
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2018 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2019 if (size == SZ_W) {
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2020 #ifdef X86_64
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2021 if (dst_op.base >= R8) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2022 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2023 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2024 ror_ir(code, 8, src_op.base, SZ_W);
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2025 } else {
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2026 #endif
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2027 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2028 zreg_to_native(opts, inst->ea_reg, dst_op.base);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2029 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2030 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2031 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2032 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2033 #ifdef X86_64
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2034 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
2035 #endif
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2036 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2037 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2038 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2039 mov_rr(code, src_op.base, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2040 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2041 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2042 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2043 } else if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2044 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2045 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2046 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2047 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
2048 }
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2049 }
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
2050 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
2051 if (inst->addr_mode != Z80_REG) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2052 z80_save_result(opts, inst);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
2053 if (inst->reg != Z80_USE_IMMED) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2054 z80_save_reg(inst, opts);
299
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents: 295
diff changeset
2055 }
247
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
2056 }
682e505f5757 Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents: 246
diff changeset
2057 break;
308
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents: 307
diff changeset
2058 }
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2059 case Z80_JP: {
506
a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
2060 if (inst->addr_mode != Z80_REG_INDIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2061 num_cycles += 6;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2062 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2063 cycles(&opts->gen, num_cycles);
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2064 if (inst->addr_mode != Z80_REG_INDIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2065 code_ptr call_dst = z80_get_native_address(context, inst->immed);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2066 if (!call_dst) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2067 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2068 //fake address to force large displacement
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
2069 call_dst = code->cur + 256;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2070 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2071 jmp(code, call_dst);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2072 } else {
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
2073 if (inst->addr_mode == Z80_REG_INDIRECT) {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
2074 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2075 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2076 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2077 }
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2078 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2079 jmp_r(code, opts->gen.scratch1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2080 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2081 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2082 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2083 case Z80_JPCC: {
1561
5a6339e46917 Fix timing for Z80 JP cc, nn instruction
Michael Pavone <pavone@retrodev.com>
parents: 1471
diff changeset
2084 cycles(&opts->gen, num_cycles + 6);//T States: 4,3,3
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2085 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2086 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2087 {
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2088 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2089 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2090 case Z80_CC_Z:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2091 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2092 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2093 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2094 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2095 case Z80_CC_C:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2096 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2097 break;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2098 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2099 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2100 case Z80_CC_PE:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2101 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2102 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2103 case Z80_CC_P:
367
f20562f2a570 Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 366
diff changeset
2104 cond = CC_NZ;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2105 case Z80_CC_M:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2106 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2107 break;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2108 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2109 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2110 jcc(code, cond, code->cur+2);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2111 uint16_t dest_addr = inst->immed;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2112 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2113 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2114 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2115 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2116 call_dst = code->cur + 256;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2117 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2118 jmp(code, call_dst);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2119 *no_jump_off = code->cur - (no_jump_off+1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2120 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2121 }
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2122 case Z80_JR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2123 cycles(&opts->gen, num_cycles + 8);//T States: 4,3,5
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2124 uint16_t dest_addr = address + inst->immed + 2;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2125 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2126 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2127 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2128 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2129 call_dst = code->cur + 256;
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2130 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2131 jmp(code, call_dst);
236
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2132 break;
19fb3523a9e5 Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents: 235
diff changeset
2133 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2134 case Z80_JRCC: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2135 cycles(&opts->gen, num_cycles + 3);//T States: 4,3
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2136 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2137 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2138 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2139 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2140 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2141 case Z80_CC_Z:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2142 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2143 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2144 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2145 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2146 case Z80_CC_C:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2147 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2148 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2149 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2150 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2151 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2152 cycles(&opts->gen, 5);//T States: 5
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2153 uint16_t dest_addr = address + inst->immed + 2;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2154 code_ptr call_dst = z80_get_native_address(context, dest_addr);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2155 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2156 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2157 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2158 call_dst = code->cur + 256;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2159 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2160 jmp(code, call_dst);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2161 *no_jump_off = code->cur - (no_jump_off+1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2162 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2163 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2164 case Z80_DJNZ: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2165 cycles(&opts->gen, num_cycles + 4);//T States: 5,3
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
2166 if (opts->regs[Z80_B] >= 0) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
2167 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
2168 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
2169 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
2170 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2171 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2172 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2173 cycles(&opts->gen, 5);//T States: 5
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
2174 uint16_t dest_addr = address + inst->immed + 2;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2175 code_ptr call_dst = z80_get_native_address(context, dest_addr);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
2176 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2177 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
2178 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2179 call_dst = code->cur + 256;
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
2180 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2181 jmp(code, call_dst);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2182 *no_jump_off = code->cur - (no_jump_off+1);
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
2183 break;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
2184 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2185 case Z80_CALL: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2186 cycles(&opts->gen, num_cycles + 7);//T States: 4,3,4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2187 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2188 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2189 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2190 call(code, opts->write_16_highfirst);//T States: 3, 3
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2191 code_ptr call_dst = z80_get_native_address(context, inst->immed);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2192 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2193 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2194 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2195 call_dst = code->cur + 256;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2196 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2197 jmp(code, call_dst);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2198 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2199 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2200 case Z80_CALLCC: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2201 cycles(&opts->gen, num_cycles + 6);//T States: 4,3,3 (false case)
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2202 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2203 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2204 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2205 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2206 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2207 case Z80_CC_Z:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2208 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2209 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2210 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2211 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2212 case Z80_CC_C:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2213 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2214 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2215 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2216 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2217 case Z80_CC_PE:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2218 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2219 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2220 case Z80_CC_P:
367
f20562f2a570 Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 366
diff changeset
2221 cond = CC_NZ;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2222 case Z80_CC_M:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2223 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2224 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2225 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2226 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2227 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2228 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2229 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2230 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2231 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2232 call(code, opts->write_16_highfirst);//T States: 3, 3
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2233 code_ptr call_dst = z80_get_native_address(context, inst->immed);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2234 if (!call_dst) {
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2235 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2236 //fake address to force large displacement
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2237 call_dst = code->cur + 256;
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2238 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
2239 jmp(code, call_dst);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2240 *no_call_off = code->cur - (no_call_off+1);
238
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents: 236
diff changeset
2241 break;
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
2242 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2243 case Z80_RET:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2244 cycles(&opts->gen, num_cycles);//T States: 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2245 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2246 call(code, opts->read_16);//T STates: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2247 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2248 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2249 jmp_r(code, opts->gen.scratch1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2250 break;
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2251 case Z80_RETCC: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2252 cycles(&opts->gen, num_cycles + 1);//T States: 5
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2253 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2254 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2255 {
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2256 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2257 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2258 case Z80_CC_Z:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2259 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2260 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2261 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2262 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2263 case Z80_CC_C:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2264 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2265 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2266 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2267 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2268 case Z80_CC_PE:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2269 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2270 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2271 case Z80_CC_P:
367
f20562f2a570 Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 366
diff changeset
2272 cond = CC_NZ;
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2273 case Z80_CC_M:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2274 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2275 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2276 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2277 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2278 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2279 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2280 call(code, opts->read_16);//T STates: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2281 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2282 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2283 jmp_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2284 *no_call_off = code->cur - (no_call_off+1);
246
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2285 break;
ed548c77b598 Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents: 243
diff changeset
2286 }
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2287 case Z80_RETI:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2288 //For some systems, this may need a callback for signalling interrupt routine completion
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2289 cycles(&opts->gen, num_cycles);//T States: 4, 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2290 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2291 call(code, opts->read_16);//T STates: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2292 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2293 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2294 jmp_r(code, opts->gen.scratch1);
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2295 break;
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2296 case Z80_RETN:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2297 cycles(&opts->gen, num_cycles);//T States: 4, 4
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2298 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2299 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2300 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2301 call(code, opts->read_16);//T STates: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2302 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2303 call(code, opts->native_addr);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2304 jmp_r(code, opts->gen.scratch1);
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
2305 break;
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2306 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2307 //RST is basically CALL to an address in page 0
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2308 cycles(&opts->gen, num_cycles + 1);//T States: 5
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2309 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2310 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2311 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2312 call(code, opts->write_16_highfirst);//T States: 3, 3
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2313 code_ptr call_dst = z80_get_native_address(context, inst->immed);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2314 if (!call_dst) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2315 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2316 //fake address to force large displacement
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
2317 call_dst = code->cur + 256;
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2318 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2319 jmp(code, call_dst);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2320 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
2321 }
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2322 case Z80_IN:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2323 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2324 num_cycles += 3;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2325 }
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2326 cycles(&opts->gen, num_cycles);//T States: 4 3/4
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2327 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2328 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2329 } else {
1260
cad1642baf66 Fix implementation of in c and out c on 32-bit x86
Michael Pavone <pavone@retrodev.com>
parents: 1225
diff changeset
2330 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2331 }
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2332 call(code, opts->read_io);
1042
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2333 if (inst->addr_mode != Z80_IMMED_INDIRECT) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2334 or_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2335 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2336 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2337 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2338 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2339 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2340 }
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2341 if (inst->reg != Z80_UNUSED) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2342 translate_z80_reg(inst, &dst_op, opts);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2343 if (dst_op.mode == MODE_REG_DIRECT) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2344 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2345 } else {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2346 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents: 1040
diff changeset
2347 }
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2348 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2349 z80_save_reg(inst, opts);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2350 break;
1060
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2351 case Z80_INI:
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2352 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2353 //read from IO (C)
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2354 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2355 call(code, opts->read_io);//T states 3
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2356
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2357 //undocumented N flag behavior
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2358 //flag set on bit 7 of value written
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2359 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2360 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2361 //save value to be written for flag calculation, as the write func does not
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2362 //guarantee that it's preserved across the call
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2363 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2364
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2365 //write to (HL)
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2366 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2367 call(code, opts->write_8);//T states 4
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2368 cycles(&opts->gen, 1);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2369
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2370 //increment HL
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2371 if (opts->regs[Z80_HL] >= 0) {
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2372 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2373 } else {
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2374 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2375 }
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2376 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2377 if (opts->regs[Z80_C] >= 0) {
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2378 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2379 } else {
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2380 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2381 }
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2382 add_ir(code, 1, opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2383 //undocumented C and H flag behavior
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2384 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2385 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2386 //decrement B
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2387 if (opts->regs[Z80_B] >= 0) {
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2388 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2389 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2390 } else {
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2391 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2392 }
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2393 //undocumented Z and S flag behavior, set based on decrement of B
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2394 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2395 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2396 //crazy undocumented P/V flag behavior
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2397 and_ir(code, 7, opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2398 if (opts->regs[Z80_B] >= 0) {
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2399 //deal with silly x86-64 restrictions on *H registers
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2400 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2401 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2402 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2403 } else {
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2404 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2405 }
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2406 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
56713dac6a69 Implement INI
Michael Pavone <pavone@retrodev.com>
parents: 1057
diff changeset
2407 break;
1061
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2408 case Z80_INIR: {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2409 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2410 //read from IO (C)
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2411 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2412 call(code, opts->read_io);//T states 3
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2413
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2414 //undocumented N flag behavior
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2415 //flag set on bit 7 of value written
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2416 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2417 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2418 //save value to be written for flag calculation, as the write func does not
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2419 //guarantee that it's preserved across the call
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2420 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2421
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2422 //write to (HL)
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2423 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2424 call(code, opts->write_8);//T states 4
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2425 cycles(&opts->gen, 1);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2426
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2427 //increment HL
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2428 if (opts->regs[Z80_HL] >= 0) {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2429 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2430 } else {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2431 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2432 }
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2433 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2434 if (opts->regs[Z80_C] >= 0) {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2435 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2436 } else {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2437 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2438 }
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2439 add_ir(code, 1, opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2440 //undocumented C and H flag behavior
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2441 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2442 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2443 //decrement B
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2444 if (opts->regs[Z80_B] >= 0) {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2445 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2446 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2447 } else {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2448 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2449 }
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2450 //undocumented Z and S flag behavior, set based on decrement of B
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2451 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2452 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2453 //crazy undocumented P/V flag behavior
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2454 and_ir(code, 7, opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2455 if (opts->regs[Z80_B] >= 0) {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2456 //deal with silly x86-64 restrictions on *H registers
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2457 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2458 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2459 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2460 } else {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2461 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2462 }
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2463 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2464 if (opts->regs[Z80_B] >= 0) {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2465 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2466 } else {
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2467 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2468 }
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2469 code_ptr done = code->cur+1;
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2470 jcc(code, CC_Z, code->cur+2);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2471 cycles(&opts->gen, 5);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2472 jmp(code, start);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2473 *done = code->cur - (done + 1);
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2474 break;
9b5bb50098d2 Implemented INIR
Michael Pavone <pavone@retrodev.com>
parents: 1060
diff changeset
2475 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2476 case Z80_IND:
1062
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2477 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2478 //read from IO (C)
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2479 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2480 call(code, opts->read_io);//T states 3
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2481
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2482 //undocumented N flag behavior
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2483 //flag set on bit 7 of value written
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2484 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2485 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2486 //save value to be written for flag calculation, as the write func does not
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2487 //guarantee that it's preserved across the call
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2488 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2489
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2490 //write to (HL)
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2491 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2492 call(code, opts->write_8);//T states 4
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2493 cycles(&opts->gen, 1);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2494
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2495 //decrement HL
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2496 if (opts->regs[Z80_HL] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2497 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2498 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2499 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2500 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2501 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2502 if (opts->regs[Z80_C] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2503 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2504 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2505 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2506 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2507 add_ir(code, 1, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2508 //undocumented C and H flag behavior
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2509 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2510 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2511 //decrement B
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2512 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2513 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2514 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2515 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2516 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2517 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2518 //undocumented Z and S flag behavior, set based on decrement of B
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2519 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2520 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2521 //crazy undocumented P/V flag behavior
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2522 and_ir(code, 7, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2523 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2524 //deal with silly x86-64 restrictions on *H registers
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2525 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2526 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2527 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2528 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2529 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2530 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2531 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2532 break;
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2533 case Z80_INDR: {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2534 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2535 //read from IO (C)
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2536 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2537 call(code, opts->read_io);//T states 3
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2538
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2539 //undocumented N flag behavior
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2540 //flag set on bit 7 of value written
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2541 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2542 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2543 //save value to be written for flag calculation, as the write func does not
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2544 //guarantee that it's preserved across the call
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2545 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2546
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2547 //write to (HL)
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2548 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2549 call(code, opts->write_8);//T states 4
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2550 cycles(&opts->gen, 1);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2551
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2552 //decrement HL
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2553 if (opts->regs[Z80_HL] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2554 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2555 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2556 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2557 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2558 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2559 if (opts->regs[Z80_C] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2560 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2561 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2562 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2563 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2564 add_ir(code, 1, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2565 //undocumented C and H flag behavior
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2566 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2567 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2568 //decrement B
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2569 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2570 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2571 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2572 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2573 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2574 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2575 //undocumented Z and S flag behavior, set based on decrement of B
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2576 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2577 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2578 //crazy undocumented P/V flag behavior
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2579 and_ir(code, 7, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2580 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2581 //deal with silly x86-64 restrictions on *H registers
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2582 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2583 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2584 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2585 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2586 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2587 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2588 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2589 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2590 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2591 } else {
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2592 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2593 }
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2594 code_ptr done = code->cur+1;
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2595 jcc(code, CC_Z, code->cur+2);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2596 cycles(&opts->gen, 5);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2597 jmp(code, start);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2598 *done = code->cur - (done + 1);
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2599 break;
779acbfb74d0 Implemented IND and INDR
Michael Pavone <pavone@retrodev.com>
parents: 1061
diff changeset
2600 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2601 case Z80_OUT:
1761
873a1330c3a9 Fix cycle counts of a few instructions in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1592
diff changeset
2602 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2603 num_cycles += 3;
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2604 }
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2605 cycles(&opts->gen, num_cycles);//T States: 4 3/4
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2606 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2607 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2608 } else {
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2609 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2610 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2611 translate_z80_reg(inst, &src_op, opts);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2612 if (src_op.mode == MODE_REG_DIRECT) {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2613 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2614 } else if (src_op.mode == MODE_IMMED) {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2615 mov_ir(code, src_op.disp, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2616 } else {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2617 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
2618 }
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
2619 call(code, opts->write_io);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
2620 z80_save_reg(inst, opts);
284
ed7098f717d7 Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents: 283
diff changeset
2621 break;
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2622 case Z80_OUTI:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2623 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2624 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2625 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2626 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2627 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2628 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2629 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2630 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2631 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2632 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2633 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2634 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2635 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2636 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2637 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2638 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2639 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2640 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2641 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2642 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2643 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2644 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2645 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2646 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2647 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2648 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2649 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2650 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2651 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2652 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2653 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2654 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2655 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2656 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2657 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2658 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2659 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2660 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2661 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2662 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2663 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2664 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2665 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2666 case Z80_OTIR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2667 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2668 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2669 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2670 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2671 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2672 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2673 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2674 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2675 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2676 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2677 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2678 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2679 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2680 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2681 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2682 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2683 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2684 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2685 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2686 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2687 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2688 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2689 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2690 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2691 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2692 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2693 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2694 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2695 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2696 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2697 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2698 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2699 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2700 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2701 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2702 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2703 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2704 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2705 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2706 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2707 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2708 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2709 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2710 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2711 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2712 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2713 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2714 code_ptr done = code->cur+1;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2715 jcc(code, CC_Z, code->cur+2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2716 cycles(&opts->gen, 5);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2717 jmp(code, start);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2718 *done = code->cur - (done + 1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2719 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2720 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2721 case Z80_OUTD:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2722 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2723 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2724 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2725 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2726 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2727 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2728 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2729 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2730 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2731 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2732 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2733 //decrement HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2734 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2735 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2736 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2737 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2738 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2739 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2740 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2741 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2742 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2743 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2744 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2745 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2746 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2747 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2748 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2749 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2750 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2751 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2752 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2753 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2754 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2755 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2756 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2757 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2758 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2759 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2760 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2761 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2762 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2763 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2764 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2765 case Z80_OTDR: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2766 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2767 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2768 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2769 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2770 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2771 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2772 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2773 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2774 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2775 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2776 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2777 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2778 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2779 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2780 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2781 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2782 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2783 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2784 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2785 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2786 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2787 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2788 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2789 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2790 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2791 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2792 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2793 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2794 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2795 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2796 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2797 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2798 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2799 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2800 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2801 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2802 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2803 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2804 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2805 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2806 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2807 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2808 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2809 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2810 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2811 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2812 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2813 code_ptr done = code->cur+1;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2814 jcc(code, CC_Z, code->cur+2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2815 cycles(&opts->gen, 5);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2816 jmp(code, start);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2817 *done = code->cur - (done + 1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2818 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents: 967
diff changeset
2819 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2820 default: {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2821 char disbuf[80];
314
54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents: 313
diff changeset
2822 z80_disasm(inst, disbuf, address);
259
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
2823 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
2824 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents: 257
diff changeset
2825 fclose(f);
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
2826 fatal_error("unimplemented Z80 instruction: %s at %X\nZ80 RAM has been saved to zram.bin for debugging", disbuf, address);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2827 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2828 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2829 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2830
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2831 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context)
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2832 {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2833 if (!context->interp_code[opcode]) {
755
7306b3967c51 Cleanup some warnings under clang through a combination of code fixes and supressing specific warnings
Michael Pavone <pavone@retrodev.com>
parents: 737
diff changeset
2834 if (opcode == 0xCB || (opcode >= 0xDD && (opcode & 0xF) == 0xD)) {
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
2835 fatal_error("Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2836 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2837 uint8_t codebuf[8];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2838 memset(codebuf, 0, sizeof(codebuf));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2839 codebuf[0] = opcode;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2840 z80inst inst;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2841 uint8_t * after = z80_decode(codebuf, &inst);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2842 if (after - codebuf > 1) {
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
2843 fatal_error("Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2844 }
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2845
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2846 z80_options * opts = context->options;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2847 code_info *code = &opts->gen.code;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2848 check_alloc_code(code, ZMAX_NATIVE_SIZE);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2849 context->interp_code[opcode] = code->cur;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2850 translate_z80inst(&inst, context, 0, 1);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2851 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2852 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2853 call(code, opts->native_addr);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2854 jmp_r(code, opts->gen.scratch1);
715
1c2020d3e275 Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly
Michael Pavone <pavone@retrodev.com>
parents: 712
diff changeset
2855 z80_handle_deferred(context);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2856 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2857 return context->interp_code[opcode];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2858 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2859
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2860 code_info z80_make_interp_stub(z80_context * context, uint16_t address)
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2861 {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2862 z80_options *opts = context->options;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2863 code_info * code = &opts->gen.code;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2864 check_alloc_code(code, 32);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2865 code_info stub = {code->cur, NULL};
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2866 //TODO: make this play well with the breakpoint code
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2867 mov_ir(code, address, opts->gen.scratch1, SZ_W);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2868 call(code, opts->read_8);
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2869 //opcode fetch M-cycles have one extra T-state
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2870 cycles(&opts->gen, 1);
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
2871 //TODO: increment R
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2872 check_cycles_int(&opts->gen, address);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2873 call(code, opts->gen.save_context);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2874 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2875 push_r(code, opts->gen.context_reg);
712
382a2b5b70c0 Fix crash bug in Z80 interpreter
Michael Pavone <pavone@retrodev.com>
parents: 702
diff changeset
2876 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.context_reg);
664
bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents: 663
diff changeset
2877 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2878 pop_r(code, opts->gen.context_reg);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2879 call(code, opts->gen.load_context);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2880 jmp_r(code, opts->gen.scratch1);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2881 stub.last = code->cur;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
2882 return stub;
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2883 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2884
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
2885
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2886 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2887 {
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2888 z80_options *opts = context->options;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2889 native_map_slot * native_code_map = opts->gen.native_code_map;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2890
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2891 memmap_chunk const *mem_chunk = find_map_chunk(address, &opts->gen, 0, NULL);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2892 if (mem_chunk) {
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2893 //calculate the lowest alias for this address
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2894 address = mem_chunk->start + ((address - mem_chunk->start) & mem_chunk->mask);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2895 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2896 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2897 if (!native_code_map[chunk].base) {
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2898 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2899 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2900 uint32_t offset = address % NATIVE_CHUNK_SIZE;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2901 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET || native_code_map[chunk].offsets[offset] == EXTENSION_WORD) {
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2902 return NULL;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2903 }
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2904 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2905 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2906
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2907 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2908 {
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2909 uint32_t meta_off;
1142
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
2910 memmap_chunk const *chunk = find_map_chunk(address, &opts->gen, MMAP_CODE, &meta_off);
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2911 if (chunk) {
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2912 meta_off += (address - chunk->start) & chunk->mask;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2913 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2914 uint32_t slot = meta_off/1024;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2915 return opts->gen.ram_inst_sizes[slot][meta_off%1024];
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2916 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2917
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2918 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2919 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
2920 z80_options * opts = context->options;
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2921 uint32_t meta_off;
1142
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
2922 memmap_chunk const *mem_chunk = find_map_chunk(address, &opts->gen, MMAP_CODE, &meta_off);
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2923 if (mem_chunk) {
1142
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
2924 if (mem_chunk->flags & MMAP_CODE) {
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2925 uint32_t masked = (address & mem_chunk->mask);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2926 uint32_t final_off = masked + meta_off;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2927 uint32_t ram_flags_off = final_off >> (opts->gen.ram_flags_shift + 3);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2928 context->ram_code_flags[ram_flags_off] |= 1 << ((final_off >> opts->gen.ram_flags_shift) & 7);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2929
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2930 uint32_t slot = final_off / 1024;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2931 if (!opts->gen.ram_inst_sizes[slot]) {
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2932 opts->gen.ram_inst_sizes[slot] = malloc(sizeof(uint8_t) * 1024);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2933 }
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2934 opts->gen.ram_inst_sizes[slot][final_off % 1024] = native_size;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2935
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2936 //TODO: Deal with case in which end of instruction is in a different memory chunk
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2937 masked = (address + size - 1) & mem_chunk->mask;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2938 final_off = masked + meta_off;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2939 ram_flags_off = final_off >> (opts->gen.ram_flags_shift + 3);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2940 context->ram_code_flags[ram_flags_off] |= 1 << ((final_off >> opts->gen.ram_flags_shift) & 7);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2941 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2942 //calculate the lowest alias for this address
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2943 address = mem_chunk->start + ((address - mem_chunk->start) & mem_chunk->mask);
1222
60d73f42a606 Hacky fix so sound works in Project MD again
Michael Pavone <pavone@retrodev.com>
parents: 1182
diff changeset
2944 } else {
60d73f42a606 Hacky fix so sound works in Project MD again
Michael Pavone <pavone@retrodev.com>
parents: 1182
diff changeset
2945 address &= opts->gen.address_mask;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2946 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2947
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2948 native_map_slot *map = opts->gen.native_code_map + address / NATIVE_CHUNK_SIZE;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2949 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2950 map->base = native_address;
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2951 map->offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2952 memset(map->offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
2953 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2954 map->offsets[address % NATIVE_CHUNK_SIZE] = native_address - map->base;
1182
2a799f24563f Fix regression in tracking of 3+ byte instructions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1147
diff changeset
2955 for(--size, address++; size; --size, address++) {
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2956 address &= opts->gen.address_mask;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2957 map = opts->gen.native_code_map + address / NATIVE_CHUNK_SIZE;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2958 if (!map->base) {
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2959 map->base = native_address;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2960 map->offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2961 memset(map->offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2962 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2963
1224
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
2964 if (map->offsets[address % NATIVE_CHUNK_SIZE] == INVALID_OFFSET) {
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
2965 //TODO: better handling of potentially overlapping instructions
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
2966 map->offsets[address % NATIVE_CHUNK_SIZE] = EXTENSION_WORD;
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
2967 }
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2968 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2969 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2970
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2971 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2972
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2973 uint32_t z80_get_instruction_start(z80_context *context, uint32_t address)
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2974 {
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2975 z80_options *opts = context->options;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2976 native_map_slot * native_code_map = opts->gen.native_code_map;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2977 memmap_chunk const *mem_chunk = find_map_chunk(address, &opts->gen, 0, NULL);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2978 if (mem_chunk) {
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2979 //calculate the lowest alias for this address
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2980 address = mem_chunk->start + ((address - mem_chunk->start) & mem_chunk->mask);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2981 }
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2982
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2983 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2984 if (!native_code_map[chunk].base) {
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2985 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2986 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2987 uint32_t offset = address % NATIVE_CHUNK_SIZE;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2988 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2989 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2990 }
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2991 while (native_code_map[chunk].offsets[offset] == EXTENSION_WORD)
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2992 {
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2993 --address;
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2994 chunk = address / NATIVE_CHUNK_SIZE;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2995 offset = address % NATIVE_CHUNK_SIZE;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2996 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2997 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2998 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
2999
1224
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3000 //Technically unbounded due to redundant prefixes, but this is the max useful size
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3001 #define Z80_MAX_INST_SIZE 4
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3002
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3003 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3004 {
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3005 uint32_t inst_start = z80_get_instruction_start(context, address);
1224
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3006 while (inst_start != INVALID_INSTRUCTION_START && (address - inst_start) < Z80_MAX_INST_SIZE) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3007 code_ptr dst = z80_get_native_address(context, inst_start);
899
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3008 code_info code = {dst, dst+32, 0};
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3009 z80_options * opts = context->options;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3010 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code.cur, inst_start, address);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3011 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3012 call(&code, opts->retrans_stub);
1224
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3013 inst_start = z80_get_instruction_start(context, inst_start - 1);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3014 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3015 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3016 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3017
1142
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3018 void z80_invalidate_code_range(z80_context *context, uint32_t start, uint32_t end)
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3019 {
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3020 z80_options *opts = context->options;
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3021 native_map_slot * native_code_map = opts->gen.native_code_map;
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3022 memmap_chunk const *mem_chunk = find_map_chunk(start, &opts->gen, 0, NULL);
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3023 if (mem_chunk) {
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3024 //calculate the lowest alias for this address
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3025 start = mem_chunk->start + ((start - mem_chunk->start) & mem_chunk->mask);
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3026 }
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3027 mem_chunk = find_map_chunk(end, &opts->gen, 0, NULL);
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3028 if (mem_chunk) {
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3029 //calculate the lowest alias for this address
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3030 end = mem_chunk->start + ((end - mem_chunk->start) & mem_chunk->mask);
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3031 }
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3032 uint32_t start_chunk = start / NATIVE_CHUNK_SIZE, end_chunk = end / NATIVE_CHUNK_SIZE;
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3033 for (uint32_t chunk = start_chunk; chunk <= end_chunk; chunk++)
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3034 {
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3035 if (native_code_map[chunk].base) {
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3036 uint32_t start_offset = chunk == start_chunk ? start % NATIVE_CHUNK_SIZE : 0;
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3037 uint32_t end_offset = chunk == end_chunk ? end % NATIVE_CHUNK_SIZE : NATIVE_CHUNK_SIZE;
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3038 for (uint32_t offset = start_offset; offset < end_offset; offset++)
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3039 {
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3040 if (native_code_map[chunk].offsets[offset] != INVALID_OFFSET && native_code_map[chunk].offsets[offset] != EXTENSION_WORD) {
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3041 code_info code;
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3042 code.cur = native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3043 code.last = code.cur + 32;
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3044 code.stack_off = 0;
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3045 mov_ir(&code, chunk * NATIVE_CHUNK_SIZE + offset, opts->gen.scratch1, SZ_D);
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3046 call(&code, opts->retrans_stub);
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3047 }
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3048 }
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3049 }
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3050 }
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3051 }
5c8b1c33ca10 Invalidate translated code on a cartridge bank change in SMS mode. Fix handling of bank 0
Michael Pavone <pavone@retrodev.com>
parents: 1131
diff changeset
3052
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3053 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3054 {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3055 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3056 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3057 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3058 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3059 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3060 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3061 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3062 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3063 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3064 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3065
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3066 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3067 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3068 z80_options * opts = context->options;
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3069 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3070 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3071 translate_z80_stream(context, opts->gen.deferred->address);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3072 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3073 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3074
559
6b248602ab84 blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3075 extern void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) asm("z80_retranslate_inst");
390
561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents: 389
diff changeset
3076 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start)
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3077 {
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3078 char disbuf[80];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3079 z80_options * opts = context->options;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3080 uint8_t orig_size = z80_get_native_inst_size(opts, address);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3081 code_info *code = &opts->gen.code;
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3082 uint8_t *after, *inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3083 z80inst instbuf;
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
3084 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3085 after = z80_decode(inst, &instbuf);
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
3086 #ifdef DO_DEBUG_PRINT
314
54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents: 313
diff changeset
3087 z80_disasm(&instbuf, disbuf, address);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3088 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3089 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3090 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3091 printf("%X\t%s\n", address, disbuf);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
3092 }
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
3093 #endif
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3094 if (orig_size != ZMAX_NATIVE_SIZE) {
597
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents: 594
diff changeset
3095 check_alloc_code(code, ZMAX_NATIVE_SIZE);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3096 code_ptr start = code->cur;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3097 deferred_addr * orig_deferred = opts->gen.deferred;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3098 translate_z80inst(&instbuf, context, address, 0);
644
2d7e84ae818c Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one
Michael Pavone <pavone@retrodev.com>
parents: 628
diff changeset
3099 /*
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3100 if ((native_end - dst) <= orig_size) {
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3101 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3102 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3103 remove_deferred_until(&opts->gen.deferred, orig_deferred);
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
3104 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0);
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3105 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3106 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3107 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3108 }
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3109 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3110 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3111 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3112 z80_handle_deferred(context);
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3113 return orig_start;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3114 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3115 }*/
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3116 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3117 code_info tmp_code = {orig_start, orig_start + 16};
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3118 jmp(&tmp_code, start);
597
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents: 594
diff changeset
3119 tmp_code = *code;
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents: 594
diff changeset
3120 code->cur = start + ZMAX_NATIVE_SIZE;
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
3121 if (!z80_is_terminal(&instbuf)) {
597
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents: 594
diff changeset
3122 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst));
264
8fd6652e56f8 Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents: 262
diff changeset
3123 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3124 z80_handle_deferred(context);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3125 return start;
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3126 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3127 code_info tmp_code = *code;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3128 code->cur = orig_start;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3129 code->last = orig_start + ZMAX_NATIVE_SIZE;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3130 translate_z80inst(&instbuf, context, address, 0);
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
3131 code_info tmp2 = *code;
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
3132 *code = tmp_code;
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
3133 if (!z80_is_terminal(&instbuf)) {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3134
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
3135 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst));
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3136 }
266
376df762ddf5 Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 264
diff changeset
3137 z80_handle_deferred(context);
252
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3138 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents: 250
diff changeset
3139 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3140 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3141
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3142 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3143 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3144 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3145 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3146 return;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3147 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3148 z80_options * opts = context->options;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3149 uint32_t start_address = address;
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
3150
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3151 do
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3152 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3153 z80inst inst;
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
3154 dprintf("translating Z80 code at address %X\n", address);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3155 do {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3156 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3157 if (existing) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3158 jmp(&opts->gen.code, existing);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3159 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3160 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3161 uint8_t * encoded, *next;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3162 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3163 if (!encoded) {
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3164 code_info stub = z80_make_interp_stub(context, address);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3165 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3166 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3167 }
601
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
3168 //make sure prologue is in a contiguous chunk of code
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents: 598
diff changeset
3169 check_code_prologue(&opts->gen.code);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3170 next = z80_decode(encoded, &inst);
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
3171 #ifdef DO_DEBUG_PRINT
314
54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents: 313
diff changeset
3172 z80_disasm(&inst, disbuf, address);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3173 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3174 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3175 } else {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3176 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3177 }
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
3178 #endif
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3179 code_ptr start = opts->gen.code.cur;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3180 translate_z80inst(&inst, context, address, 0);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3181 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3182 address += next-encoded;
255
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents: 254
diff changeset
3183 address &= 0xFFFF;
283
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents: 282
diff changeset
3184 } while (!z80_is_terminal(&inst));
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3185 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3186 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3187 address = opts->gen.deferred->address;
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
3188 dprintf("defferred address: %X\n", address);
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
3189 }
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3190 } while (opts->gen.deferred);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3191 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3192
1116
fe8c79f82c22 More cleanup in preparation for SMS/Mark III support
Michael Pavone <pavone@retrodev.com>
parents: 1110
diff changeset
3193 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider, uint32_t io_address_mask)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3194 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3195 memset(options, 0, sizeof(*options));
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3196
653
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3197 options->gen.memmap = chunks;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
3198 options->gen.memmap_chunks = num_chunks;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3199 options->gen.address_size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3200 options->gen.address_mask = 0xFFFF;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3201 options->gen.max_address = 0x10000;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3202 options->gen.bus_cycles = 3;
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
3203 options->gen.clock_divider = clock_divider;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3204 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3205 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags);
620
9d6fed6501ba Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.
Michael Pavone <pavone@retrodev.com>
parents: 601
diff changeset
3206 options->gen.ram_flags_shift = 7;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3207
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3208 options->flags = 0;
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3209 #ifdef X86_64
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3210 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3211 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3212 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3213 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3214 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3215 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3216 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3217 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3218 options->regs[Z80_IYH] = -1;
239
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents: 238
diff changeset
3219 options->regs[Z80_IYL] = R8;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3220 options->regs[Z80_I] = -1;
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3221 options->regs[Z80_R] = RDI;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3222 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3223 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3224 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3225 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3226 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3227 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3228 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3229 options->regs[Z80_IY] = R8;
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
3230
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3231 options->gen.scratch1 = R13;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3232 options->gen.scratch2 = R14;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3233 #else
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3234 memset(options->regs, -1, sizeof(options->regs));
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3235 options->regs[Z80_A] = RAX;
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3236 options->regs[Z80_R] = AH;
1048
05ecef6c73b6 More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents: 1047
diff changeset
3237 options->regs[Z80_H] = BH;
05ecef6c73b6 More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents: 1047
diff changeset
3238 options->regs[Z80_L] = RBX;
05ecef6c73b6 More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents: 1047
diff changeset
3239 options->regs[Z80_HL] = RBX;
05ecef6c73b6 More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents: 1047
diff changeset
3240
05ecef6c73b6 More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents: 1047
diff changeset
3241 options->regs[Z80_SP] = RDI;
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
3242
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3243 options->gen.scratch1 = RCX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3244 options->gen.scratch2 = RDX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
3245 #endif
667
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents: 666
diff changeset
3246
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3247 options->gen.context_reg = RSI;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3248 options->gen.cycles = RBP;
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3249 options->gen.limit = -1;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3250
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3251 options->gen.native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3252 memset(options->gen.native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3253 options->gen.deferred = NULL;
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3254 uint32_t inst_size_size = sizeof(uint8_t *) * ram_size(&options->gen) / 1024;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3255 options->gen.ram_inst_sizes = malloc(inst_size_size);
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3256 memset(options->gen.ram_inst_sizes, 0, inst_size_size);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3257
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3258 code_info *code = &options->gen.code;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3259 init_code_info(code);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3260
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3261 options->save_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3262 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3263 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3264
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3265 options->gen.save_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3266 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3267 {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3268 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3269 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3270 if (i < Z80_I) {
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3271 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3272 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3273 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3274 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3275 size = SZ_B;
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3276 }
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3277 if (reg == Z80_R) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3278 and_ir(code, 0x7F, options->regs[Z80_R], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3279 or_rrdisp(code, options->regs[Z80_R], options->gen.context_reg, zr_off(Z80_R), SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3280 } else if (options->regs[reg] >= 0) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3281 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, zr_off(reg), size);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3282 }
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3283 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3284 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3285 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3286 }
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3287 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3288 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3289 }
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3290 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3291 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3292 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3293 retn(code);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3294
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3295 options->load_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3296 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3297 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3298 options->gen.load_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3299 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3300 {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3301 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3302 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3303 if (i < Z80_I) {
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3304 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3305 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3306 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3307 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3308 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3309 }
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3310 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3311 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size);
1225
197cb199a35b Fix loading of the R register from the in memory context
Michael Pavone <pavone@retrodev.com>
parents: 1224
diff changeset
3312 if (reg == Z80_R) {
197cb199a35b Fix loading of the R register from the in memory context
Michael Pavone <pavone@retrodev.com>
parents: 1224
diff changeset
3313 and_irdisp(code, 0x80, options->gen.context_reg, zr_off(reg), SZ_B);
197cb199a35b Fix loading of the R register from the in memory context
Michael Pavone <pavone@retrodev.com>
parents: 1224
diff changeset
3314 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3315 }
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3316 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3317 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3318 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3319 }
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3320 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3321 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3322 }
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3323 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3324 sub_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3325 retn(code);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3326
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3327 options->native_addr = code->cur;
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3328 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3329 push_r(code, options->gen.context_reg);
657
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
3330 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D);
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
3331 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3332 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3333 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3334 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3335 retn(code);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3336
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3337 uint32_t tmp_stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3338
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3339 options->gen.handle_cycle_limit = code->cur;
900
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3340 //calculate call/stack adjust size
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3341 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3342 call_noalign(code, options->gen.handle_cycle_limit);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3343 uint32_t call_adjust_size = code->cur - options->gen.handle_cycle_limit;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3344 code->cur = options->gen.handle_cycle_limit;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3345
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3346 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3347 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3348 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3349 code_ptr no_sync = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3350 jcc(code, CC_B, no_sync);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3351 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3352 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3353 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3354 call(code, options->save_context_scratch);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3355 tmp_stack_off = code->stack_off;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3356 pop_r(code, RAX); //return address in read/write func
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3357 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3358 pop_r(code, RBX); //return address in translated code
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3359 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
900
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3360 sub_ir(code, call_adjust_size, RAX, SZ_PTR); //adjust return address to point to the call + stack adjust that got us here
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3361 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3362 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
665
d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents: 664
diff changeset
3363 restore_callee_save_regs(code);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3364 //return to caller of z80_run
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3365 retn(code);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3366
598
faad1927d836 Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80
Michael Pavone <pavone@retrodev.com>
parents: 597
diff changeset
3367 *no_sync = code->cur - (no_sync + 1);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3368 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3369 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3370 retn(code);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3371 code->stack_off = tmp_stack_off;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3372
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3373 options->gen.handle_code_write = (code_ptr)z80_handle_code_write;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3374
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3375 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3376 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3377
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3378 code_ptr skip_int = code->cur;
900
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3379 //calculate adjust size
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3380 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3381 uint32_t adjust_size = code->cur - skip_int;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3382 code->cur = skip_int;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3383
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3384 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3385 code_ptr skip_sync = code->cur + 1;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3386 jcc(code, CC_B, skip_sync);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3387 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3388 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3389 //save PC
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3390 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, pc), SZ_D);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3391 options->do_sync = code->cur;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3392 call(code, options->gen.save_context);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3393 tmp_stack_off = code->stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3394 //pop return address off the stack and save for resume later
898
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
3395 //pop_rind(code, options->gen.context_reg);
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
3396 pop_r(code, RAX);
900
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents: 899
diff changeset
3397 add_ir(code, adjust_size, RAX, SZ_PTR);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3398 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
898
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
3399 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
3400
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3401 //restore callee saved registers
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3402 restore_callee_save_regs(code);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3403 //return to caller of z80_run
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3404 retn(code);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3405 *skip_sync = code->cur - (skip_sync+1);
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3406 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3407 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3408 retn(code);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3409 code->stack_off = tmp_stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3410
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3411 options->gen.handle_cycle_limit_int = code->cur;
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3412 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3413 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3414 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3415 jcc(code, CC_B, skip_int);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3416 //set limit to the cycle limit
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3417 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.scratch2, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3418 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3419 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3420 add_rr(code, options->gen.scratch2, options->gen.cycles, SZ_D);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3421 //disable interrupts
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3422 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, int_is_nmi), SZ_B);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3423 code_ptr is_nmi = code->cur + 1;
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3424 jcc(code, CC_NZ, is_nmi);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3425 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
3426 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
1761
873a1330c3a9 Fix cycle counts of a few instructions in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1592
diff changeset
3427 cycles(&options->gen, 6); //interupt ack cycle
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3428 code_ptr after_int_disable = code->cur + 1;
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3429 jmp(code, after_int_disable);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3430 *is_nmi = code->cur - (is_nmi + 1);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3431 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, iff1), options->gen.scratch2, SZ_B);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3432 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3433 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
1761
873a1330c3a9 Fix cycle counts of a few instructions in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1592
diff changeset
3434 cycles(&options->gen, 5); //NMI processing cycles
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3435 *after_int_disable = code->cur - (after_int_disable + 1);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3436 //save return address (in scratch1) to Z80 stack
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3437 sub_ir(code, 2, options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3438 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3439 //we need to do check_cycles and cycles outside of the write_8 call
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3440 //so that the stack has the correct depth if we need to return to C
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3441 //for a synchronization
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3442 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3443 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3444 //save word to write before call to write_8_noinc
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3445 push_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3446 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3447 //restore word to write
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3448 pop_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3449 //write high byte to SP+1
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3450 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3451 add_ir(code, 1, options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3452 shr_ir(code, 8, options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3453 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3454 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3455 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3456 //dispose of return address as we'll be jumping somewhere else
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3457 add_ir(code, 16, RSP, SZ_PTR);
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3458 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, int_is_nmi), SZ_B);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3459 is_nmi = code->cur + 1;
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3460 jcc(code, CC_NZ, is_nmi);
1471
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3461 //TODO: Support interrupt mode 0, not needed for Genesis sit it seems to read $FF during intack
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3462 //which is conveniently rst $38, i.e. the same thing that im 1 does
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3463 //check interrupt mode
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3464 cmp_irdisp(code, 2, options->gen.context_reg, offsetof(z80_context, im), SZ_B);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3465 code_ptr im2 = code->cur + 1;
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3466 jcc(code, CC_Z, im2);
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
3467 mov_ir(code, 0x38, options->gen.scratch1, SZ_W);
1761
873a1330c3a9 Fix cycle counts of a few instructions in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1592
diff changeset
3468 cycles(&options->gen, 1); //total time for mode 0/1 is 13 t-states
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3469 code_ptr after_int_dest = code->cur + 1;
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3470 jmp(code, after_int_dest);
1471
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3471 *im2 = code->cur - (im2 + 1);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3472 //read vector address from I << 8 | vector
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3473 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + Z80_I, options->gen.scratch1, SZ_B);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3474 shl_ir(code, 8, options->gen.scratch1, SZ_W);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3475 movzx_rdispr(code, options->gen.context_reg, offsetof(z80_context, im2_vector), options->gen.scratch2, SZ_B, SZ_W);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3476 or_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_W);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3477 push_r(code, options->gen.scratch1);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3478 cycles(&options->gen, 3);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3479 call(code, options->read_8_noinc);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3480 pop_r(code, options->gen.scratch2);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3481 push_r(code, options->gen.scratch1);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3482 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_W);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3483 add_ir(code, 1, options->gen.scratch1, SZ_W);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3484 cycles(&options->gen, 3);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3485 call(code, options->read_8_noinc);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3486 pop_r(code, options->gen.scratch2);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3487 shl_ir(code, 8, options->gen.scratch1, SZ_W);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3488 movzx_rr(code, options->gen.scratch2, options->gen.scratch2, SZ_B, SZ_W);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3489 or_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_W);
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3490 code_ptr after_int_dest2 = code->cur + 1;
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3491 jmp(code, after_int_dest2);
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3492 *is_nmi = code->cur - (is_nmi + 1);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3493 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, int_is_nmi), SZ_B);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3494 mov_irdisp(code, CYCLE_NEVER, options->gen.context_reg, offsetof(z80_context, nmi_start), SZ_D);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3495 mov_ir(code, 0x66, options->gen.scratch1, SZ_W);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3496 *after_int_dest = code->cur - (after_int_dest + 1);
1471
2e6320d261ff Implemented Z80 IM 2 and attempted correct intack cycle delay
Michael Pavone <pavone@retrodev.com>
parents: 1448
diff changeset
3497 *after_int_dest2 = code->cur - (after_int_dest2 + 1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3498 call(code, options->native_addr);
663
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents: 662
diff changeset
3499 mov_rrind(code, options->gen.scratch1, options->gen.context_reg, SZ_PTR);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3500 tmp_stack_off = code->stack_off;
665
d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents: 664
diff changeset
3501 restore_callee_save_regs(code);
663
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents: 662
diff changeset
3502 //return to caller of z80_run to sync
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents: 662
diff changeset
3503 retn(code);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3504 code->stack_off = tmp_stack_off;
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3505
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3506 //HACK
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3507 options->gen.address_size = SZ_D;
1116
fe8c79f82c22 More cleanup in preparation for SMS/Mark III support
Michael Pavone <pavone@retrodev.com>
parents: 1110
diff changeset
3508 options->gen.address_mask = io_address_mask;
1761
873a1330c3a9 Fix cycle counts of a few instructions in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1592
diff changeset
3509 options->gen.bus_cycles = 4;
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3510 options->read_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, READ_8, NULL);
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3511 options->write_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, WRITE_8, NULL);
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3512 options->gen.address_size = SZ_W;
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3513 options->gen.address_mask = 0xFFFF;
1761
873a1330c3a9 Fix cycle counts of a few instructions in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1592
diff changeset
3514 options->gen.bus_cycles = 3;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3515
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3516 options->read_16 = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3517 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3518 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3519 //TODO: figure out how to handle the extra wait state for word reads to bank area
657
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
3520 //may also need special handling to avoid too much stack depth when access is blocked
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3521 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3522 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3523 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
3524 #ifndef X86_64
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
3525 //scratch 2 is a caller save register in 32-bit builds and may be clobbered by something called from the read8 fun
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
3526 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
3527 #endif
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3528 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3529 add_ir(code, 1, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3530 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3531 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3532 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3533 shl_ir(code, 8, options->gen.scratch1, SZ_W);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
3534 #ifdef X86_64
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3535 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
3536 #else
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
3537 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
3538 #endif
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3539 retn(code);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3540
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3541 options->write_16_highfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3542 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3543 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3544 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3545 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3546 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3547 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3548 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3549 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3550 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3551 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3552 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3553 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3554 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3555 retn(code);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3556
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3557 options->write_16_lowfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3558 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3559 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3560 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3561 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3562 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3563 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3564 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3565 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3566 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3567 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3568 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3569 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3570 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3571 retn(code);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3572
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3573 options->retrans_stub = code->cur;
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3574 tmp_stack_off = code->stack_off;
899
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3575 //calculate size of patch
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3576 mov_ir(code, 0x7FFF, options->gen.scratch1, SZ_D);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3577 code->stack_off += sizeof(void *);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3578 if (code->stack_off & 0xF) {
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3579 sub_ir(code, 16 - (code->stack_off & 0xF), RSP, SZ_PTR);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3580 }
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3581 call_noalign(code, options->retrans_stub);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3582 uint32_t patch_size = code->cur - options->retrans_stub;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3583 code->cur = options->retrans_stub;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3584 code->stack_off = tmp_stack_off;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3585
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3586 //pop return address
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3587 pop_r(code, options->gen.scratch2);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3588 add_ir(code, 16-sizeof(void*), RSP, SZ_PTR);
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3589 code->stack_off = tmp_stack_off;
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3590 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3591 //adjust pointer before move and call instructions that got us here
899
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents: 898
diff changeset
3592 sub_ir(code, patch_size, options->gen.scratch2, SZ_PTR);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3593 push_r(code, options->gen.context_reg);
657
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
3594 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3595 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3596 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3597 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3598 jmp_r(code, options->gen.scratch1);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3599
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3600 options->run = (z80_ctx_fun)code->cur;
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3601 tmp_stack_off = code->stack_off;
665
d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents: 664
diff changeset
3602 save_callee_save_regs(code);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
3603 #ifdef X86_64
1828
37afb9cf58be Get 64-bit builds working for Windows target
Michael Pavone <pavone@retrodev.com>
parents: 1767
diff changeset
3604 mov_rr(code, FIRST_ARG_REG, options->gen.context_reg, SZ_PTR);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
3605 #else
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
3606 mov_rdispr(code, RSP, 5 * sizeof(int32_t), options->gen.context_reg, SZ_PTR);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
3607 #endif
594
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents: 593
diff changeset
3608 call(code, options->load_context_scratch);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3609 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3610 code_ptr no_extra = code->cur+1;
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3611 jcc(code, CC_Z, no_extra);
898
2f1157f00dc6 Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents: 895
diff changeset
3612 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3613 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc));
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3614 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3615 *no_extra = code->cur - (no_extra + 1);
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
3616 jmp_rind(code, options->gen.context_reg);
895
13388ab6d78a Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents: 894
diff changeset
3617 code->stack_off = tmp_stack_off;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3618 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3619
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3620 z80_context *init_z80_context(z80_options * options)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3621 {
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3622 size_t ctx_size = sizeof(z80_context) + ram_size(&options->gen) / (1 << options->gen.ram_flags_shift) / 8;
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3623 z80_context *context = calloc(1, ctx_size);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3624 context->options = options;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3625 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3626 context->int_pulse_start = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3627 context->int_pulse_end = CYCLE_NEVER;
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3628 context->nmi_start = CYCLE_NEVER;
1130
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3629
8f14767661fa Remove memory map assumptions from Z80 core and move a little bit of logic to the generic backend.c so it can be shared between CPU cores
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3630 return context;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3631 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3632
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3633 static void check_nmi(z80_context *context)
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3634 {
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3635 if (context->nmi_start < context->int_cycle) {
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3636 context->int_cycle = context->nmi_start;
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3637 context->int_is_nmi = 1;
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3638 }
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3639 }
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3640
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3641 void z80_run(z80_context * context, uint32_t target_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3642 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3643 if (context->reset || context->busack) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3644 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3645 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3646 if (context->current_cycle < target_cycle) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3647 //busreq is sampled at the end of an m-cycle
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3648 //we can approximate that by running for a single m-cycle after a bus request
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3649 context->sync_cycle = context->busreq ? context->current_cycle + 3*context->options->gen.clock_divider : target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3650 if (!context->native_pc) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3651 context->native_pc = z80_get_native_address_trans(context, context->pc);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3652 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3653 while (context->current_cycle < context->sync_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3654 {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1116
diff changeset
3655 if (context->next_int_pulse && (context->int_pulse_end < context->current_cycle || context->int_pulse_end == CYCLE_NEVER)) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1116
diff changeset
3656 context->next_int_pulse(context);
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3657 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3658 if (context->iff1) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3659 context->int_cycle = context->int_pulse_start < context->int_enable_cycle ? context->int_enable_cycle : context->int_pulse_start;
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3660 context->int_is_nmi = 0;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3661 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3662 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3663 }
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3664 check_nmi(context);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3665
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3666 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
670
f4f3e74b0ce6 Restore Z80 interrupt pulse duration and make a small improvement to debug print output
Michael Pavone <pavone@retrodev.com>
parents: 668
diff changeset
3667 dprintf("Running Z80 from cycle %d to cycle %d. Int cycle: %d (%d - %d)\n", context->current_cycle, context->sync_cycle, context->int_cycle, context->int_pulse_start, context->int_pulse_end);
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3668 context->options->run(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3669 dprintf("Z80 ran to cycle %d\n", context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3670 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3671 if (context->busreq) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3672 context->busack = 1;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3673 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3674 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3675 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3676 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3677 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3678
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
3679 void z80_options_free(z80_options *opts)
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
3680 {
1592
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3681 for (uint32_t address = 0; address < opts->gen.address_mask; address += NATIVE_CHUNK_SIZE)
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3682 {
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3683 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3684 if (opts->gen.native_code_map[chunk].base) {
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3685 free(opts->gen.native_code_map[chunk].offsets);
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3686 }
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3687 }
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
3688 free(opts->gen.native_code_map);
1592
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3689 uint32_t ram_inst_slots = ram_size(&opts->gen) / 1024;
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3690 for (uint32_t i = 0; i < ram_inst_slots; i++)
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3691 {
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3692 free(opts->gen.ram_inst_sizes[i]);
31effaadf877 Fix some memory errors (mostly leaks) identified by valgrind
Michael Pavone <pavone@retrodev.com>
parents: 1561
diff changeset
3693 }
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
3694 free(opts->gen.ram_inst_sizes);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
3695 free(opts);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
3696 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 854
diff changeset
3697
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3698 void z80_assert_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3699 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3700 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3701 context->reset = 1;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3702 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3703
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3704 void z80_clear_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3705 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3706 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3707 if (context->reset) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3708 //TODO: Handle case where reset is not asserted long enough
701
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents: 697
diff changeset
3709 context->im = 0;
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents: 697
diff changeset
3710 context->iff1 = context->iff2 = 0;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3711 context->native_pc = NULL;
701
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents: 697
diff changeset
3712 context->extra_pc = NULL;
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3713 context->pc = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3714 context->reset = 0;
676
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents: 670
diff changeset
3715 if (context->busreq) {
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents: 670
diff changeset
3716 //TODO: Figure out appropriate delay
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents: 670
diff changeset
3717 context->busack = 1;
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents: 670
diff changeset
3718 }
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3719 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3720 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3721
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3722 void z80_assert_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3723 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3724 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3725 context->busreq = 1;
854
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3726 //this is an imperfect aproximation since most M-cycles take less tstates than the max
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3727 //and a short 3-tstate m-cycle can take an unbounded number due to wait states
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3728 if (context->current_cycle - cycle > MAX_MCYCLE_LENGTH * context->options->gen.clock_divider) {
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3729 context->busack = 1;
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents: 844
diff changeset
3730 }
701
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents: 697
diff changeset
3731 }
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3732
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3733 void z80_clear_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3734 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3735 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3736 context->busreq = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3737 context->busack = 0;
844
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 842
diff changeset
3738 //there appears to be at least a 1 Z80 cycle delay between busreq
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 842
diff changeset
3739 //being released and resumption of execution
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 842
diff changeset
3740 context->current_cycle += context->options->gen.clock_divider;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3741 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3742
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3743 uint8_t z80_get_busack(z80_context * context, uint32_t cycle)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3744 {
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3745 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3746 return context->busack;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3747 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3748
1376
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3749 void z80_assert_nmi(z80_context *context, uint32_t cycle)
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3750 {
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3751 context->nmi_start = cycle;
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3752 check_nmi(context);
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3753 }
70d88d9bfe13 Implemented Z80 NMI
Michael Pavone <pavone@retrodev.com>
parents: 1260
diff changeset
3754
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3755 void z80_adjust_cycles(z80_context * context, uint32_t deduction)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3756 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3757 if (context->current_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3758 fprintf(stderr, "WARNING: Deduction of %u cycles when Z80 cycle counter is only %u\n", deduction, context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3759 context->current_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3760 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3761 context->current_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3762 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3763 if (context->int_enable_cycle != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3764 if (context->int_enable_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3765 context->int_enable_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3766 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3767 context->int_enable_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3768 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3769 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3770 if (context->int_pulse_start != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3771 if (context->int_pulse_end < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3772 context->int_pulse_start = context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3773 } else {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1116
diff changeset
3774 if (context->int_pulse_end != CYCLE_NEVER) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1116
diff changeset
3775 context->int_pulse_end -= deduction;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1116
diff changeset
3776 }
668
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3777 if (context->int_pulse_start < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3778 context->int_pulse_start = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3779 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3780 context->int_pulse_start -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3781 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3782 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents: 667
diff changeset
3783 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3784 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3785
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3786 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst)
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3787 {
1131
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3788 code_info code = {
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3789 dst,
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3790 dst+32,
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3791 #ifdef X86_64
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3792 8
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3793 #else
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3794 0
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3795 #endif
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3796 };
659
759c38bf97f8 Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents: 657
diff changeset
3797 mov_ir(&code, address, context->options->gen.scratch1, SZ_W);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3798 call(&code, context->bp_stub);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3799 return code.cur-dst;
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3800 }
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3801
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3802 void zcreate_stub(z80_context * context)
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3803 {
1224
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3804 //FIXME: Stack offset stuff is probably broken on 32-bit
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3805 z80_options * opts = context->options;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3806 code_info *code = &opts->gen.code;
894
a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
3807 uint32_t start_stack_off = code->stack_off;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3808 check_code_prologue(code);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3809 context->bp_stub = code->cur;
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3810
1131
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3811 //Calculate length of prologue
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3812 check_cycles_int(&opts->gen, 0);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3813 int check_int_size = code->cur-context->bp_stub;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3814 code->cur = context->bp_stub;
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3815
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3816 //Calculate length of patch
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3817 int patch_size = zbreakpoint_patch(context, 0, code->cur);
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3818
1131
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3819 #ifdef X86_64
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3820 code->stack_off = 8;
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3821 #endif
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3822 //Save context and call breakpoint handler
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3823 call(code, opts->gen.save_context);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3824 push_r(code, opts->gen.scratch1);
657
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 653
diff changeset
3825 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1);
664
bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents: 663
diff changeset
3826 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR);
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
3827 //Restore context
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3828 call(code, opts->gen.load_context);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3829 pop_r(code, opts->gen.scratch1);
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
3830 //do prologue stuff
1131
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3831 cmp_ir(code, 1, opts->gen.cycles, SZ_D);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3832 uint8_t * jmp_off = code->cur+1;
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
3833 jcc(code, CC_NS, code->cur + 7);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3834 pop_r(code, opts->gen.scratch1);
664
bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents: 663
diff changeset
3835 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
1224
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3836 #ifdef X86_64
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3837 sub_ir(code, 8, RSP, SZ_PTR);
15c5be05e6a9 Ported correct but inefficient overlapping instruction handling from 68K core to Z80 core. Fixed remaining stack alignment issue for Z80 breakpoints on 64-bit. Probably still needs fixing for 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 1222
diff changeset
3838 #endif
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3839 push_r(code, opts->gen.scratch1);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3840 jmp(code, opts->gen.handle_cycle_limit_int);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3841 *jmp_off = code->cur - (jmp_off+1);
682
Michael Pavone <pavone@retrodev.com>
parents: 676 559
diff changeset
3842 //jump back to body of translated instruction
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3843 pop_r(code, opts->gen.scratch1);
664
bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents: 663
diff changeset
3844 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3845 jmp_r(code, opts->gen.scratch1);
894
a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
3846 code->stack_off = start_stack_off;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3847 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3848
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3849 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler)
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3850 {
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3851 context->bp_handler = bp_handler;
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3852 uint8_t bit = 1 << (address % 8);
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3853 if (!(bit & context->breakpoint_flags[address / 8])) {
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3854 context->breakpoint_flags[address / 8] |= bit;
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3855 if (!context->bp_stub) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3856 zcreate_stub(context);
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3857 }
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3858 uint8_t * native = z80_get_native_address(context, address);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3859 if (native) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3860 zbreakpoint_patch(context, address, native);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3861 }
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3862 }
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3863 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
3864
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3865 void zremove_breakpoint(z80_context * context, uint16_t address)
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3866 {
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
3867 context->breakpoint_flags[address / 8] &= ~(1 << (address % 8));
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3868 uint8_t * native = z80_get_native_address(context, address);
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
3869 if (native) {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3870 z80_options * opts = context->options;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3871 code_info tmp_code = opts->gen.code;
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3872 opts->gen.code.cur = native;
1131
136b1676109b Partial fix for Z80 debugger brokeness introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents: 1130
diff changeset
3873 opts->gen.code.last = native + 128;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3874 check_cycles_int(&opts->gen, address);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
3875 opts->gen.code = tmp_code;
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
3876 }
366
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3877 }
836585d389b8 Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents: 363
diff changeset
3878
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3879 void z80_serialize(z80_context *context, serialize_buffer *buf)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3880 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3881 for (int i = 0; i <= Z80_A; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3882 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3883 save_int8(buf, context->regs[i]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3884 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3885 uint8_t f = context->flags[ZF_S];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3886 f <<= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3887 f |= context->flags[ZF_Z] ;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3888 f <<= 2;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3889 f |= context->flags[ZF_H];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3890 f <<= 2;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3891 f |= context->flags[ZF_PV];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3892 f <<= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3893 f |= context->flags[ZF_N];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3894 f <<= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3895 f |= context->flags[ZF_C];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3896 f |= context->flags[ZF_XY] & 0x28;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3897 save_int8(buf, f);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3898 for (int i = 0; i <= Z80_A; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3899 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3900 save_int8(buf, context->alt_regs[i]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3901 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3902 f = context->alt_flags[ZF_S];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3903 f <<= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3904 f |= context->alt_flags[ZF_Z] ;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3905 f <<= 2;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3906 f |= context->alt_flags[ZF_H];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3907 f <<= 2;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3908 f |= context->alt_flags[ZF_PV];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3909 f <<= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3910 f |= context->alt_flags[ZF_N];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3911 f <<= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3912 f |= context->alt_flags[ZF_C];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3913 f |= context->flags[ZF_XY] & 0x28;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3914 save_int8(buf, f);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3915 save_int16(buf, context->pc);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3916 save_int16(buf, context->sp);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3917 save_int8(buf, context->im);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3918 save_int8(buf, context->iff1);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3919 save_int8(buf, context->iff2);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3920 save_int8(buf, context->int_is_nmi);
1440
7d4483944d4d Allow actually saving a save state in more Z80 states. Save busreq/reset state in bus arbiter section for "native" save states
Michael Pavone <pavone@retrodev.com>
parents: 1433
diff changeset
3921 save_int8(buf, context->busack);
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3922 save_int32(buf, context->current_cycle);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3923 save_int32(buf, context->int_cycle);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3924 save_int32(buf, context->int_enable_cycle);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3925 save_int32(buf, context->int_pulse_start);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3926 save_int32(buf, context->int_pulse_end);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3927 save_int32(buf, context->nmi_start);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3928 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3929
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3930 void z80_deserialize(deserialize_buffer *buf, void *vcontext)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3931 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3932 z80_context *context = vcontext;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3933 for (int i = 0; i <= Z80_A; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3934 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3935 context->regs[i] = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3936 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3937 uint8_t f = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3938 context->flags[ZF_XY] = f & 0x28;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3939 context->flags[ZF_C] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3940 f >>= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3941 context->flags[ZF_N] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3942 f >>= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3943 context->flags[ZF_PV] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3944 f >>= 2;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3945 context->flags[ZF_H] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3946 f >>= 2;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3947 context->flags[ZF_Z] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3948 f >>= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3949 context->flags[ZF_S] = f;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3950 for (int i = 0; i <= Z80_A; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3951 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3952 context->alt_regs[i] = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3953 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3954 f = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3955 context->alt_flags[ZF_XY] = f & 0x28;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3956 context->alt_flags[ZF_C] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3957 f >>= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3958 context->alt_flags[ZF_N] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3959 f >>= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3960 context->alt_flags[ZF_PV] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3961 f >>= 2;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3962 context->alt_flags[ZF_H] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3963 f >>= 2;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3964 context->alt_flags[ZF_Z] = f & 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3965 f >>= 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3966 context->alt_flags[ZF_S] = f;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3967 context->pc = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3968 context->sp = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3969 context->im = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3970 context->iff1 = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3971 context->iff2 = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3972 context->int_is_nmi = load_int8(buf);
1440
7d4483944d4d Allow actually saving a save state in more Z80 states. Save busreq/reset state in bus arbiter section for "native" save states
Michael Pavone <pavone@retrodev.com>
parents: 1433
diff changeset
3973 context->busack = load_int8(buf);
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3974 context->current_cycle = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3975 context->int_cycle = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3976 context->int_enable_cycle = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3977 context->int_pulse_start = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3978 context->int_pulse_end = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3979 context->nmi_start = load_int32(buf);
1448
9327c1dc3791 Ensure extra_pc is NULL when resuming a save state
Michael Pavone <pavone@retrodev.com>
parents: 1440
diff changeset
3980 context->native_pc = context->extra_pc = NULL;
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3981 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1376
diff changeset
3982