repos/blastem: vdp.c annotate

annotate vdp.c @ 1299:da1ffc4026c4

Fix latching of V32 mode bit

author	Michael Pavone <pavone@retrodev.com>
date	Sat, 25 Mar 2017 11:31:43 -0700
parents	aa1a8eb5bb2b
children	810ae0287d66

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	2 Copyright 2013 Michael Pavone
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	5 */
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "vdp.h"
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	7 #include "blastem.h"
1103 22e87b739ad6 WIP split of ROM loading/argument parsing from Genesis emulation code. Compiles and doesn't crash, but nothing works. Still a few too many globals as well. Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	8 #include "genesis.h"
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #include <stdlib.h>
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 #include <string.h>
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	11 #include "render.h"
991 f9ee6f746cb4 Properly emulate machine freeze when reading from VDP while configured for writes Michael Pavone <pavone@retrodev.com> parents: 984 diff changeset	12 #include "util.h"
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	13
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	14 #define NTSC_INACTIVE_START 224
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	15 #define PAL_INACTIVE_START 240
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	16 #define MODE4_INACTIVE_START 192
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define BUF_BIT_PRIORITY 0x40
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define MAP_BIT_PRIORITY 0x8000
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define MAP_BIT_H_FLIP 0x800
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define MAP_BIT_V_FLIP 0x1000
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	21
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	22 #define SCROLL_BUFFER_SIZE 32
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	23 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	24 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	25
328 bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	26 #define MCLKS_SLOT_H40 16
bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	27 #define MCLKS_SLOT_H32 20
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	28 #define VINT_SLOT_H40 0 //21 slots before HSYNC, 16 during, 10 after
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	29 #define VINT_SLOT_H32 0 //old value was 23, but recent tests suggest the actual value is close to the H40 one
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	30 #define VINT_SLOT_MODE4 4
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	31 #define HSYNC_SLOT_H40 230
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	32 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17)
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	33 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	34 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	35 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	36 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	37 #define LINE_CHANGE_H40 165
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	38 #define LINE_CHANGE_H32 133
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	39 #define LINE_CHANGE_MODE4 249
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	40 #define VBLANK_START_H40 (LINE_CHANGE_H40+2)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	41 #define VBLANK_START_H32 (LINE_CHANGE_H32+2)
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	42 #define FIFO_LATENCY 3
328 bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	43
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	44 #define BORDER_TOP_V24 27
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	45 #define BORDER_TOP_V28 11
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	46 #define BORDER_TOP_V24_PAL 54
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	47 #define BORDER_TOP_V28_PAL 38
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	48 #define BORDER_TOP_V30_PAL 30
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	49
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	50 #define BORDER_BOT_V24 24
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	51 #define BORDER_BOT_V28 8
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	52 #define BORDER_BOT_V24_PAL 48
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	53 #define BORDER_BOT_V28_PAL 32
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	54 #define BORDER_BOT_V30_PAL 24
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	55
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	56 #define INVALID_LINE 0x200
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	57
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	58 static int32_t color_map[1 << 12];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	59 static uint16_t mode4_address_map[0x4000];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	60 static uint32_t planar_to_chunky[256];
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	61 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	62
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	63 static uint8_t debug_base[][3] = {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	64 {127, 127, 127}, //BG
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	65 {0, 0, 127}, //A
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	66 {127, 0, 0}, //Window
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	67 {0, 127, 0}, //B
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	68 {127, 0, 127} //Sprites
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	69 };
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	70
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	71 static void update_video_params(vdp_context *context)
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	72 {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	73 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	74 if (context->latched_mode & BIT_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	75 if (context->flags2 & FLAG2_REGION_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	76 context->inactive_start = PAL_INACTIVE_START;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	77 context->border_top = BORDER_TOP_V30_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	78 context->border_bot = BORDER_BOT_V30_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	79 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	80 context->inactive_start = 0x200;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	81 context->border_top = context->border_bot = 0;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	82 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	83 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	84 context->inactive_start = NTSC_INACTIVE_START;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	85 if (context->flags2 & FLAG2_REGION_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	86 context->border_top = BORDER_TOP_V28_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	87 context->border_bot = BORDER_BOT_V28_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	88 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	89 context->border_top = BORDER_TOP_V28;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	90 context->border_bot = BORDER_TOP_V28;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	91 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	92 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	93 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	94 context->inactive_start = MODE4_INACTIVE_START;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	95 if (context->flags2 & FLAG2_REGION_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	96 context->border_top = BORDER_TOP_V24_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	97 context->border_bot = BORDER_BOT_V24_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	98 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	99 context->border_top = BORDER_TOP_V24;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	100 context->border_bot = BORDER_BOT_V24;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	101 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	102 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	103 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	104
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	105 static uint8_t color_map_init_done;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	106
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	107 void init_vdp_context(vdp_context * context, uint8_t region_pal)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 {
58 a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs. Mike Pavone <pavone@retrodev.com> parents: 56 diff changeset	109 memset(context, 0, sizeof(*context));
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	110 context->vdpmem = malloc(VRAM_SIZE);
58 a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs. Mike Pavone <pavone@retrodev.com> parents: 56 diff changeset	111 memset(context->vdpmem, 0, VRAM_SIZE);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	112 /*
488 32f053ad9b02 Basic OpenGL rendering is working Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	113 */
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	114 if (headless) {
1168 fa73a77ddf92 Fix benchmark mode Michael Pavone <pavone@retrodev.com> parents: 1167 diff changeset	115 context->output = malloc(LINEBUF_SIZE * sizeof(uint32_t));
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	116 context->output_pitch = 0;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	117 } else {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	118 context->fb = render_get_framebuffer(FRAMEBUFFER_ODD, &context->output_pitch);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	119 }
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	120 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	121 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	122 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE;
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	123 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE;
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	124 context->sprite_draws = MAX_DRAWS;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	125 context->fifo_write = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	126 context->fifo_read = -1;
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	127 context->regs[REG_HINT] = context->hint_counter = 0xFF;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	128
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	129 if (!color_map_init_done) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	130 uint8_t b,g,r;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	131 for (uint16_t color = 0; color < (1 << 12); color++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	132 if (color & FBUF_SHADOW) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	133 b = levels[(color >> 9) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	134 g = levels[(color >> 5) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	135 r = levels[(color >> 1) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	136 } else if(color & FBUF_HILIGHT) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	137 b = levels[((color >> 9) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	138 g = levels[((color >> 5) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	139 r = levels[((color >> 1) & 0x7) + 7];
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	140 } else if(color & FBUF_MODE4) {
1127 cb4771f4543a Fix Mode 4 color mapping Michael Pavone <pavone@retrodev.com> parents: 1125 diff changeset	141 b = levels[(color >> 4 & 0xC) \| (color >> 6 & 0x2)];
1125 fba485949723 Brighten up Mode 4 colors Michael Pavone <pavone@retrodev.com> parents: 1124 diff changeset	142 g = levels[(color >> 2 & 0x8) \| (color >> 1 & 0x4) \| (color >> 4 & 0x2)];
fba485949723 Brighten up Mode 4 colors Michael Pavone <pavone@retrodev.com> parents: 1124 diff changeset	143 r = levels[(color << 1 & 0xC) \| (color >> 1 & 0x2)];
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	144 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	145 b = levels[(color >> 8) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	146 g = levels[(color >> 4) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	147 r = levels[color & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	148 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	149 color_map[color] = render_map_color(r, g, b);
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	150 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	151 for (uint16_t mode4_addr = 0; mode4_addr < 0x4000; mode4_addr++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	152 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	153 uint16_t mode5_addr = mode4_addr & 0x3DFD;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	154 mode5_addr \|= mode4_addr << 8 & 0x200;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	155 mode5_addr \|= mode4_addr >> 8 & 2;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	156 mode4_address_map[mode4_addr] = mode5_addr;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	157 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	158 for (uint32_t planar = 0; planar < 256; planar++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	159 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	160 uint32_t chunky = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	161 for (int bit = 7; bit >= 0; bit--)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	162 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	163 chunky = chunky << 4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	164 chunky \|= planar >> bit & 1;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	165 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	166 planar_to_chunky[planar] = chunky;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	167 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	168 color_map_init_done = 1;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	169 }
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	170 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++)
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	171 {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	172 uint8_t src = color & DBG_SRC_MASK;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	173 if (src > DBG_SRC_S) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	174 context->debugcolors[color] = 0;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	175 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	176 uint8_t r,g,b;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	177 b = debug_base[src][0];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	178 g = debug_base[src][1];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	179 r = debug_base[src][2];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	180 if (color & DBG_PRIORITY)
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	181 {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	182 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	183 b += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	184 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	185 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	186 g += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	187 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	188 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	189 r += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	190 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	191 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	192 if (color & DBG_SHADOW) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	193 b /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	194 g /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	195 r /=2 ;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	196 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	197 if (color & DBG_HILIGHT) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	198 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	199 b += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	200 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	201 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	202 g += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	203 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	204 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	205 r += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	206 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	207 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	208 context->debugcolors[color] = render_map_color(r, g, b);
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	209 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	210 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	211 if (region_pal) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	212 context->flags2 \|= FLAG2_REGION_PAL;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	213 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	214 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	215 if (!headless) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	216 context->output = (uint32_t )(((char )context->fb) + context->output_pitch * context->border_top);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	217 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	219
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	220 void vdp_free(vdp_context *context)
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	221 {
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	222 free(context->vdpmem);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	223 free(context->linebuf);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	224 free(context);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	225 }
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	226
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	227 static int is_refresh(vdp_context * context, uint32_t slot)
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	228 {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	229 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	230 return slot == 250 \|\| slot == 26 \|\| slot == 59 \|\| slot == 90 \|\| slot == 122 \|\| slot == 154;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	231 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	232 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	233 //These numbers are guesses based on H40 numbers
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	234 return slot == 243 \|\| slot == 19 \|\| slot == 51 \|\| slot == 83 \|\| slot == 115;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	235 //The numbers below are the refresh slots during active display
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	236 //return (slot == 29 \|\| slot == 61 \|\| slot == 93 \|\| slot == 125);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	237 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	238 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	239
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	240 static void increment_address(vdp_context *context)
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	241 {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	242 context->address += context->regs[REG_AUTOINC];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	243 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	244 context->address++;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	245 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	246 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	247
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	248 static void render_sprite_cells(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 {
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	250 if (context->cur_slot >= context->sprite_draws) {
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	251 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	252
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	255 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 }
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	262 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	263 context->cur_slot--;
143 e5487ef04619 Fix infinite loop bug in sprite rendering Mike Pavone <pavone@retrodev.com> parents: 142 diff changeset	264 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
1029 4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	265 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	266 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	267 context->linebuf[x] = (context->vdpmem[address] >> 4) \| d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	268 } else if (context->vdpmem[address] >> 4) {
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	269 context->flags2 \|= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	270 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 x += dir;
1029 4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	273 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	274 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	275 context->linebuf[x] = (context->vdpmem[address] & 0xF) \| d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	276 } else if (context->vdpmem[address] & 0xF) {
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	277 context->flags2 \|= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	278 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	279 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	280 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	284
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	285 static void fetch_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	286 {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	287 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	288 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	289 uint32_t address = mode4_address_map[d->address & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	290 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	291 context->fetch_tmp[1] = context->vdpmem[address + 1];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	292 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	293 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	294
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	295 static void render_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	296 {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	297 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	298 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	299 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	300 pixels \|= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	301 uint32_t address = mode4_address_map[(d->address + 2) & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	302 pixels \|= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	303 pixels \|= planar_to_chunky[context->vdpmem[address + 1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	304 int x = d->x_pos & 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	305 for (int i = 28; i >= 0; i -= 4, x++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	306 {
1155 da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	307 if (context->linebuf[x] && (pixels >> i & 0xF)) {
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	308 if (
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	309 ((context->regs[REG_MODE_1] & BIT_SPRITE_8PX) && x > 8)
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	310 \|\| ((!(context->regs[REG_MODE_1] & BIT_SPRITE_8PX)) && x < 256)
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	311 ) {
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	312 context->flags2 \|= FLAG2_SPRITE_COLLIDE;
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	313 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	314 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	315 context->linebuf[x] = pixels >> i & 0xF;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	316 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	317 }
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	318 context->sprite_index--;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	319 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	320 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	321
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	322 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	323 {
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	324 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	325 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	326 uint16_t current_index = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	327 uint8_t count = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	328 do {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	329 uint16_t address = current_index * 8 + sat_address;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	330 uint16_t cache_address = current_index * 4;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	331 uint8_t height = ((context->sat_cache[cache_address+2] & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	332 uint8_t width = (((context->sat_cache[cache_address+2] >> 2) & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	333 int16_t y = ((context->sat_cache[cache_address] & 0x3) << 8 \| context->sat_cache[cache_address+1]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	334 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 \| context->vdpmem[address + 7]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	335 uint16_t link = context->sat_cache[cache_address+3] & 0x7F;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	336 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	337 uint8_t pri = context->vdpmem[address + 4] >> 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	338 uint16_t pattern = ((context->vdpmem[address + 4] << 8 \| context->vdpmem[address + 5]) & 0x7FF) << 5;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	339 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	340 current_index = link;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	341 count++;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	342 } while (current_index != 0 && count < 80);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	343 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	344 uint16_t sat_address = (context->regs[REG_SAT] & 0x7E) << 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	345 for (int i = 0; i < 64; i++)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	346 {
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	347 uint8_t y = context->vdpmem[mode4_address_map[sat_address + (i ^ 1)]];
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	348 if (y == 0xD0) {
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	349 break;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	350 }
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	351 uint8_t x = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2 + 1]];
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	352 uint16_t tile_address = context->vdpmem[mode4_address_map[sat_address + 0x80 + i2]] 32
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	353 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	354 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	355 tile_address &= ~32;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	356 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	357 printf("Sprite %d: X=%d, Y=%d, Pat=%X\n", i, x, y, tile_address);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	358 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	359 }
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	360 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	361
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	362 #define VRAM_READ 0 //0000
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	363 #define VRAM_WRITE 1 //0001
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	364 //2 would trigger register write 0010
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	365 #define CRAM_WRITE 3 //0011
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	366 #define VSRAM_READ 4 //0100
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	367 #define VSRAM_WRITE 5//0101
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	368 //6 would trigger regsiter write 0110
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	369 //7 is a mystery //0111
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	370 #define CRAM_READ 8 //1000
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	371 //9 is also a mystery //1001
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	372 //A would trigger register write 1010
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	373 //B is a mystery 1011
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	374 #define VRAM_READ8 0xC //1100
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	375 //D is a mystery 1101
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	376 //E would trigger register write 1110
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	377 //F is a mystery 1111
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	378
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	379 //Possible theory on how bits work
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	380 //CD0 = Read/Write flag
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	381 //CD2,(CD1\|CD3) = RAM type
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	382 // 00 = VRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	383 // 01 = CRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	384 // 10 = VSRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	385 // 11 = VRAM8
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	386 //Would result in
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	387 // 7 = VRAM8 write
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	388 // 9 = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	389 // B = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	390 // D = VRAM8 write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	391 // F = VRAM8 write alais
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	392
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	393 #define DMA_START 0x20
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	394
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	395 static const char * cd_name(uint8_t cd)
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	396 {
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	397 switch (cd & 0xF)
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	398 {
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	399 case VRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	400 return "VRAM read";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	401 case VRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	402 return "VRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	403 case CRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	404 return "CRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	405 case VSRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	406 return "VSRAM read";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	407 case VSRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	408 return "VSRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	409 case VRAM_READ8:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	410 return "VRAM read (undocumented 8-bit mode)";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	411 default:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	412 return "invalid";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	413 }
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	414 }
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	415
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	416 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	417 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	418 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	419 printf("Mode Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	420 "00: %.2X \| H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	421 "01: %.2X \| Display %s, V-ints %s, Height: %d, Mode %d\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	422 "0B: %.2X \| E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	423 "0C: %.2X \| Width: %d, Shadow/Highlight: %s\n",
757 483f7e7926a6 More clang warning cleanup Michael Pavone <pavone@retrodev.com> parents: 748 diff changeset	424 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", (context->regs[REG_MODE_1] & BIT_PAL_SEL) != 0,
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	425 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	426 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	427 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4,
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	428 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	429 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	430 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	431 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	432 printf("\nTable Group\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	433 "02: %.2X \| Scroll A Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	434 "03: %.2X \| Window Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	435 "04: %.2X \| Scroll B Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	436 "05: %.2X \| Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	437 "0D: %.2X \| HScroll Data Table: $%.4X\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	438 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	439 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	440 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	441 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x7E : 0x7F)) << 9,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	442 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	443 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	444 printf("\nTable Group\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	445 "02: %.2X \| Background Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	446 "05: %.2X \| Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	447 "06: %.2X \| Sprite Tile Base: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	448 "08: %.2X \| Background X Scroll: %d\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	449 "09: %.2X \| Background Y Scroll: %d\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	450 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0xE) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	451 context->regs[REG_SAT], (context->regs[REG_SAT] & 0x7E) << 7,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	452 context->regs[REG_STILE_BASE], (context->regs[REG_STILE_BASE] & 2) << 11,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	453 context->regs[REG_X_SCROLL], context->regs[REG_X_SCROLL],
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	454 context->regs[REG_Y_SCROLL], context->regs[REG_Y_SCROLL]);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	455
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	456 }
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	457 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	458 printf("\nMisc Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	459 "07: %.2X \| Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	460 "0A: %.2X \| H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	461 "0F: %.2X \| Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	462 "10: %.2X \| Scroll A/B Size: %sx%s\n",
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	463 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR],
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	464 context->regs[REG_HINT], context->regs[REG_HINT],
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	465 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	466 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
621 5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	467 char * src_types[] = {"68K", "68K", "Copy", "Fill"};
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	468 printf("\nDMA Group\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	469 "13: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	470 "14: %.2X \| DMA Length: $%.4X words\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	471 "15: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	472 "16: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	473 "17: %.2X \| DMA Source Address: $%.6X, Type: %s\n",
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	474 context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	475 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 \| context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	476 context->regs[REG_DMASRC_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	477 context->regs[REG_DMASRC_M],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	478 context->regs[REG_DMASRC_H],
629 9089951a1994 Small fix to display of DMA source address in vr debug command Michael Pavone <pavone@retrodev.com> parents: 624 diff changeset	479 context->regs[REG_DMASRC_H] << 17 \| context->regs[REG_DMASRC_M] << 9 \| context->regs[REG_DMASRC_L] << 1,
621 5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	480 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]);
438 b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	481 printf("\nInternal Group\n"
b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	482 "Address: %X\n"
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	483 "CD: %X - %s\n"
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	484 "Pending: %s\n"
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	485 "VCounter: %d\n"
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	486 "HCounter: %d\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	487 "VINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	488 "HINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	489 "Status: %X\n",
1150 322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode Michael Pavone <pavone@retrodev.com> parents: 1149 diff changeset	490 context->address, context->cd, cd_name(context->cd),
322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode Michael Pavone <pavone@retrodev.com> parents: 1149 diff changeset	491 (context->flags & FLAG_PENDING) ? "word" : (context->flags2 & FLAG2_BYTE_PENDING) ? "byte" : "none",
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	492 context->vcounter, context->hslot*2, (context->flags2 & FLAG2_VINT_PENDING) ? "true" : "false",
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	493 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context));
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	494
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	495 //TODO: Window Group, DMA Group
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	496 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	497
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	498 static void scan_sprite_table(uint32_t line, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	499 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	500 if (context->sprite_index && context->slot_counter) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	501 line += 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	502 line &= 0xFF;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	503 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	504 uint8_t height_mult;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	505 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	506 line *= 2;
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	507 if (context->flags2 & FLAG2_EVEN_FIELD) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	508 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	509 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	510 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	511 ymin = 256;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	512 height_mult = 16;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	513 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	514 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	515 ymin = 128;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	516 height_mult = 8;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	517 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	518 context->sprite_index &= 0x7F;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	519 if (context->regs[REG_MODE_4] & BIT_H40) {
38 898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	520 if (context->sprite_index >= MAX_SPRITES_FRAME) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	521 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	522 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	523 }
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	524 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	525 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	526 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	527 }
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	528 uint16_t address = context->sprite_index * 4;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	529 line += ymin;
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	530 uint16_t y = ((context->sat_cache[address] & 0x3) << 8 \| context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	531 uint8_t height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	532 //printf("Sprite %d \| y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	533 if (y <= line && line < (y + height)) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	534 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	535 context->sprite_info_list[--(context->slot_counter)].size = context->sat_cache[address+2];
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	536 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	537 context->sprite_info_list[context->slot_counter].y = y-ymin;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	538 }
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	539 context->sprite_index = context->sat_cache[address+3] & 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	540 if (context->sprite_index && context->slot_counter)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	541 {
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	542 if (context->regs[REG_MODE_4] & BIT_H40) {
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	543 if (context->sprite_index >= MAX_SPRITES_FRAME) {
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	544 context->sprite_index = 0;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	545 return;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	546 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	547 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) {
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	548 context->sprite_index = 0;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	549 return;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	550 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	551 address = context->sprite_index * 4;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	552 y = ((context->sat_cache[address] & 0x3) << 8 \| context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	553 height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	554 //printf("Sprite %d \| y: %d, height: %d\n", context->sprite_index, y, height);
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	555 if (y <= line && line < (y + height)) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	556 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	557 context->sprite_info_list[--(context->slot_counter)].size = context->sat_cache[address+2];
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	558 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	559 context->sprite_info_list[context->slot_counter].y = y-ymin;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	560 }
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	561 context->sprite_index = context->sat_cache[address+3] & 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	562 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	563 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	564 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	565
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	566 static void scan_sprite_table_mode4(vdp_context * context)
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	567 {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	568 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	569 uint32_t line = context->vcounter;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	570 line &= 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	571
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	572 uint32_t sat_address = mode4_address_map[(context->regs[REG_SAT] << 7 & 0x3F00) + context->sprite_index];
1138 25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping Michael Pavone <pavone@retrodev.com> parents: 1137 diff changeset	573 uint32_t y = context->vdpmem[sat_address+1];
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	574 uint32_t size = (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) ? 16 : 8;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	575
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	576 if (y == 0xd0) {
1122 d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	577 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	578 return;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	579 } else {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	580 if (y <= line && line < (y + size)) {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	581 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	582 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	583 context->flags \|= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	584 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	585 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	586 context->sprite_info_list[--(context->slot_counter)].size = size;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	587 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	588 context->sprite_info_list[context->slot_counter].y = y;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	589 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	590 context->sprite_index++;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	591 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	592
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	593 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1138 25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping Michael Pavone <pavone@retrodev.com> parents: 1137 diff changeset	594 y = context->vdpmem[sat_address];
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	595 if (y == 0xd0) {
1122 d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	596 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	597 return;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	598 } else {
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	599 if (y <= line && line < (y + size)) {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	600 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	601 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	602 context->flags \|= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	603 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	604 }
1122 d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	605 context->sprite_info_list[--(context->slot_counter)].size = size;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	606 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	607 context->sprite_info_list[context->slot_counter].y = y;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	608 }
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	609 context->sprite_index++;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	610 }
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	611 }
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	612
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	613 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	614 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	615
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	616 static void read_sprite_x(uint32_t line, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	617 {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	618 if (context->cur_slot >= context->slot_counter) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	619 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	620 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	621 line &= 0xFF;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	622 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	623 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	624 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	625 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	626 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	627 line *= 2;
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	628 if (context->flags2 & FLAG2_EVEN_FIELD) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	629 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	630 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	631 height *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	632 }
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	633 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	634 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) \| context->vdpmem[att_addr+1];
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	635 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	636 uint8_t row;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	637 if (tileinfo & MAP_BIT_V_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	638 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	639 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	640 row = line-context->sprite_info_list[context->cur_slot].y;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	641 }
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	642 uint16_t address;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	643 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	644 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	645 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	646 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	647 }
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	648 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 \| context->vdpmem[att_addr + 3]) & 0x1FF;
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	649 if (x) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	650 context->flags \|= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	651 } else if(context->flags & (FLAG_CAN_MASK \| FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	652 context->flags \|= FLAG_MASKED;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	653 }
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	654
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	655 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	656 int16_t i;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	657 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	658 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	659 --context->sprite_draws;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	660 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	661 }
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	662 } else {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	663 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	664 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	665 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	666 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	667 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	668 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	669 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	670 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	671 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	672 //printf("Sprite %d \| x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35 233c7737c152 Small fix to overflow flag Mike Pavone <pavone@retrodev.com> parents: 34 diff changeset	673 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	674 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	675 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	676 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	677 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	678 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	679 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	680 }
1000 1a797fcbb35f Added TODO for hardware checking Michael Pavone <pavone@retrodev.com> parents: 999 diff changeset	681 //Used to be i < width
1a797fcbb35f Added TODO for hardware checking Michael Pavone <pavone@retrodev.com> parents: 999 diff changeset	682 //TODO: Confirm this is the right condition on hardware
1a797fcbb35f Added TODO for hardware checking Michael Pavone <pavone@retrodev.com> parents: 999 diff changeset	683 if (!context->sprite_draws) {
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	684 context->flags \|= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	685 }
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	686 context->cur_slot--;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	687 } else {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	688 context->flags \|= FLAG_DOT_OFLOW;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	689 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	690 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	691 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	692
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	693 static void read_sprite_x_mode4(vdp_context * context)
427 2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	694 {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	695 if (context->cur_slot >= context->slot_counter) {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	696 uint32_t address = (context->regs[REG_SAT] << 7 & 0x3F00) + 0x80 + context->sprite_info_list[context->cur_slot].index * 2;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	697 address = mode4_address_map[address];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	698 --context->sprite_draws;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	699 uint32_t tile_address = context->vdpmem[address] * 32 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	700 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	701 tile_address &= ~32;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	702 }
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	703 tile_address += (context->vcounter - context->sprite_info_list[context->cur_slot].y)* 4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	704 context->sprite_draw_list[context->sprite_draws].x_pos = context->vdpmem[address + 1];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	705 context->sprite_draw_list[context->sprite_draws].address = tile_address;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	706 context->cur_slot--;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	707 }
427 2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	708 }
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	709
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	710 #define CRAM_BITS 0xEEE
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	711 #define VSRAM_BITS 0x7FF
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	712 #define VSRAM_DIRTY_BITS 0xF800
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	713
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	714 //rough estimate of slot number at which border display starts
1270 687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	715 #define BG_START_SLOT 6
1183 8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	716
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	717 void write_cram(vdp_context * context, uint16_t address, uint16_t value)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	718 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	719 uint16_t addr;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	720 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	721 addr = (address/2) & (CRAM_SIZE-1);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	722 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	723 addr = address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	724 value = (value << 1 & 0xE) \| (value << 2 & 0xE0) \| (value & 0xE00);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	725 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	726 context->cram[addr] = value;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	727 context->colors[addr] = color_map[value & CRAM_BITS];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	728 context->colors[addr + CRAM_SIZE] = color_map[(value & CRAM_BITS) \| FBUF_SHADOW];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	729 context->colors[addr + CRAM_SIZE*2] = color_map[(value & CRAM_BITS) \| FBUF_HILIGHT];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	730 context->colors[addr + CRAM_SIZE*3] = color_map[(value & CRAM_BITS) \| FBUF_MODE4];
1183 8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	731
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	732 if (context->hslot >= BG_START_SLOT && (
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	733 context->vcounter < context->inactive_start + context->border_bot
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	734 \|\| context->vcounter > 0x200 - context->border_top
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	735 )) {
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	736 uint8_t bg_end_slot = BG_START_SLOT + (context->regs[REG_MODE_4] & BIT_H40) ? LINEBUF_SIZE/2 : (256+HORIZ_BORDER)/2;
1183 8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	737 if (context->hslot < bg_end_slot) {
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	738 uint32_t color = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->colors[addr] : context->colors[addr + CRAM_SIZE*3];
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	739 context->output[(context->hslot - BG_START_SLOT)*2 + 1] = color;
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	740 }
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	741 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	742 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	743
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	744 static void vdp_advance_dma(vdp_context * context)
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	745 {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	746 context->regs[REG_DMASRC_L] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	747 if (!context->regs[REG_DMASRC_L]) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	748 context->regs[REG_DMASRC_M] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	749 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	750 context->address += context->regs[REG_AUTOINC];
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	751 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L]) - 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	752 context->regs[REG_DMALEN_H] = dma_len >> 8;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	753 context->regs[REG_DMALEN_L] = dma_len;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	754 if (!dma_len) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	755 context->flags &= ~FLAG_DMA_RUN;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	756 context->cd &= 0xF;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	757 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	758 }
1019 e34334e6c682 Fix GST savestate loading to deal with SAT cache to fix sprite corruption on savestate load. Clear out Z80 native_pc so the Z80 state does not get hosed when loading a savestate while the emulator is already running Michael Pavone <pavone@retrodev.com> parents: 1001 diff changeset	759
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	760 void write_vram_byte(vdp_context *context, uint16_t address, uint8_t value)
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	761 {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	762 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	763 if (!(address & 4)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	764 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	765 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	766 uint16_t cache_address = address - sat_address;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	767 cache_address = (cache_address & 3) \| (cache_address >> 1 & 0x1FC);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	768 context->sat_cache[cache_address] = value;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	769 }
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	770 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	771 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	772 address = mode4_address_map[address & 0x3FFF];
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	773 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	774 context->vdpmem[address] = value;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	775 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	776
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	777 static void external_slot(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	778 {
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	779 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && context->fifo_read < 0) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	780 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	781 fifo_entry * cur = context->fifo + context->fifo_read;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	782 cur->cycle = context->cycles;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	783 cur->address = context->address;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	784 cur->partial = 2;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	785 vdp_advance_dma(context);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	786 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	787 fifo_entry * start = context->fifo + context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	788 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	789 switch (start->cd & 0xF)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	790 {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	791 case VRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	792 if (start->partial) {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	793 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	794 write_vram_byte(context, start->address ^ 1, start->partial == 2 ? start->value >> 8 : start->value);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	795 } else {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	796 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	797 write_vram_byte(context, start->address, start->value >> 8);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	798 start->partial = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	799 //skip auto-increment and removal of entry from fifo
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	800 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	801 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	802 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	803 case CRAM_WRITE: {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	804 //printf("CRAM Write \| %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	805 if (start->partial == 1) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	806 uint16_t val;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	807 if ((start->address & 1) && (context->regs[REG_MODE_2] & BIT_MODE_5)) {
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	808 val = (context->cram[start->address >> 1 & (CRAM_SIZE-1)] & 0xFF) \| start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	809 } else {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	810 uint16_t address = (context->regs[REG_MODE_2] & BIT_MODE_5) ? start->address >> 1 & (CRAM_SIZE-1) : start->address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	811 val = (context->cram[address] & 0xFF00) \| start->value;
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	812 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	813 write_cram(context, start->address, val);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	814 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	815 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	816 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	817 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	818 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	819 case VSRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	820 if (((start->address/2) & 63) < VSRAM_SIZE) {
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	821 //printf("VSRAM Write: %X to %X @ vcounter: %d, hslot: %d, cycle: %d\n", start->value, context->address, context->vcounter, context->hslot, context->cycles);
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	822 if (start->partial == 1) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	823 if (start->address & 1) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	824 context->vsram[(start->address/2) & 63] &= 0xFF;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	825 context->vsram[(start->address/2) & 63] \|= start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	826 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	827 context->vsram[(start->address/2) & 63] &= 0xFF00;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	828 context->vsram[(start->address/2) & 63] \|= start->value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	829 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	830 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	831 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	832 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	833 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	834
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	835 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	836 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	837 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	838 if (context->fifo_read == context->fifo_write) {
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	839 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	840 context->flags \|= FLAG_DMA_RUN;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	841 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	842 context->fifo_read = -1;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	843 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	844 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	845 if (context->flags & FLAG_READ_FETCHED) {
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	846 write_vram_byte(context, context->address ^ 1, context->prefetch);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	847
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	848 //Update DMA state
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	849 vdp_advance_dma(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	850
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	851 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	852 } else {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	853 context->prefetch = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L] ^ 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	854
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	855 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	856 }
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	857 } else if (!(context->cd & 1) && !(context->flags & (FLAG_READ_FETCHED\|FLAG_PENDING))) {
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	858 switch(context->cd & 0xF)
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	859 {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	860 case VRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	861 if (context->flags2 & FLAG2_READ_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	862 context->prefetch \|= context->vdpmem[context->address \| 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	863 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	864 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	865 //Should this happen after the prefetch or after the read?
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	866 increment_address(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	867 } else {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	868 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	869 context->flags2 \|= FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	870 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	871 break;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	872 case VRAM_READ8: {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	873 uint32_t address = context->address ^ 1;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	874 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	875 address = mode4_address_map[address & 0x3FFF];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	876 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	877 context->prefetch = context->vdpmem[address];
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	878 context->prefetch \|= context->fifo[context->fifo_write].value & 0xFF00;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	879 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	880 //Should this happen after the prefetch or after the read?
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	881 increment_address(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	882 break;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	883 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	884 case CRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	885 context->prefetch = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	886 context->prefetch \|= context->fifo[context->fifo_write].value & ~CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	887 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	888 //Should this happen after the prefetch or after the read?
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	889 increment_address(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	890 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	891 case VSRAM_READ: {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	892 uint16_t address = (context->address /2) & 63;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	893 if (address >= VSRAM_SIZE) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	894 address = 0;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	895 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	896 context->prefetch = context->vsram[address] & VSRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	897 context->prefetch \|= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	898 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	899 //Should this happen after the prefetch or after the read?
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	900 increment_address(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	901 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	902 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	903 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	904 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	905 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	906
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	907 static void run_dma_src(vdp_context * context, int32_t slot)
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	908 {
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	909 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	910 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	911 if (context->fifo_write == context->fifo_read) {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	912 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	913 }
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	914 fifo_entry * cur = NULL;
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	915 if (!(context->regs[REG_DMASRC_H] & 0x80))
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	916 {
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	917 //68K -> VDP
924 1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period Michael Pavone <pavone@retrodev.com> parents: 923 diff changeset	918 if (slot == -1 \|\| !is_refresh(context, slot-1)) {
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	919 cur = context->fifo + context->fifo_write;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	920 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	921 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	922 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) \| (context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	923 cur->cd = context->cd;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	924 cur->partial = 0;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	925 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	926 context->fifo_read = context->fifo_write;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	927 }
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	928 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	929 vdp_advance_dma(context);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	930 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	931 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	932 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	933
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	934 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	935 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	936
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	937 static void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	938 {
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	939 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	940 if (context->double_res) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	941 line *= 2;
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	942 if (context->flags2 & FLAG2_EVEN_FIELD) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	943 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	944 }
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	945 window_line_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	946 v_offset_mask = 0xF;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	947 vscroll_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	948 } else {
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	949 window_line_shift = 3;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	950 v_offset_mask = 0x7;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	951 vscroll_shift = 3;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	952 }
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	953 if (!vsram_off) {
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	954 uint16_t left_col, right_col;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	955 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
920 e64168bb2b25 Fix calculation of window start column when it's on the right side. This removes graphical glitches in Afterburner 2, Fireshark and Dungeons and Dragons: Warriors of the Eternal Sun and probably others Michael Pavone <pavone@retrodev.com> parents: 884 diff changeset	956 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2 + 2;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	957 right_col = 42;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	958 } else {
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	959 left_col = 0;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	960 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	961 if (right_col) {
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	962 right_col += 2;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	963 }
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	964 }
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	965 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	966 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	967 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	968 bottom_line = context->double_res ? 481 : 241;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	969 } else {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	970 top_line = 0;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	971 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	972 }
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	973 if ((column >= left_col && column < right_col) \|\| (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	974 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	975 uint16_t line_offset, offset, mask;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	976 if (context->regs[REG_MODE_4] & BIT_H40) {
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	977 address &= 0xF000;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	978 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	979 mask = 0x7F;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	980
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	981 } else {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	982 address &= 0xF800;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	983 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	984 mask = 0x3F;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	985 }
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	986 if (context->double_res) {
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	987 mask <<= 1;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	988 mask \|= 1;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	989 }
42 6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane. Mike Pavone <pavone@retrodev.com> parents: 41 diff changeset	990 offset = address + line_offset + (((column - 2) * 2) & mask);
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	991 context->col_1 = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	992 //printf("Window \| top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42 6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane. Mike Pavone <pavone@retrodev.com> parents: 41 diff changeset	993 offset = address + line_offset + (((column - 1) * 2) & mask);
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	994 context->col_2 = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	995 context->v_offset = (line) & v_offset_mask;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	996 context->flags \|= FLAG_WINDOW;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	997 return;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	998 }
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	999 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1000 }
1290 aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk Michael Pavone <pavone@retrodev.com> parents: 1289 diff changeset	1001 //TODO: Verify behavior for 0x20 case
aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk Michael Pavone <pavone@retrodev.com> parents: 1289 diff changeset	1002 uint16_t vscroll = 0xFF \| (context->regs[REG_SCROLL] & 0x30) << 4;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1003 if (context->double_res) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1004 vscroll <<= 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1005 vscroll \|= 1;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1006 }
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1007 //TODO: Further research on vscroll latch behavior and the "first column bug"
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1008 if (!column) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1009 if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1010 if (context->regs[REG_MODE_4] & BIT_H40) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1011 //Based on observed behavior documented by Eke-Eke, I'm guessing the VDP
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1012 //ends up fetching the last value on the VSRAM bus in the H40 case
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1013 //getting the last latched value should be close enough for now
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1014 if (!vsram_off) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1015 context->vscroll_latch[0] = context->vscroll_latch[1];
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1016 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1017 } else {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1018 //supposedly it's always forced to 0 in the H32 case
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1019 context->vscroll_latch[0] = context->vscroll_latch[1] = 0;
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1020 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1021 } else {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1022 context->vscroll_latch[vsram_off] = context->vsram[vsram_off];
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1023 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1024 } else if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
710 4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	1025 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off];
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	1026 }
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	1027 vscroll &= context->vscroll_latch[vsram_off] + line;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1028 context->v_offset = vscroll & v_offset_mask;
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	1029 //printf("%s \| line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1030 vscroll >>= vscroll_shift;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1031 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1032 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1033 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1034 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1035 case 0:
108 1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1036 hscroll_mask = 0x1F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1037 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1038 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1039 case 0x1:
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	1040 hscroll_mask = 0x3F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1041 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1042 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1043 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1044 //TODO: Verify this behavior
1290 aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk Michael Pavone <pavone@retrodev.com> parents: 1289 diff changeset	1045 hscroll_mask = 0x5F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1046 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1047 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1048 case 0x3:
108 1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1049 hscroll_mask = 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1050 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1051 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1052 }
28 037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1053 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1054 for (int i = 0; i < 2; i++) {
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	1055 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	1056 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	1057 //printf("%s \| line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28 037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1058 uint16_t col_val = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1059 if (i) {
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1060 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1061 } else {
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1062 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1063 }
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1064 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1065 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1066
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1067 static void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1068 {
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	1069 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1070 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1071
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1072 static void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1073 {
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	1074 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1075 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1076
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1077 static void read_map_mode4(uint16_t column, uint32_t line, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1078 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1079 uint32_t address = (context->regs[REG_SCROLL_A] & 0xE) << 10;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1080 //add row
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1081 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1082 if (column < 24 \|\| !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1083 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1084 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1085 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1086 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1087 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1088 address += (vscroll >> 3) * 2 * 32;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1089 //add column
1136 52f25c41abdd Fix horizontal scrolling in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1135 diff changeset	1090 address += ((column - (context->hscroll_a >> 3)) & 31) * 2;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1091 //adjust for weird VRAM mapping in Mode 4
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1092 address = mode4_address_map[address];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1093 context->col_1 = (context->vdpmem[address] << 8) \| context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1094 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1095
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1096 static void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1097 {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1098 uint16_t address;
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1099 uint16_t vflip_base;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1100 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1101 address = ((col & 0x3FF) << 6);
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1102 vflip_base = 60;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1103 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1104 address = ((col & 0x7FF) << 5);
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1105 vflip_base = 28;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1106 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1107 if (col & MAP_BIT_V_FLIP) {
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1108 address += vflip_base - 4 * context->v_offset;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1109 } else {
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1110 address += 4 * context->v_offset;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1111 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1112 uint16_t pal_priority = (col >> 9) & 0x70;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1113 int32_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1114 if (col & MAP_BIT_H_FLIP) {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1115 offset += 7;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1116 offset &= SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1117 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1118 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1119 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1120 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1121 for (uint32_t i=0; i < 4; i++, address++)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1122 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1123 tmp_buf[offset] = pal_priority \| (context->vdpmem[address] >> 4);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1124 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1125 offset &= SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1126 tmp_buf[offset] = pal_priority \| (context->vdpmem[address] & 0xF);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1127 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1128 offset &= SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1129 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1130 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1131
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1132 static void render_map_1(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1133 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1134 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1135 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1136
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1137 static void render_map_2(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1138 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1139 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1140 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1141
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1142 static void render_map_3(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1143 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1144 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1145 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1146
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1147 static void fetch_map_mode4(uint16_t col, uint32_t line, vdp_context *context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1148 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1149 //calculate pixel row to fetch
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1150 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1151 if (col < 24 \|\| !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1152 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1153 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1154 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1155 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1156 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1157 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1158 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1159 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1160 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1161
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1162 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1163 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1164 context->fetch_tmp[1] = context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1165 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1166
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1167 static void render_map_output(uint32_t line, int32_t col, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1168 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1169 uint32_t *dst;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1170 if (line == 0x1FF) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1171 if (!col) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1172 return;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1173 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1174 col -= 2;
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1175 if (col) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1176 dst = context->output + BORDER_LEFT + col * 8;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1177 } else {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1178 dst = context->output;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1179 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1180 for (int i = 0; i < BORDER_LEFT; i++, dst++)
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1181 {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1182 *dst = bg_color;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1183 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1184 }
1170 9170fc4d9835 Don't adjust cycles every frame. Only when we start getting close to UINT_MAX. Don't adjust all the way down to zero when we do adjust. Shouldn't fix anything, but may make debugging current issues easier. Michael Pavone <pavone@retrodev.com> parents: 1169 diff changeset	1185 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1186 for (int i = 0; i < 16; i++)
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1187 {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1188 *(dst++) = color;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1189 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1190 return;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1191 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1192 if (line >= 240) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1193 return;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1194 }
1180 e2b81a0f8fd8 Undo poorly thought out minor optimization that screwed up rendering Michael Pavone <pavone@retrodev.com> parents: 1179 diff changeset	1195 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1196 uint8_t sprite_buf, plane_a, *plane_b;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1197 int plane_a_off, plane_b_off;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1198 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1199 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1200 col-=2;
1270 687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1201 if (col) {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1202 dst = context->output + BORDER_LEFT + col * 8;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1203 } else {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1204 dst = context->output;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1205 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1206 for (int i = 0; i < BORDER_LEFT; i++, dst++)
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1207 {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1208 *dst = bg_color;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1209 }
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1210 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1211 if (context->debug < 2) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1212 sprite_buf = context->linebuf + col * 8;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1213 uint8_t a_src, src;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1214 if (context->flags & FLAG_WINDOW) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1215 plane_a_off = context->buf_a_off;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1216 a_src = DBG_SRC_W;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1217 } else {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1218 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1219 a_src = DBG_SRC_A;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1220 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1221 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1222 //printf("A \| tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	1223
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1224 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1225 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1226 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1227 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1228 uint8_t pixel = context->regs[REG_BG_COLOR];
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1229 uint32_t *colors = context->colors;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1230 src = DBG_SRC_BG;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1231 if (*plane_b & 0xF) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1232 pixel = *plane_b;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1233 src = DBG_SRC_B;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1234 }
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1235 uint8_t intensity = *plane_b & BUF_BIT_PRIORITY;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1236 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1237 pixel = *plane_a;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1238 src = DBG_SRC_A;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1239 }
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1240 intensity \|= *plane_a & BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1241 if (sprite_buf & 0xF && (sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1242 if ((*sprite_buf & 0x3F) == 0x3E) {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1243 intensity += BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1244 } else if ((*sprite_buf & 0x3F) == 0x3F) {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1245 intensity = 0;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1246 } else {
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1247 pixel = *sprite_buf;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1248 src = DBG_SRC_S;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1249 if ((pixel & 0xF) == 0xE) {
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1250 intensity = BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1251 } else {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1252 intensity \|= pixel & BUF_BIT_PRIORITY;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1253 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1254 }
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1255 }
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1256 if (!intensity) {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1257 src \|= DBG_SHADOW;
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1258 colors += CRAM_SIZE;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1259 } else if (intensity == BUF_BIT_PRIORITY*2) {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1260 src \|= DBG_HILIGHT;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1261 colors += CRAM_SIZE*2;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1262 }
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	1263
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1264 uint32_t outpixel;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1265 if (context->debug) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1266 outpixel = context->debugcolors[src];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1267 } else {
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1268 outpixel = colors[pixel & 0x3F];
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1269 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1270 *(dst++) = outpixel;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1271 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1272 } else {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1273 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1274 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1275 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1276 uint8_t pixel = context->regs[REG_BG_COLOR];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1277 src = DBG_SRC_BG;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1278 if (*plane_b & 0xF) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1279 pixel = *plane_b;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1280 src = DBG_SRC_B;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1281 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1282 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1283 pixel = *plane_a;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1284 src = DBG_SRC_A;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1285 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1286 if (sprite_buf & 0xF && (sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1287 pixel = *sprite_buf;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	1288 src = DBG_SRC_S;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1289 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1290 uint32_t outpixel;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1291 if (context->debug) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1292 outpixel = context->debugcolors[src];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1293 } else {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1294 outpixel = context->colors[pixel & 0x3F];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1295 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1296 *(dst++) = outpixel;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1297 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1298 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1299 } else if (context->debug == 2) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1300 if (col < 32) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1301 (dst++) = context->colors[col 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1302 (dst++) = context->colors[col 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1303 (dst++) = context->colors[col 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1304 (dst++) = context->colors[col 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1305 (dst++) = context->colors[col 2 + 1];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1306 (dst++) = context->colors[col 2 + 1];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1307 (dst++) = context->colors[col 2 + 1];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1308 (dst++) = context->colors[col 2 + 1];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1309 (dst++) = context->colors[col 2 + 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1310 (dst++) = context->colors[col 2 + 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1311 (dst++) = context->colors[col 2 + 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1312 (dst++) = context->colors[col 2 + 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1313 (dst++) = context->colors[col 2 + 3];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1314 (dst++) = context->colors[col 2 + 3];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1315 (dst++) = context->colors[col 2 + 3];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1316 (dst++) = context->colors[col 2 + 3];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1317 } else if (col == 32 \|\| line >= 192) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1318 for (int32_t i = 0; i < 16; i ++) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1319 *(dst++) = 0;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	1320 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1321 } else {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1322 for (int32_t i = 0; i < 16; i ++) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1323 (dst++) = context->colors[line / 3 + (col - 34) 0x20];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1324 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1325 }
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1326 } else {
771 0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3 Michael Pavone <pavone@retrodev.com> parents: 757 diff changeset	1327 uint32_t base = (context->debug - 3) * 0x200;
0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3 Michael Pavone <pavone@retrodev.com> parents: 757 diff changeset	1328 uint32_t cell = base + (line / 8) * (context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32) + col;
0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3 Michael Pavone <pavone@retrodev.com> parents: 757 diff changeset	1329 uint32_t address = (cell * 32 + (line % 8) * 4) & 0xFFFF;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1330 for (int32_t i = 0; i < 4; i ++) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1331 *(dst++) = context->colors[(context->debug_pal << 4) \| (context->vdpmem[address] >> 4)];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1332 *(dst++) = context->colors[(context->debug_pal << 4) \| (context->vdpmem[address] & 0xF)];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1333 address++;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1334 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1335 cell++;
771 0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3 Michael Pavone <pavone@retrodev.com> parents: 757 diff changeset	1336 address = (cell * 32 + (line % 8) * 4) & 0xFFFF;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1337 for (int32_t i = 0; i < 4; i ++) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1338 *(dst++) = context->colors[(context->debug_pal << 4) \| (context->vdpmem[address] >> 4)];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1339 *(dst++) = context->colors[(context->debug_pal << 4) \| (context->vdpmem[address] & 0xF)];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1340 address++;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1341 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1342 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1343 }
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1344 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1345 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1346 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1347
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1348 static void render_map_mode4(uint32_t line, int32_t col, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1349 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1350 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1351 if (col < 24 \|\| !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1352 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1353 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1354 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1355 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1356 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1357 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1358 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1359 //vflip
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1360 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1361 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1362
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1363 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1364 pixels \|= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1365
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1366 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4 + 2];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1367 pixels \|= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1368 pixels \|= planar_to_chunky[context->vdpmem[address+1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1369
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1370 int i, i_inc, i_limit;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1371 if (context->col_1 & 0x200) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1372 //hflip
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1373 i = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1374 i_inc = 4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1375 i_limit = 32;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1376 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1377 i = 28;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1378 i_inc = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1379 i_limit = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1380 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1381 uint8_t pal_priority = (context->col_1 >> 7 & 0x10) \| (context->col_1 >> 6 & 0x40);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1382 for (uint8_t *dst = context->tmp_buf_a + context->buf_a_off; i != i_limit; i += i_inc, dst++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1383 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1384 *dst = (pixels >> i & 0xF) \| pal_priority;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1385 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1386 context->buf_a_off = (context->buf_a_off + 8) & 15;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1387
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1388 uint8_t bgcolor = 0x10 \| (context->regs[REG_BG_COLOR] & 0xF) + CRAM_SIZE*3;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1389 uint32_t dst = context->output + col 8;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1390 if (context->debug < 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1391 if (col \|\| !(context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1392 uint8_t sprite_src = context->linebuf + col 8;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1393 if (context->regs[REG_MODE_1] & BIT_SPRITE_8PX) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1394 sprite_src += 8;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1395 }
1121 1913f9c28003 Less broken Mode 4 implementation Michael Pavone <pavone@retrodev.com> parents: 1120 diff changeset	1396 for (int i = 0; i < 8; i++, sprite_src++)
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1397 {
1121 1913f9c28003 Less broken Mode 4 implementation Michael Pavone <pavone@retrodev.com> parents: 1120 diff changeset	1398 uint8_t bg_src = context->tmp_buf_a + ((8 + i + col 8 - (context->hscroll_a & 0x7)) & 15);
1132 fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1399 if ((bg_src & 0x4F) > 0x40 \|\| !sprite_src) {
fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1400 //background plane has priority and is opaque or sprite layer is transparent
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1401 if (context->debug) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1402 *(dst++) = context->debugcolors[DBG_SRC_A];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1403 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1404 (dst++) = context->colors[(bg_src & 0x1F) + CRAM_SIZE*3];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1405 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1406 } else {
1132 fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1407 //sprite layer is opaque and not covered by high priority BG pixels
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1408 if (context->debug) {
1132 fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1409 *(dst++) = context->debugcolors[DBG_SRC_S];
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1410 } else {
1132 fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1411 (dst++) = context->colors[sprite_src \| 0x10 + CRAM_SIZE*3];
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1412 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1413 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1414 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1415 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1416 for (int i = 0; i < 8; i++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1417 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1418 *(dst++) = context->colors[bgcolor];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1419 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1420 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1421 } else if (context->debug == 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1422 for (int i = 0; i < 8; i++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1423 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1424 (dst++) = context->colors[CRAM_SIZE3 + col];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1425 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1426 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1427 uint32_t cell = (line / 8) * 32 + col;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1428 uint32_t address = cell * 32 + (line % 8) * 4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1429 uint32_t m4_address = mode4_address_map[address & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1430 uint32_t pixel = planar_to_chunky[context->vdpmem[m4_address]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1431 pixel \|= planar_to_chunky[context->vdpmem[m4_address + 1]];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1432 m4_address = mode4_address_map[(address + 2) & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1433 pixel \|= planar_to_chunky[context->vdpmem[m4_address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1434 pixel \|= planar_to_chunky[context->vdpmem[m4_address + 1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1435 if (context->debug_pal < 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1436 for (int i = 28; i >= 0; i -= 4)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1437 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1438 (dst++) = context->colors[CRAM_SIZE3 \| (context->debug_pal << 4) \| (pixel >> i & 0xF)];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1439 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1440 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1441 for (int i = 28; i >= 0; i -= 4)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1442 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1443 uint8_t value = (pixel >> i & 0xF) * 17;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1444 if (context->debug_pal == 3) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1445 value = 255 - value;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1446 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1447 *(dst++) = render_map_color(value, value, value);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1448 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1449 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1450 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1451 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1452
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1453 static uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19};
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1454
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1455 static void vdp_advance_line(vdp_context *context)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1456 {
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1457 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1458 static uint32_t last_line = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1459 if (last_line != 0xFFFFFFFF) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1460 uint32_t diff = context->cycles - last_line;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1461 if (diff != MCLKS_LINE) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1462 printf("Line %d took %d cycles\n", context->vcounter, diff);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1463 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1464 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1465 last_line = context->cycles;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1466 #endif
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1467 context->vcounter++;
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1468
1156 b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1469 uint8_t is_mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1470 if (is_mode_5) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1471 if (context->flags2 & FLAG2_REGION_PAL) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1472 if (context->latched_mode & BIT_PAL) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1473 if (context->vcounter == 0x10B) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1474 context->vcounter = 0x1D2;
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1475 }
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1476 } else if (context->vcounter == 0x103){
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1477 context->vcounter = 0x1CA;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1478 }
1156 b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1479 } else if (!(context->latched_mode & BIT_PAL) && context->vcounter == 0xEB) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1480 context->vcounter = 0x1E5;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1481 }
1299 da1ffc4026c4 Fix latching of V32 mode bit Michael Pavone <pavone@retrodev.com> parents: 1290 diff changeset	1482 if (context->vcounter == 0x200 - context->border_top) {
da1ffc4026c4 Fix latching of V32 mode bit Michael Pavone <pavone@retrodev.com> parents: 1290 diff changeset	1483 latch_mode(context);
da1ffc4026c4 Fix latching of V32 mode bit Michael Pavone <pavone@retrodev.com> parents: 1290 diff changeset	1484 }
1156 b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1485 } else if (context->vcounter == 0xDB) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1486 context->vcounter = 0x1D5;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1487 }
1273 6dedaa645843 Fix graphical corruption and sprite flickering introduced into some games by the last change for horizontal border support Michael Pavone <pavone@retrodev.com> parents: 1272 diff changeset	1488 context->vcounter &= 0x1FF;
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1489
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1490 if (context->vcounter > context->inactive_start) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1491 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1492 } else if (context->hint_counter) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1493 context->hint_counter--;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1494 } else {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1495 context->flags2 \|= FLAG2_HINT_PENDING;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1496 context->pending_hint_start = context->cycles;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1497 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1498 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1499 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1500
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1501 static void advance_output_line(vdp_context *context)
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1502 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1503 if (headless) {
1168 fa73a77ddf92 Fix benchmark mode Michael Pavone <pavone@retrodev.com> parents: 1167 diff changeset	1504 if (context->vcounter == context->inactive_start) {
fa73a77ddf92 Fix benchmark mode Michael Pavone <pavone@retrodev.com> parents: 1167 diff changeset	1505 context->frame++;
fa73a77ddf92 Fix benchmark mode Michael Pavone <pavone@retrodev.com> parents: 1167 diff changeset	1506 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1507 context->vcounter &= 0x1FF;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1508 } else {
1273 6dedaa645843 Fix graphical corruption and sprite flickering introduced into some games by the last change for horizontal border support Michael Pavone <pavone@retrodev.com> parents: 1272 diff changeset	1509 if (context->vcounter == (context->inactive_start & 0x1FF)) {
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1510 render_framebuffer_updated(context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN: FRAMEBUFFER_ODD, context->h40_lines > (context->inactive_start + context->border_top) / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1511 if (context->double_res) {
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1512 context->flags2 ^= FLAG2_EVEN_FIELD;
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1513 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1514 context->fb = render_get_framebuffer(context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN : FRAMEBUFFER_ODD, &context->output_pitch);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1515 context->h40_lines = 0;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1516 context->frame++;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1517 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1518 uint32_t output_line;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1519 if (context->vcounter < context->inactive_start + context->border_bot) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1520 output_line = context->border_top + context->vcounter;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1521 } else if (context->vcounter > 0x200 - context->border_top) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1522 output_line = context->vcounter - (0x200 - context->border_top);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1523 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1524 output_line = INVALID_LINE;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1525 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1526 context->output = (uint32_t )(((char )context->fb) + context->output_pitch * output_line);
1271 c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1527 #ifdef DEBUG_FB_FILL
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1528 for (int i = 0; i < LINEBUF_SIZE; i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1529 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1530 context->output[i] = 0xFFFF00FF;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1531 }
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1532 #endif
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1533 if (output_line != INVALID_LINE && (context->regs[REG_MODE_4] & BIT_H40)) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1534 context->h40_lines++;
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1535 }
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1536 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1537 }
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1538
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1539 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; }
924 1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period Michael Pavone <pavone@retrodev.com> parents: 923 diff changeset	1540 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1541
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1542 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1543 case startcyc:\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1544 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1545 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1546 case ((startcyc+1)&0xFF):\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1547 external_slot(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1548 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1549 case ((startcyc+2)&0xFF):\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1550 render_map_1(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1551 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1552 case ((startcyc+3)&0xFF):\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1553 render_map_2(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1554 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1555 case ((startcyc+4)&0xFF):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1556 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1557 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1558 case ((startcyc+5)&0xFF):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1559 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1560 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1561 case ((startcyc+6)&0xFF):\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1562 render_map_3(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1563 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1564 case ((startcyc+7)&0xFF):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1565 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1566 CHECK_LIMIT
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1567
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1568 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1569 case startcyc:\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1570 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1571 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1572 case (startcyc+1):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1573 /* refresh, no don't run dma src */\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1574 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1575 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1576 CHECK_ONLY\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1577 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1578 render_map_1(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1579 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1580 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1581 render_map_2(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1582 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1583 case (startcyc+4):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1584 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1585 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1586 case (startcyc+5):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1587 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1588 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1589 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1590 render_map_3(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1591 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1592 case (startcyc+7):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1593 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1594 CHECK_LIMIT
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1595
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1596 #define COLUMN_RENDER_BLOCK_MODE4(column, startcyc) \
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1597 case startcyc:\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1598 read_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1599 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1600 case ((startcyc+1)&0xFF):\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1601 if (column & 3) {\
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1602 scan_sprite_table_mode4(context);\
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1603 } else {\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1604 external_slot(context);\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1605 }\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1606 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1607 case ((startcyc+2)&0xFF):\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1608 fetch_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1609 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1610 case ((startcyc+3)&0xFF):\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1611 render_map_mode4(context->vcounter, column, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1612 CHECK_LIMIT
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1613
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1614 #define CHECK_LIMIT_HSYNC(slot) \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1615 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1616 if (slot >= HSYNC_SLOT_H40 && slot < HSYNC_END_H40) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1617 context->cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1618 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1619 context->cycles += slot_cycles;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1620 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1621 if (slot == 182) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1622 context->hslot = 229;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1623 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1624 context->hslot++;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1625 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1626 CHECK_ONLY
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	1627
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1628 #define SPRITE_RENDER_H40(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1629 case slot:\
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1630 if ((slot) == BG_START_SLOT + LINEBUF_SIZE/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1631 advance_output_line(context);\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1632 }\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1633 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1634 scan_sprite_table(context->vcounter, context);\
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1635 CHECK_LIMIT_HSYNC(slot)
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	1636
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1637 //Note that the line advancement check will fail if BG_START_SLOT is > 6
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1638 //as we're bumping up against the hcounter jump
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1639 #define SPRITE_RENDER_H32(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1640 case slot:\
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1641 if ((slot) == BG_START_SLOT + (256+HORIZ_BORDER)/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1642 advance_output_line(context);\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1643 }\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1644 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1645 scan_sprite_table(context->vcounter, context);\
924 1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period Michael Pavone <pavone@retrodev.com> parents: 923 diff changeset	1646 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1647 if (slot == 147) {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1648 context->hslot = 233;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1649 } else {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1650 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1651 }\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1652 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1653 CHECK_ONLY
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1654
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1655 #define MODE4_CHECK_SLOT_LINE(slot) \
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1656 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1657 if ((slot) == 147) {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1658 context->hslot = 233;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1659 } else {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1660 context->hslot++;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1661 }\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1662 context->cycles += slot_cycles;\
1163 b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1663 if ((slot+1) == LINE_CHANGE_MODE4) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1664 vdp_advance_line(context);\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1665 if (context->vcounter == 192) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1666 return;\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1667 }\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1668 }\
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1669 CHECK_ONLY
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1670
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1671 #define CALC_SLOT(slot, increment) ((slot+increment) > 147 && (slot+increment) < 233 ? (slot+increment-148+233): (slot+increment))
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1672
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1673 #define SPRITE_RENDER_H32_MODE4(slot) \
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1674 case slot:\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1675 read_sprite_x_mode4(context);\
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1676 MODE4_CHECK_SLOT_LINE(slot)\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1677 case CALC_SLOT(slot, 1):\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1678 read_sprite_x_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1679 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot,1))\
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1680 case CALC_SLOT(slot, 2):\
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1681 fetch_sprite_cells_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1682 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 2))\
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1683 case CALC_SLOT(slot, 3):\
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1684 render_sprite_cells_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1685 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 3))\
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1686 case CALC_SLOT(slot, 4):\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1687 fetch_sprite_cells_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1688 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 4))\
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1689 case CALC_SLOT(slot, 5):\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1690 render_sprite_cells_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1691 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 5))
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1692
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1693 static void vdp_h40(vdp_context * context, uint32_t target_cycles)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1694 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1695 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1696 uint32_t mask;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1697 uint32_t const slot_cycles = MCLKS_SLOT_H40;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1698 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1699 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1700 for (;;)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1701 {
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1702 case 165:
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1703 if (context->vcounter == 0x1FF) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1704 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1705 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1706 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1707 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1708 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1709 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1710 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1711 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1712 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1713 *dst = bg_color;
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1714 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1715 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1716 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1717 }
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1718 CHECK_LIMIT
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1719 case 166:
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1720 if (context->vcounter == 0x1FF) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1721 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1722 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1723 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1724 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1725 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1726 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1727 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1728 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1729 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1730 *dst = bg_color;
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1731 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1732 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1733 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1734 }
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1735 CHECK_LIMIT
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1736 //sprite attribute table scan starts
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1737 case 167:
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1738 if (context->vcounter == 0x1FF) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1739 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1740 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1741 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1742 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1743 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1744 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1745 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1746 }
1271 c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1747 for (int i = 0; i < LINEBUF_SIZE - 2 * (context->hslot - BG_START_SLOT); i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1748 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1749 *(dst++) = bg_color;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1750 }
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1751 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1752 context->sprite_index = 0x80;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1753 context->slot_counter = MAX_SPRITES_LINE;
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1754 render_sprite_cells( context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1755 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1756 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1757 SPRITE_RENDER_H40(168)
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1758 SPRITE_RENDER_H40(169)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1759 SPRITE_RENDER_H40(170)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1760 SPRITE_RENDER_H40(171)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1761 SPRITE_RENDER_H40(172)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1762 SPRITE_RENDER_H40(173)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1763 SPRITE_RENDER_H40(174)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1764 SPRITE_RENDER_H40(175)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1765 SPRITE_RENDER_H40(176)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1766 SPRITE_RENDER_H40(177)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1767 SPRITE_RENDER_H40(178)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1768 SPRITE_RENDER_H40(179)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1769 SPRITE_RENDER_H40(180)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1770 SPRITE_RENDER_H40(181)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1771 SPRITE_RENDER_H40(182)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1772 SPRITE_RENDER_H40(229)
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1773 //!HSYNC asserted
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1774 SPRITE_RENDER_H40(230)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1775 SPRITE_RENDER_H40(231)
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1776 case 232:
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1777 external_slot(context);
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1778 CHECK_LIMIT_HSYNC(232)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1779 SPRITE_RENDER_H40(233)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1780 SPRITE_RENDER_H40(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1781 SPRITE_RENDER_H40(235)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1782 SPRITE_RENDER_H40(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1783 SPRITE_RENDER_H40(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1784 SPRITE_RENDER_H40(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1785 SPRITE_RENDER_H40(239)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1786 SPRITE_RENDER_H40(240)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1787 SPRITE_RENDER_H40(241)
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1788 SPRITE_RENDER_H40(242)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1789 SPRITE_RENDER_H40(243)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1790 case 244:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1791 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1792 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1793 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1794 mask \|= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1795 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1796 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1797 mask \|= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1798 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1799 address += (context->vcounter & mask) * 4;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1800 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1801 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1802 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
924 1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period Michael Pavone <pavone@retrodev.com> parents: 923 diff changeset	1803 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1804 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1805 context->cycles += h40_hsync_cycles[14];
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1806 CHECK_ONLY
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1807 //!HSYNC high
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1808 SPRITE_RENDER_H40(245)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1809 SPRITE_RENDER_H40(246)
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1810 SPRITE_RENDER_H40(247)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1811 SPRITE_RENDER_H40(248)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1812 case 249:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1813 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1814 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1815 SPRITE_RENDER_H40(250)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1816 case 251:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1817 render_map_1(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1818 scan_sprite_table(context->vcounter, context);//Just a guess
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1819 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1820 case 252:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1821 render_map_2(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1822 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1823 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1824 case 253:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1825 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1826 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1827 SPRITE_RENDER_H40(254)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1828 case 255:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1829 render_map_3(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1830 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1831 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1832 case 0:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1833 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1834 scan_sprite_table(context->vcounter, context);//Just a guess
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1835 //reverse context slot counter so it counts the number of sprite slots
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1836 //filled rather than the number of available slots
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1837 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1838 context->cur_slot = MAX_SPRITES_LINE-1;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1839 context->sprite_draws = MAX_DRAWS;
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	1840 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1841 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1842 COLUMN_RENDER_BLOCK(2, 1)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1843 COLUMN_RENDER_BLOCK(4, 9)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1844 COLUMN_RENDER_BLOCK(6, 17)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1845 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1846 COLUMN_RENDER_BLOCK(10, 33)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1847 COLUMN_RENDER_BLOCK(12, 41)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1848 COLUMN_RENDER_BLOCK(14, 49)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1849 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1850 COLUMN_RENDER_BLOCK(18, 65)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1851 COLUMN_RENDER_BLOCK(20, 73)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1852 COLUMN_RENDER_BLOCK(22, 81)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1853 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1854 COLUMN_RENDER_BLOCK(26, 97)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1855 COLUMN_RENDER_BLOCK(28, 105)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1856 COLUMN_RENDER_BLOCK(30, 113)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1857 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1858 COLUMN_RENDER_BLOCK(34, 129)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1859 COLUMN_RENDER_BLOCK(36, 137)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1860 COLUMN_RENDER_BLOCK(38, 145)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1861 COLUMN_RENDER_BLOCK_REFRESH(40, 153)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1862 case 161:
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1863 external_slot(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1864 CHECK_LIMIT
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1865 case 162: {
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1866 external_slot(context);
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1867 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1868 for (int i = LINEBUF_SIZE-BORDER_RIGHT; i < LINEBUF_SIZE; i++)
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1869 {
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1870 context->output[i] = bg_color;
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1871 }
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1872 CHECK_LIMIT
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1873 }
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1874 //sprite render to line buffer starts
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1875 case 163:
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1876 context->cur_slot = MAX_DRAWS-1;
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1877 memset(context->linebuf, 0, LINEBUF_SIZE);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1878 render_sprite_cells(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1879 CHECK_LIMIT
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1880 case 164:
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1881 render_sprite_cells(context);
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1882 if (context->flags & FLAG_DMA_RUN) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1883 run_dma_src(context, -1);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1884 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1885 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1886 context->cycles += slot_cycles;
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1887 vdp_advance_line(context);
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1888 if (context->vcounter == context->inactive_start) {
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1889 return;
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1890 }
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1891 CHECK_ONLY
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1892 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1893 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1894 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1895 context->cycles += slot_cycles;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1896 return;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1897 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1898 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1899
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1900 static void vdp_h32(vdp_context * context, uint32_t target_cycles)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1901 {
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1902 uint16_t address;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1903 uint32_t mask;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1904 uint32_t const slot_cycles = MCLKS_SLOT_H32;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1905 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1906 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1907 for (;;)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1908 {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1909 case 133:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1910 if (context->vcounter == 0x1FF) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1911 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1912 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1913 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1914 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1915 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1916 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1917 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1918 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1919 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1920 *dst = bg_color;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1921 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1922 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1923 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1924 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1925 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1926 case 134:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1927 if (context->vcounter == 0x1FF) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1928 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1929 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1930 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1931 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1932 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1933 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1934 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1935 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1936 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1937 *dst = bg_color;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1938 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1939 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1940 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1941 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1942 CHECK_LIMIT
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	1943 //sprite attribute table scan starts
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1944 case 135: //FIXME - Here
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1945 if (context->vcounter == 0x1FF) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1946 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1947 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1948 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1949 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1950 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1951 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1952 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1953 }
1271 c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1954 for (int i = 0; i < (256+HORIZ_BORDER) - 2 * (context->hslot - BG_START_SLOT); i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1955 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1956 *(dst++) = bg_color;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1957 }
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1958 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1959 context->sprite_index = 0x80;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1960 context->slot_counter = MAX_SPRITES_LINE_H32;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1961 render_sprite_cells( context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1962 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1963 CHECK_LIMIT
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	1964 SPRITE_RENDER_H32(136)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	1965 SPRITE_RENDER_H32(137)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	1966 SPRITE_RENDER_H32(138)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1967 SPRITE_RENDER_H32(139)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1968 SPRITE_RENDER_H32(140)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1969 SPRITE_RENDER_H32(141)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1970 SPRITE_RENDER_H32(142)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1971 SPRITE_RENDER_H32(143)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1972 SPRITE_RENDER_H32(144)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1973 case 145:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1974 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1975 CHECK_LIMIT
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1976 SPRITE_RENDER_H32(146)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1977 SPRITE_RENDER_H32(147)
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	1978 SPRITE_RENDER_H32(233)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1979 SPRITE_RENDER_H32(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1980 SPRITE_RENDER_H32(235)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1981 //HSYNC start
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1982 SPRITE_RENDER_H32(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1983 SPRITE_RENDER_H32(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1984 SPRITE_RENDER_H32(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1985 SPRITE_RENDER_H32(239)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1986 SPRITE_RENDER_H32(240)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1987 SPRITE_RENDER_H32(241)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1988 SPRITE_RENDER_H32(242)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1989 case 243:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1990 external_slot(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1991 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1992 case 244:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1993 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1994 mask = 0;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1995 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1996 mask \|= 0xF8;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1997 }
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1998 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	1999 mask \|= 0x7;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2000 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2001 address += (context->vcounter & mask) * 4;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2002 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2003 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2004 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2005 CHECK_LIMIT
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2006 SPRITE_RENDER_H32(245)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2007 SPRITE_RENDER_H32(246)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2008 SPRITE_RENDER_H32(247)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2009 SPRITE_RENDER_H32(248)
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2010 //!HSYNC high
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2011 case 249:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2012 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2013 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2014 SPRITE_RENDER_H32(250)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2015 case 251:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2016 render_map_1(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2017 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2018 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2019 case 252:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2020 render_map_2(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2021 scan_sprite_table(context->vcounter, context);//Just a guess
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2022 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2023 case 253:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2024 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2025 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2026 case 254:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2027 render_sprite_cells(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2028 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2029 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2030 case 255:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2031 render_map_3(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2032 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2033 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2034 case 0:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2035 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2036 scan_sprite_table(context->vcounter, context);//Just a guess
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2037 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2038 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2039 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2040 context->cur_slot = MAX_SPRITES_LINE_H32-1;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2041 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2042 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2043 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2044 COLUMN_RENDER_BLOCK(2, 1)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2045 COLUMN_RENDER_BLOCK(4, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2046 COLUMN_RENDER_BLOCK(6, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2047 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2048 COLUMN_RENDER_BLOCK(10, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2049 COLUMN_RENDER_BLOCK(12, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2050 COLUMN_RENDER_BLOCK(14, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2051 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2052 COLUMN_RENDER_BLOCK(18, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2053 COLUMN_RENDER_BLOCK(20, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2054 COLUMN_RENDER_BLOCK(22, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2055 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2056 COLUMN_RENDER_BLOCK(26, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2057 COLUMN_RENDER_BLOCK(28, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2058 COLUMN_RENDER_BLOCK(30, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2059 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2060 case 129:
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2061 external_slot(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2062 CHECK_LIMIT
1269 ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2063 case 130: {
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2064 external_slot(context);
1269 ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2065 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2066 for (int i = 256+BORDER_LEFT; i < 256+HORIZ_BORDER; i++)
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2067 {
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2068 context->output[i] = bg_color;
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2069 }
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2070 CHECK_LIMIT
1269 ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2071 }
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2072 //sprite render to line buffer starts
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2073 case 131:
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2074 context->cur_slot = MAX_DRAWS_H32-1;
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2075 memset(context->linebuf, 0, LINEBUF_SIZE);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2076 render_sprite_cells(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2077 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2078 case 132:
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2079 render_sprite_cells(context);
1173 d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2080 if (context->flags & FLAG_DMA_RUN) {
d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2081 run_dma_src(context, -1);
d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2082 }
d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2083 context->hslot++;
d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2084 context->cycles += slot_cycles;
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2085 vdp_advance_line(context);
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2086 if (context->vcounter == context->inactive_start) {
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2087 return;
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2088 }
1173 d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2089 CHECK_ONLY
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2090 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2091 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2092 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2093 context->cycles += MCLKS_SLOT_H32;
503 eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	2094 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	2095 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	2096
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2097 static void vdp_h32_mode4(vdp_context * context, uint32_t target_cycles)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2098 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2099 uint16_t address;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2100 uint32_t mask;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2101 uint32_t const slot_cycles = MCLKS_SLOT_H32;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2102 switch(context->hslot)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2103 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2104 for (;;)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2105 {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2106 //sprite rendering starts
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2107 SPRITE_RENDER_H32_MODE4(137)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2108 SPRITE_RENDER_H32_MODE4(143)
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2109 case 234:
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2110 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2111 CHECK_LIMIT
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2112 case 235:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2113 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2114 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2115 //!HSYNC low
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2116 case 236:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2117 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2118 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2119 case 237:
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2120 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2121 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2122 case 238:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2123 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2124 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2125 SPRITE_RENDER_H32_MODE4(239)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2126 SPRITE_RENDER_H32_MODE4(245)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2127 case 251:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2128 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2129 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2130 case 252:
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2131 external_slot(context);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2132 if (context->regs[REG_MODE_1] & BIT_HSCRL_LOCK && context->vcounter < 16) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2133 context->hscroll_a = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2134 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2135 context->hscroll_a = context->regs[REG_X_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2136 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2137 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2138 case 253:
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2139 context->sprite_index = 0;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2140 context->slot_counter = MAX_DRAWS_H32_MODE4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2141 scan_sprite_table_mode4(context);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2142 CHECK_LIMIT
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2143 case 254:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2144 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2145 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2146 case 255:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2147 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2148 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2149 case 0:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2150 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2151 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2152 case 1:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2153 scan_sprite_table_mode4(context);
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2154 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2155 case 2:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2156 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2157 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2158 case 3:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2159 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2160 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2161 case 4:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2162 scan_sprite_table_mode4(context);
1121 1913f9c28003 Less broken Mode 4 implementation Michael Pavone <pavone@retrodev.com> parents: 1120 diff changeset	2163 context->buf_a_off = 8;
1913f9c28003 Less broken Mode 4 implementation Michael Pavone <pavone@retrodev.com> parents: 1120 diff changeset	2164 memset(context->tmp_buf_a, 0, 8);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2165 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2166 COLUMN_RENDER_BLOCK_MODE4(0, 5)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2167 COLUMN_RENDER_BLOCK_MODE4(1, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2168 COLUMN_RENDER_BLOCK_MODE4(2, 13)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2169 COLUMN_RENDER_BLOCK_MODE4(3, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2170 COLUMN_RENDER_BLOCK_MODE4(4, 21)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2171 COLUMN_RENDER_BLOCK_MODE4(5, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2172 COLUMN_RENDER_BLOCK_MODE4(6, 29)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2173 COLUMN_RENDER_BLOCK_MODE4(7, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2174 COLUMN_RENDER_BLOCK_MODE4(8, 37)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2175 COLUMN_RENDER_BLOCK_MODE4(9, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2176 COLUMN_RENDER_BLOCK_MODE4(10, 45)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2177 COLUMN_RENDER_BLOCK_MODE4(11, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2178 COLUMN_RENDER_BLOCK_MODE4(12, 53)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2179 COLUMN_RENDER_BLOCK_MODE4(13, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2180 COLUMN_RENDER_BLOCK_MODE4(14, 61)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2181 COLUMN_RENDER_BLOCK_MODE4(15, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2182 COLUMN_RENDER_BLOCK_MODE4(16, 69)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2183 COLUMN_RENDER_BLOCK_MODE4(17, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2184 COLUMN_RENDER_BLOCK_MODE4(18, 77)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2185 COLUMN_RENDER_BLOCK_MODE4(19, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2186 COLUMN_RENDER_BLOCK_MODE4(20, 85)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2187 COLUMN_RENDER_BLOCK_MODE4(21, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2188 COLUMN_RENDER_BLOCK_MODE4(22, 93)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2189 COLUMN_RENDER_BLOCK_MODE4(23, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2190 COLUMN_RENDER_BLOCK_MODE4(24, 101)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2191 COLUMN_RENDER_BLOCK_MODE4(25, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2192 COLUMN_RENDER_BLOCK_MODE4(26, 109)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2193 COLUMN_RENDER_BLOCK_MODE4(27, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2194 COLUMN_RENDER_BLOCK_MODE4(28, 117)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2195 COLUMN_RENDER_BLOCK_MODE4(29, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2196 COLUMN_RENDER_BLOCK_MODE4(30, 125)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2197 COLUMN_RENDER_BLOCK_MODE4(31, 129)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2198 case 133:
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2199 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2200 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2201 case 134:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2202 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2203 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2204 case 135:
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2205 external_slot(context);
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2206 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2207 case 136:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2208 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2209 //set things up for sprite rendering in the next slot
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2210 memset(context->linebuf, 0, LINEBUF_SIZE);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2211 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2212 context->sprite_draws = MAX_DRAWS_H32_MODE4;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2213 CHECK_LIMIT
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2214 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2215 default:
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2216 context->hslot++;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2217 context->cycles += MCLKS_SLOT_H32;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2218 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2219 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2220
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2221 void latch_mode(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2222 {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2223 context->latched_mode = context->regs[REG_MODE_2] & BIT_PAL;
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2224 update_video_params(context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2225 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2226
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2227 static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2228 {
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2229 uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2230 uint8_t index_reset_value, max_draws, max_sprites;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2231 uint16_t vint_line, active_line;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2232 uint32_t bg_color;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2233
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2234 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2235 if (is_h40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2236 buf_clear_slot = 161;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2237 index_reset_slot = 165;
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2238 bg_end_slot = BG_START_SLOT + LINEBUF_SIZE/2;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2239 max_draws = MAX_DRAWS-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2240 max_sprites = MAX_SPRITES_LINE;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2241 index_reset_value = 0x80;
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2242 vint_slot = VINT_SLOT_H40;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2243 line_change = LINE_CHANGE_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2244 jump_start = 182;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2245 jump_dest = 229;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2246 } else {
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2247 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2248 max_draws = MAX_DRAWS_H32-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2249 max_sprites = MAX_SPRITES_LINE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2250 buf_clear_slot = 128;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2251 index_reset_slot = 132;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2252 index_reset_value = 0x80;
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2253 vint_slot = VINT_SLOT_H32;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2254 line_change = LINE_CHANGE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2255 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2256 jump_dest = 233;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2257 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2258 vint_line = context->inactive_start;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2259 active_line = 0x1FF;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2260 } else {
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2261 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2262 max_draws = MAX_DRAWS_H32_MODE4;
1278 34d3cb05014d Fix VDP buffer overrun that was causing sprite flickering in some games Michael Pavone <pavone@retrodev.com> parents: 1273 diff changeset	2263 max_sprites = 8;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2264 buf_clear_slot = 136;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2265 index_reset_slot = 253;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2266 index_reset_value = 0;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2267 vint_line = context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2268 vint_slot = VINT_SLOT_MODE4;
1177 67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency Michael Pavone <pavone@retrodev.com> parents: 1175 diff changeset	2269 line_change = LINE_CHANGE_MODE4;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2270 bg_color = render_map_color(0, 0, 0);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2271 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2272 jump_dest = 233;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2273 active_line = 0;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2274 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2275 uint32_t *dst = (
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2276 context->vcounter < context->inactive_start + context->border_bot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2277 \|\| context->vcounter > 0x200 - context->border_top
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2278 ) && context->hslot >= BG_START_SLOT && context->hslot < bg_end_slot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2279 ? context->output + 2 * (context->hslot - BG_START_SLOT)
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2280 : NULL;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2281
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2282 while(context->cycles < target_cycles)
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2283 {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2284 if (context->hslot == BG_START_SLOT && (
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2285 context->vcounter < context->inactive_start + context->border_bot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2286 \|\| context->vcounter > 0x200 - context->border_top
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2287 )) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2288 dst = context->output + (context->hslot - BG_START_SLOT) * 2;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2289 } else if (context->hslot == bg_end_slot) {
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	2290 advance_output_line(context);
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2291 dst = NULL;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2292 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2293
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2294 if (context->hslot == buf_clear_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2295 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2296 context->cur_slot = max_draws;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2297 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2298 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2299 context->sprite_draws = MAX_DRAWS_H32_MODE4;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2300 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2301 memset(context->linebuf, 0, LINEBUF_SIZE);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2302 } else if (context->hslot == index_reset_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2303 context->sprite_index = index_reset_value;
1278 34d3cb05014d Fix VDP buffer overrun that was causing sprite flickering in some games Michael Pavone <pavone@retrodev.com> parents: 1273 diff changeset	2304 context->slot_counter = max_sprites;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2305 } else if (context->vcounter == vint_line && context->hslot == vint_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2306 context->flags2 \|= FLAG2_VINT_PENDING;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2307 context->pending_vint_start = context->cycles;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2308 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2309
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2310 if (dst) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2311 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2312 bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2313 } else if (context->regs[REG_MODE_1] & BIT_MODE_4) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2314 bg_color = context->colors[CRAM_SIZE * 3 + 0x10 + (context->regs[REG_BG_COLOR] & 0xF)];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2315 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2316 *(dst++) = bg_color;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2317 *(dst++) = bg_color;
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2318 if (context->hslot == (bg_end_slot-1)) {
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2319 *(dst++) = bg_color;
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2320 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2321 }
1183 8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2322
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2323 if (!is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2324 external_slot(context);
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2325 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2326 run_dma_src(context, context->hslot);
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2327 }
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2328 }
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2329
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2330 if (is_h40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2331 if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2332 context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2333 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2334 context->cycles += MCLKS_SLOT_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2335 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2336 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2337 context->cycles += MCLKS_SLOT_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2338 }
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2339 if (context->hslot == jump_start) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2340 context->hslot = jump_dest;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2341 } else {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2342 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2343 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2344 if (context->hslot == line_change) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2345 vdp_advance_line(context);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2346 if (context->vcounter == active_line) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2347 return;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2348 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2349 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2350 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2351 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2352
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2353 void vdp_run_context(vdp_context * context, uint32_t target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2354 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2355 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2356 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2357 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2358 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2359 uint8_t active_slot;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2360 if (mode_5) {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2361 //line 0x1FF is basically active even though it's not displayed
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2362 active_slot = (context->vcounter < context->inactive_start \|\| context->vcounter == 0x1FF) && (context->regs[REG_MODE_2] & DISPLAY_ENABLE);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2363 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2364 //display is effectively disabled if neither mode 5 nor mode 4 are selected
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2365 active_slot = context->vcounter < context->inactive_start && (context->regs[REG_MODE_2] & DISPLAY_ENABLE) && (context->regs[REG_MODE_1] & BIT_MODE_4);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2366 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2367
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2368 if (active_slot) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2369 if (mode_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2370 if (is_h40) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2371 vdp_h40(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2372 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2373 vdp_h32(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2374 }
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	2375 } else {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2376 vdp_h32_mode4(context, target_cycles);
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	2377 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	2378 } else {
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2379 vdp_inactive(context, target_cycles, is_h40, mode_5);
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2380 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2381 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2382 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2383
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2384 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2385 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2386 uint32_t old_frame = context->frame;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2387 while (context->frame == old_frame) {
1179 1271b240b9c2 Fix vdp_run_to_vblank Michael Pavone <pavone@retrodev.com> parents: 1178 diff changeset	2388 vdp_run_context(context, context->cycles + MCLKS_LINE);
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2389 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2390 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2391 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2392
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2393 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2394 {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2395 for(;;) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2396 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2397 if (!dmalen) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2398 dmalen = 0x10000;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2399 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2400 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2401 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 \|\| (context->cd & 0xF) == VRAM_WRITE) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2402 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2403 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2404 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2405 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2406 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2407 if (target_cycles < min_dma_complete) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2408 vdp_run_context(context, target_cycles);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2409 return;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2410 } else {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2411 vdp_run_context(context, min_dma_complete);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2412 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2413 return;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2414 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2415 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2416 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2417 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2418
1154 c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2419 static uint16_t get_ext_vcounter(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2420 {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2421 uint16_t line= context->vcounter & 0xFF;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2422 if (context->double_res) {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2423 line <<= 1;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2424 if (line & 0x100) {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2425 line \|= 1;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2426 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2427 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2428 return line << 8;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2429 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2430
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2431 void vdp_latch_hv(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2432 {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2433 context->hv_latch = context->hslot \| get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2434 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2435
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2436 uint16_t vdp_hv_counter_read(vdp_context * context)
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2437 {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2438 if ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_1] & BIT_HVC_LATCH)) {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2439 return context->hv_latch;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2440 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2441 uint16_t hv;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2442 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2443 hv = context->hslot;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2444 } else {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2445 hv = context->hv_latch & 0xFF;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2446 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2447 hv \|= get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2448
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2449 return hv;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2450 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2451
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2452 int vdp_control_port_write(vdp_context * context, uint16_t value)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2453 {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2454 //printf("control port write: %X at %d\n", value, context->cycles);
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2455 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2456 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2457 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2458 if (context->flags & FLAG_PENDING) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2459 context->address = (context->address & 0x3FFF) \| (value << 14);
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2460 //It seems like the DMA enable bit doesn't so much enable DMA so much
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2461 //as it enables changing CD5 from control port writes
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2462 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2463 context->cd = (context->cd & preserve) \| ((value >> 2) & ~preserve & 0xFF);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2464 context->flags &= ~FLAG_PENDING;
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2465 //Should these be taken care of here or after the first write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2466 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2467 context->flags2 &= ~FLAG2_READ_PENDING;
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	2468 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2469 if (context->cd & 0x20) {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2470 //
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2471 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2472 //DMA copy or 68K -> VDP, transfer starts immediately
131 8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances Mike Pavone <pavone@retrodev.com> parents: 109 diff changeset	2473 context->dma_cd = context->cd;
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2474 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot);
1191 8dc50e50ced6 Remove accidentally committed debug logging Michael Pavone <pavone@retrodev.com> parents: 1189 diff changeset	2475 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
8dc50e50ced6 Remove accidentally committed debug logging Michael Pavone <pavone@retrodev.com> parents: 1189 diff changeset	2476 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) \| (context->regs[REG_DMASRC_M] << 9) \| (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 \| context->regs[REG_DMALEN_L]);
1289 6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2477 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2478 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2479 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2480 //sticking with 3 slots for now until I can do some more captures
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2481 vdp_run_context(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5));
1285 76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation Michael Pavone <pavone@retrodev.com> parents: 1278 diff changeset	2482 context->flags \|= FLAG_DMA_RUN;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2483 return 1;
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2484 } else {
1285 76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation Michael Pavone <pavone@retrodev.com> parents: 1278 diff changeset	2485 context->flags \|= FLAG_DMA_RUN;
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2486 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2487 }
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2488 } else {
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	2489 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2490 }
63 a6dd5b7a971b Add FPS counter to console output Mike Pavone <pavone@retrodev.com> parents: 58 diff changeset	2491 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2492 } else {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2493 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2494 context->address = (context->address &0xC000) \| (value & 0x3FFF);
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2495 context->cd = (context->cd & 0x3C) \| (value >> 14);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2496 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2497 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2498 uint8_t reg = (value >> 8) & 0x1F;
1123 d5412f76accc Fix inactive start line for Mode 4 in vdp_next_hint. Fix an off by one error in the range of registers allowed to be written in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1122 diff changeset	2499 if (reg < (mode_5 ? VDP_REGS : 0xB)) {
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	2500 //printf("register %d set to %X\n", reg, value & 0xFF);
480 0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	2501 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) {
1154 c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2502 vdp_latch_hv(context);
480 0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	2503 }
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	2504 if (reg == REG_BG_COLOR) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	2505 value &= 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	2506 }
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	2507 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2508 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame);
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	2509 }*/
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2510 context->regs[reg] = value;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2511 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2512 context->double_res = (value & (BIT_INTERLACE \| BIT_DOUBLE_RES)) == (BIT_INTERLACE \| BIT_DOUBLE_RES);
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	2513 if (!context->double_res) {
1106 cacbd3f18f03 Fix field flag handling bug introduced with VDP/render interface cleanup Michael Pavone <pavone@retrodev.com> parents: 1103 diff changeset	2514 context->flags2 &= ~FLAG2_EVEN_FIELD;
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	2515 }
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2516 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2517 if (reg == REG_MODE_2) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2518 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2519 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2520 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2521 } else if (mode_5) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2522 context->flags \|= FLAG_PENDING;
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2523 //Should these be taken care of here or after the second write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2524 //context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2525 //context->flags2 &= ~FLAG2_READ_PENDING;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2526 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2527 context->flags &= ~FLAG_READ_FETCHED;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2528 context->flags2 &= ~FLAG2_READ_PENDING;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2529 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2530 }
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2531 return 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2532 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2533
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2534 void vdp_control_port_write_pbc(vdp_context *context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2535 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2536 if (context->flags2 & FLAG2_BYTE_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2537 uint16_t full_val = value << 8 \| context->pending_byte;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2538 context->flags2 &= ~FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2539 //TODO: Deal with fact that Vbus->VDP DMA doesn't do anything in PBC mode
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2540 vdp_control_port_write(context, full_val);
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2541 if (context->cd == VRAM_READ) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2542 context->cd = VRAM_READ8;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2543 }
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2544 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2545 context->pending_byte = value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2546 context->flags2 \|= FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2547 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2548 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2549
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2550 int vdp_data_port_write(vdp_context * context, uint16_t value)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2551 {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2552 //printf("data port write: %X at %d\n", value, context->cycles);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2553 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2554 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2555 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2556 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2557 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2558 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2559 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2560 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2561 }
109 004dd46e0a97 COmment out fifo full debug printf Mike Pavone <pavone@retrodev.com> parents: 108 diff changeset	2562 /*if (context->fifo_cur == context->fifo_end) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2563 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109 004dd46e0a97 COmment out fifo full debug printf Mike Pavone <pavone@retrodev.com> parents: 108 diff changeset	2564 }*/
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2565 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2566 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2567 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2568 while (context->fifo_write == context->fifo_read) {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2569 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2570 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2571 fifo_entry * cur = context->fifo + context->fifo_write;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2572 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2573 cur->address = context->address;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2574 cur->value = value;
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2575 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2576 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2577 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2578 cur->cd = (context->cd & 2) \| 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2579 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2580 cur->partial = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2581 if (context->fifo_read < 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2582 context->fifo_read = context->fifo_write;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2583 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2584 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2585 increment_address(context);
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2586 return 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2587 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2588
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2589 void vdp_data_port_write_pbc(vdp_context * context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2590 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2591 if (context->flags & FLAG_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2592 context->flags &= ~FLAG_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2593 //Should these be cleared here?
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2594 context->flags &= ~FLAG_READ_FETCHED;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2595 context->flags2 &= ~FLAG2_READ_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2596 }
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2597 context->flags2 &= ~FLAG2_BYTE_PENDING;
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2598 /*if (context->fifo_cur == context->fifo_end) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2599 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2600 }*/
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2601 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2602 context->flags &= ~FLAG_DMA_RUN;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2603 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2604 while (context->fifo_write == context->fifo_read) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2605 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2606 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2607 fifo_entry * cur = context->fifo + context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2608 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2609 cur->address = context->address;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2610 cur->value = value;
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2611 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2612 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2613 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2614 cur->cd = (context->cd & 2) \| 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2615 }
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2616 cur->partial = 1;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2617 if (context->fifo_read < 0) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2618 context->fifo_read = context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2619 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2620 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2621 increment_address(context);
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2622 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2623
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2624 void vdp_test_port_write(vdp_context * context, uint16_t value)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2625 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2626 //TODO: implement test register
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2627 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2628
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2629 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2630 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2631 context->flags &= ~FLAG_PENDING;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2632 context->flags2 &= ~FLAG2_BYTE_PENDING;
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2633 //Bits 15-10 are not fixed like Charles MacDonald's doc suggests, but instead open bus values that reflect 68K prefetch
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2634 uint16_t value = context->system->get_open_bus_value(context->system) & 0xFC00;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2635 if (context->fifo_read < 0) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2636 value \|= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2637 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2638 if (context->fifo_read == context->fifo_write) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2639 value \|= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2640 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2641 if (context->flags2 & FLAG2_VINT_PENDING) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2642 value \|= 0x80;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2643 }
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2644 if (context->flags & FLAG_DOT_OFLOW) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2645 value \|= 0x40;
1156 b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	2646 context->flags &= ~FLAG_DOT_OFLOW;
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2647 }
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2648 if (context->flags2 & FLAG2_SPRITE_COLLIDE) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2649 value \|= 0x20;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2650 context->flags2 &= ~FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2651 }
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	2652 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && !(context->flags2 & FLAG2_EVEN_FIELD)) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2653 value \|= 0x10;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2654 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2655 uint32_t line= context->vcounter;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2656 uint32_t slot = context->hslot;
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2657 if ((line >= context->inactive_start && line < 0x1FF) \|\| !(context->regs[REG_MODE_2] & BIT_DISP_EN)) {
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	2658 value \|= 0x8;
789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	2659 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2660 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2661 if (slot < HBLANK_END_H40 \|\| slot > HBLANK_START_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2662 value \|= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2663 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2664 } else {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2665 if (slot < HBLANK_END_H32 \|\| slot > HBLANK_START_H32) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2666 value \|= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2667 }
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	2668 }
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2669 if (context->cd & 0x20) {
141 576f55711d8d Fix DMA in progress flag in VDP status register Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	2670 value \|= 0x2;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2671 }
714 e29bc2918f69 Fix VDP status register PAL bit based on observations of the Titan Overdrive demo Michael Pavone <pavone@retrodev.com> parents: 711 diff changeset	2672 if (context->flags2 & FLAG2_REGION_PAL) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2673 value \|= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2674 }
459 c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2675 //printf("status read at cycle %d returned %X\n", context->cycles, value);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2676 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2677 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2678
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2679 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2680 {
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2681 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2682 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2683 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2684 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2685 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2686 }
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	2687 if (context->cd & 1) {
991 f9ee6f746cb4 Properly emulate machine freeze when reading from VDP while configured for writes Michael Pavone <pavone@retrodev.com> parents: 984 diff changeset	2688 warning("Read from VDP data port while writes are configured, CPU is now frozen. VDP Address: %X, CD: %X\n", context->address, context->cd);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2689 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2690 while (!(context->flags & FLAG_READ_FETCHED)) {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2691 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2692 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2693 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2694 return context->prefetch;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2695 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2696
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2697 uint8_t vdp_data_port_read_pbc(vdp_context * context)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2698 {
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2699 context->flags &= ~(FLAG_PENDING \| FLAG_READ_FETCHED);
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2700 context->flags2 &= ~FLAG2_BYTE_PENDING;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2701
1152 ddbb61be6119 Fix to pass a couple more tests in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1151 diff changeset	2702 context->cd = VRAM_READ8;
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2703 return context->prefetch;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2704 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2705
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2706 uint16_t vdp_test_port_read(vdp_context * context)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2707 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2708 //TODO: Find out what actually gets returned here
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2709 return 0xFFFF;
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2710 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2711
65 aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2712 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2713 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2714 context->cycles -= deduction;
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2715 if (context->pending_vint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2716 context->pending_vint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2717 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2718 context->pending_vint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2719 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2720 if (context->pending_hint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2721 context->pending_hint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2722 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2723 context->pending_hint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2724 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2725 if (context->fifo_read >= 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2726 int32_t idx = context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2727 do {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2728 if (context->fifo[idx].cycle >= deduction) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2729 context->fifo[idx].cycle -= deduction;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2730 } else {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2731 context->fifo[idx].cycle = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2732 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2733 idx = (idx+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2734 } while(idx != context->fifo_write);
65 aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2735 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2736 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2737
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	2738 static uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context)
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2739 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2740 if (context->hslot < 183) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2741 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2742 } else if (context->hslot < HSYNC_END_H40) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2743 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2744 uint32_t hsync = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2745 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2746 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2747 hsync += h40_hsync_cycles[i];
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2748 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2749 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2750 return before_hsync + hsync + after_hsync;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2751 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2752 return (256-context->hslot) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2753 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2754 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2755
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	2756 static uint32_t vdp_cycles_next_line(vdp_context * context)
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2757 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2758 if (context->regs[REG_MODE_4] & BIT_H40) {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2759 //TODO: Handle "illegal" Mode 4/H40 combo
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	2760 if (context->hslot < LINE_CHANGE_H40) {
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	2761 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2762 } else {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2763 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2764 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2765 } else {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2766 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2767 if (context->hslot < LINE_CHANGE_H32) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2768 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2769 } else if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2770 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2771 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2772 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2773 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2774 } else {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2775 if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2776 return (148 - context->hslot + LINE_CHANGE_MODE4 - 233) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2777 } else if (context->hslot < LINE_CHANGE_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2778 return (LINE_CHANGE_MODE4 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2779 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2780 return MCLKS_LINE - (context->hslot - LINE_CHANGE_MODE4) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2781 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2782 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2783 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2784 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2785
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	2786 static uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target)
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2787 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2788 uint32_t jump_start, jump_dst;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2789 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2790 if (context->flags2 & FLAG2_REGION_PAL) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2791 if (context->latched_mode & BIT_PAL) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2792 jump_start = 0x10B;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2793 jump_dst = 0x1D2;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2794 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2795 jump_start = 0x103;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2796 jump_dst = 0x1CA;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2797 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2798 } else {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2799 if (context->latched_mode & BIT_PAL) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2800 jump_start = 0;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2801 jump_dst = 0;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2802 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2803 jump_start = 0xEB;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2804 jump_dst = 0x1E5;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2805 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2806 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2807 } else {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2808 jump_start = 0xDB;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2809 jump_dst = 0x1D5;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2810 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2811 uint32_t lines;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2812 if (context->vcounter < target) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2813 if (target < jump_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2814 lines = target - context->vcounter;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2815 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2816 lines = jump_start - context->vcounter + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2817 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2818 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2819 if (context->vcounter < jump_start) {
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	2820 lines = jump_start - context->vcounter + 512 - jump_dst;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2821 } else {
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	2822 lines = 512 - context->vcounter;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2823 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2824 if (target < jump_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2825 lines += target;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2826 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2827 lines += jump_start + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2828 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2829 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2830 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context);
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2831 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2832
680 4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	2833 uint32_t vdp_cycles_to_frame_end(vdp_context * context)
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	2834 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2835 return context->cycles + vdp_cycles_to_line(context, context->inactive_start);
680 4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	2836 }
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	2837
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2838 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2839 {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2840 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2841 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2842 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2843 if (context->flags2 & FLAG2_HINT_PENDING) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2844 return context->pending_hint_start;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2845 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2846 uint32_t hint_line;
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2847 if (context->vcounter + context->hint_counter >= context->inactive_start) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2848 if (context->regs[REG_HINT] > context->inactive_start) {
724 2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display Michael Pavone <pavone@retrodev.com> parents: 722 diff changeset	2849 return 0xFFFFFFFF;
2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display Michael Pavone <pavone@retrodev.com> parents: 722 diff changeset	2850 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2851 hint_line = context->regs[REG_HINT];
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2852 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2853 hint_line = context->vcounter + context->hint_counter + 1;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2854 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2855
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2856 return context->cycles + vdp_cycles_to_line(context, hint_line);
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2857 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2858
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2859 static uint32_t vdp_next_vint_real(vdp_context * context)
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2860 {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2861 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2862 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2863 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2864 if (context->flags2 & FLAG2_VINT_PENDING) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2865 return context->pending_vint_start;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2866 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2867
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2868
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2869 return vdp_next_vint_z80(context);
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2870 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2871
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2872 uint32_t vdp_next_vint(vdp_context *context)
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2873 {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2874 uint32_t ret = vdp_next_vint_real(context);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2875 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2876 static uint32_t last = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2877 if (last != ret) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2878 printf("vdp_next_vint is %d at frame %d, line %d, hslot %d\n", ret, context->frame, context->vcounter, context->hslot);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2879 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2880 last = ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2881 #endif
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2882 return ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2883 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2884
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2885 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2886 {
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2887 uint16_t vint_line = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->inactive_start : context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2888 if (context->vcounter == vint_line) {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2889 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2890 if (context->regs[REG_MODE_4] & BIT_H40) {
1175 0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2891 if (context->hslot >= LINE_CHANGE_H40 \|\| context->hslot <= VINT_SLOT_H40) {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2892 uint32_t cycles = context->cycles;
1175 0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2893 if (context->hslot >= LINE_CHANGE_H40) {
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2894 if (context->hslot < 183) {
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2895 cycles += (183 - context->hslot) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2896 }
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2897
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2898 if (context->hslot < HSYNC_SLOT_H40) {
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2899 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2900 }
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2901 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ )
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2902 {
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2903 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2904 }
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2905 cycles += (256 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2906 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2907
1175 0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2908 cycles += (VINT_SLOT_H40 - (context->hslot >= LINE_CHANGE_H40 ? 0 : context->hslot)) * MCLKS_SLOT_H40;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2909 return cycles;
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	2910 }
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2911 } else {
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2912 if (context->hslot >= LINE_CHANGE_H32 \|\| context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2913 if (context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2914 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32;
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2915 } else if (context->hslot < 233) {
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2916 return context->cycles + (VINT_SLOT_H32 + 256 - 233 + 148 - context->hslot) * MCLKS_SLOT_H32;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2917 } else {
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2918 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2919 }
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	2920 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2921 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2922 } else {
1177 67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency Michael Pavone <pavone@retrodev.com> parents: 1175 diff changeset	2923 if (context->hslot >= LINE_CHANGE_MODE4) {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2924 return context->cycles + (VINT_SLOT_MODE4 + 256 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2925 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2926 if (context->hslot <= VINT_SLOT_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2927 return context->cycles + (VINT_SLOT_MODE4 - context->hslot) * MCLKS_SLOT_H32;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2928 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2929 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2930 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2931 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line);
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2932 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2933 if (context->regs[REG_MODE_4] & BIT_H40) {
1175 0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	2934 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2935 } else {
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2936 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2937 }
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2938 } else {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2939 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32;
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2940 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2941 return context->cycles + cycles_to_vint;
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2942 }
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	2943
953 08346262990b Remove the int number argument to vdp_int_ack since it is no longer used Michael Pavone <pavone@retrodev.com> parents: 952 diff changeset	2944 void vdp_int_ack(vdp_context * context)
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2945 {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2946 //CPU interrupt acknowledge is only used in Mode 5
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2947 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2948 //Apparently the VDP interrupt controller is not very smart
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2949 //Instead of paying attention to what interrupt is being acknowledged it just
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2950 //clears the pending flag for whatever interrupt it is currently asserted
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2951 //which may be different from the interrupt it was asserting when the 68k
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2952 //started the interrupt process. The window for this is narrow and depends
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2953 //on the latency between the int enable register write and the interrupt being
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2954 //asserted, but Fatal Rewind depends on this due to some buggy code
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2955 if ((context->flags2 & FLAG2_VINT_PENDING) && (context->regs[REG_MODE_2] & BIT_VINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2956 context->flags2 &= ~FLAG2_VINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2957 } else if((context->flags2 & FLAG2_HINT_PENDING) && (context->regs[REG_MODE_1] & BIT_HINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2958 context->flags2 &= ~FLAG2_HINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2959 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2960 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2961 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2962

Mercurial > repos > blastem

annotate vdp.c @ 1299:da1ffc4026c4