repos/blastem: z80_to_x86.c annotate

annotate z80_to_x86.c @ 1086:f0a1e0a2263c

Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement

author	Michael Pavone <pavone@retrodev.com>
date	Thu, 06 Oct 2016 22:25:12 -0700
parents	779acbfb74d0
children	d1eed3b1121c

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	2 Copyright 2013 Michael Pavone
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	5 */
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	6 #include "z80inst.h"
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "z80_to_x86.h"
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include "gen_x86.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	9 #include "mem.h"
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	10 #include "util.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	11 #include <stdio.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	12 #include <stdlib.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	13 #include <stddef.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	14 #include <string.h>
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	15
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 #define MODE_UNUSED (MODE_IMMED-1)
854 adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	17 #define MAX_MCYCLE_LENGTH 6
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	18
315 684e71e9f0d0 Fix return address for RST Mike Pavone <pavone@retrodev.com> parents: 314 diff changeset	19 //#define DO_DEBUG_PRINT
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	20
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	21 #ifdef DO_DEBUG_PRINT
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	22 #define dprintf printf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	23 #else
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	24 #define dprintf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	25 #endif
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	26
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	27 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst);
715 1c2020d3e275 Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly Michael Pavone <pavone@retrodev.com> parents: 712 diff changeset	28 void z80_handle_deferred(z80_context * context);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	29
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	30 uint8_t z80_size(z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 uint8_t reg = (inst->reg & 0x1F);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	33 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	34 return reg < Z80_BC ? SZ_B : SZ_W;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	35 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 //TODO: Handle any necessary special cases
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 return SZ_B;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	39
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	40 uint8_t zf_off(uint8_t flag)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	41 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	42 return offsetof(z80_context, flags) + flag;
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	43 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	44
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	45 uint8_t zaf_off(uint8_t flag)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	46 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	47 return offsetof(z80_context, alt_flags) + flag;
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	48 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	49
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	50 uint8_t zr_off(uint8_t reg)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	51 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	52 if (reg > Z80_A) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	53 reg = z80_low_reg(reg);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	54 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	55 return offsetof(z80_context, regs) + reg;
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	56 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	57
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	58 uint8_t zar_off(uint8_t reg)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	59 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	60 if (reg > Z80_A) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	61 reg = z80_low_reg(reg);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	62 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	63 return offsetof(z80_context, alt_regs) + reg;
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	64 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	65
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	66 void zreg_to_native(z80_options *opts, uint8_t reg, uint8_t native_reg)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	67 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	68 if (opts->regs[reg] >= 0) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	69 mov_rr(&opts->gen.code, opts->regs[reg], native_reg, reg > Z80_A ? SZ_W : SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	70 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	71 mov_rdispr(&opts->gen.code, opts->gen.context_reg, zr_off(reg), native_reg, reg > Z80_A ? SZ_W : SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	72 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	73 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	74
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	75 void native_to_zreg(z80_options *opts, uint8_t native_reg, uint8_t reg)
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	76 {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	77 if (opts->regs[reg] >= 0) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	78 mov_rr(&opts->gen.code, native_reg, opts->regs[reg], reg > Z80_A ? SZ_W : SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	79 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	80 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, zr_off(reg), reg > Z80_A ? SZ_W : SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	81 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	82 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	83
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	84 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts)
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	85 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	86 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 if (inst->reg == Z80_USE_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	89 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 ea->mode = MODE_UNUSED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 } else {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	93 ea->mode = MODE_REG_DIRECT;
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	94 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	95 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	96 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	97 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	98 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	99 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	100 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	101 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	102 }
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	103 } else if(opts->regs[inst->reg] >= 0) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	104 ea->base = opts->regs[inst->reg];
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	105 if (ea->base >= AH && ea->base <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	106 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	107 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	108 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	109 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	110 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	111 ror_ir(code, 8, ea->base, SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	112 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	113 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	114 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	115 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	116 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	117 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	118 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	120 ea->mode = MODE_REG_DISPLACE8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	121 ea->base = opts->gen.context_reg;
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	122 ea->disp = zr_off(inst->reg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	123 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	126
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	127 void z80_save_reg(z80inst * inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	129 code_info *code = &opts->gen.code;
716 b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo Michael Pavone <pavone@retrodev.com> parents: 715 diff changeset	130 if (inst->reg == Z80_USE_IMMED \|\| inst->reg == Z80_UNUSED) {
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo Michael Pavone <pavone@retrodev.com> parents: 715 diff changeset	131 return;
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo Michael Pavone <pavone@retrodev.com> parents: 715 diff changeset	132 }
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	133 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	134 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	135 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	136 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	137 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	138 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	139 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	140 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	141 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	142 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	143 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	144 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	145 //we can't mix an *H reg with a register that requires the REX prefix
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	146 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	147 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	148 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	149 //temp regs require REX prefix too
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	150 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	151 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	153 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	154
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	155 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	157 code_info *code = &opts->gen.code;
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	158 uint8_t size, areg;
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	159 int8_t reg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	160 ea->mode = MODE_REG_DIRECT;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	161 areg = read ? opts->gen.scratch1 : opts->gen.scratch2;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	164 case Z80_REG:
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	165 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	166 if (inst->reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	167 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	168 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	169 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	170 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	171 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	172 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	173 }
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	174 } else if(opts->regs[inst->ea_reg] >= 0) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 ea->base = opts->regs[inst->ea_reg];
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	176 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	177 uint8_t other_reg = opts->regs[inst->reg];
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	178 #ifdef X86_64
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	179 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	180 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	181 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	182 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	183 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	184 #endif
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	185 }
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	186 } else {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	187 ea->mode = MODE_REG_DISPLACE8;
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	188 ea->base = opts->gen.context_reg;
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	189 ea->disp = zr_off(inst->ea_reg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 case Z80_REG_INDIRECT:
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	193 zreg_to_native(opts, inst->ea_reg, areg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	197 //push_r(code, opts->gen.scratch1);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	198 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 if (size == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	201 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	203 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	206 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 case Z80_IMMED_INDIRECT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	213 mov_ir(code, inst->immed, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	214 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 if (read) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	216 /*if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	217 push_r(code, opts->gen.scratch1);
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	218 }*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	219 if (size == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	220 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	222 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	225 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	227 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	228 case Z80_IY_DISPLACE:
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	229 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, areg);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	230 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	234 //push_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	235 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	237 if (size == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	238 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	240 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	243 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 case Z80_UNUSED:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	246 ea->mode = MODE_UNUSED;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 default:
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	249 fatal_error("Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	250 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	252
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	253 void z80_save_ea(code_info code, z80inst inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	255 if ((inst->addr_mode & 0x1F) == Z80_REG) {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	256 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	257 if (inst->reg == Z80_IYL) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	258 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	259 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	260 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	261 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	262 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	263 }
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	264 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	265 uint8_t other_reg = opts->regs[inst->reg];
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	266 #ifdef X86_64
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	267 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	268 //we can't mix an *H reg with a register that requires the REX prefix
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	269 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	270 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	271 #endif
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	272 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	274 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	275
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	276 void z80_save_result(z80_options opts, z80inst inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 {
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	278 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	279 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	280 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	281 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	282 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	283 case Z80_IY_DISPLACE:
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	284 if (inst->op != Z80_LD) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	285 mov_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	286 }
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	287 if (z80_size(inst) == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	288 call(&opts->gen.code, opts->write_8);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	289 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	290 call(&opts->gen.code, opts->write_16_lowfirst);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	291 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	294
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	299
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	301 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	303 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	304
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	305 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	306 {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	307 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	308 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	309 context->regs[Z80_D], context->regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	310 (context->regs[Z80_H] << 8) \| context->regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	311 (context->regs[Z80_IXH] << 8) \| context->regs[Z80_IXL],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	312 (context->regs[Z80_IYH] << 8) \| context->regs[Z80_IYL],
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	313 context->sp, context->im, context->iff1, context->iff2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	314 puts("--Alternate Regs--");
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	315 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	316 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	317 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	318 (context->alt_regs[Z80_H] << 8) \| context->alt_regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	319 (context->alt_regs[Z80_IXH] << 8) \| context->alt_regs[Z80_IXL],
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	320 (context->alt_regs[Z80_IYH] << 8) \| context->alt_regs[Z80_IYL]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	321 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	322 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	323
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	324 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	325 {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	326 uint32_t num_cycles;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	327 host_ea src_op, dst_op;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	328 uint8_t size;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	329 z80_options *opts = context->options;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	330 uint8_t * start = opts->gen.code.cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	331 code_info *code = &opts->gen.code;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	332 if (!interp) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	333 check_cycles_int(&opts->gen, address);
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	334 if (context->breakpoint_flags[address / 8] & (1 << (address % 8))) {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	335 zbreakpoint_patch(context, address, start);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	336 }
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	337 num_cycles = 4 * inst->opcode_bytes;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	338 add_ir(code, inst->opcode_bytes > 1 ? 2 : 1, opts->regs[Z80_R], SZ_B);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	339 #ifdef Z80_LOG_ADDRESS
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	340 log_address(&opts->gen, address, "Z80: %X @ %d\n");
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	341 #endif
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	342 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	343 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	344 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	345 case Z80_LD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	346 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	347 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	348 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	349 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	350 case Z80_REG_INDIRECT:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	351 if (size != SZ_B) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	352 num_cycles += 2;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	353 }
841 58606d16d35c Fix timing of certain variants of LD Michael Pavone <pavone@retrodev.com> parents: 840 diff changeset	354 if (inst->reg == Z80_I \|\| inst->ea_reg == Z80_I \|\| inst->reg == Z80_R \|\| inst->ea_reg == Z80_R) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	355 num_cycles += 1;
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	356 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	357 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	358 case Z80_IMMED:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	359 num_cycles += size == SZ_B ? 3 : 6;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	360 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	361 case Z80_IMMED_INDIRECT:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	362 num_cycles += 6;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	363 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	364 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	365 case Z80_IY_DISPLACE:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	366 num_cycles = 8; //3 for displacement, 5 for address addition
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	367 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	368 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	369 cycles(&opts->gen, num_cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	370 if (inst->addr_mode & Z80_DIR) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	371 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	372 translate_z80_reg(inst, &src_op, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	373 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	374 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	375 translate_z80_reg(inst, &dst_op, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 }
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	377 if (inst->reg == Z80_R) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	378 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	379 mov_rr(code, opts->regs[Z80_A], opts->regs[Z80_R], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	380 and_ir(code, 0x80, opts->gen.scratch1, SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	381 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zr_off(Z80_R), SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	382 } else if (inst->ea_reg == Z80_R && inst->addr_mode == Z80_REG) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	383 mov_rr(code, opts->regs[Z80_R], opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	384 and_ir(code, 0x7F, opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	385 or_rdispr(code, opts->gen.context_reg, zr_off(Z80_R), opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	386 } else if (src_op.mode == MODE_REG_DIRECT) {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	387 if(dst_op.mode == MODE_REG_DISPLACE8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	388 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	389 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	390 mov_rr(code, src_op.base, dst_op.base, size);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	391 }
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	392 } else if(src_op.mode == MODE_IMMED) {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	393 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	394 mov_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	395 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	396 mov_ir(code, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	397 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	398 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	399 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	400 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	401 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	402 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	403 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	404 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	405 }
842 ba93a3941300 Set flags for ld a, r Michael Pavone <pavone@retrodev.com> parents: 841 diff changeset	406 if ((inst->ea_reg == Z80_I \|\| inst->ea_reg == Z80_R) && inst->addr_mode == Z80_REG) {
ba93a3941300 Set flags for ld a, r Michael Pavone <pavone@retrodev.com> parents: 841 diff changeset	407 //ld a, i and ld a, r sets some flags
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	408 cmp_ir(code, 0, dst_op.base, SZ_B);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	409 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	410 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
821 21a69dfb6ee7 Implement half carry for a couple of the trivial cases Michael Pavone <pavone@retrodev.com> parents: 819 diff changeset	411 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	412 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);;
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	413 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	414 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	415 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	416 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	417 z80_save_ea(code, inst, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	418 if (inst->addr_mode & Z80_DIR) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	419 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	420 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	422 case Z80_PUSH:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	423 cycles(&opts->gen, num_cycles + 1);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	424 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	425 if (inst->reg == Z80_AF) {
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	426 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	427 shl_ir(code, 8, opts->gen.scratch1, SZ_W);
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	428 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	429 and_ir(code, 0x28, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	430 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	431 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	432 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	433 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	434 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	435 ror_ir(code, 2, opts->gen.scratch1, SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	436 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B);
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	437 ror_ir(code, 2, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	438 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	439 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	440 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	441 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	442 } else {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	443 zreg_to_native(opts, inst->reg, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	444 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	445 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	446 call(code, opts->write_16_highfirst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	447 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	448 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	449 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	450 case Z80_POP:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	451 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	452 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	453 call(code, opts->read_16);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	454 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	455 if (inst->reg == Z80_AF) {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	456
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	457 bt_ir(code, 0, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	458 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	459 bt_ir(code, 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	460 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	461 bt_ir(code, 2, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	462 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	463 bt_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	464 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	465 bt_ir(code, 6, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	466 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	467 bt_ir(code, 7, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	468 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S));
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	469 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	470 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	471 native_to_zreg(opts, opts->gen.scratch1, Z80_A);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	472 } else {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	473 native_to_zreg(opts, opts->gen.scratch1, inst->reg);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	474 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	475 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	476 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	477 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	478 case Z80_EX:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	479 cycles(&opts->gen, num_cycles);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	480 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	481 if(inst->reg == Z80_AF) {
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	482 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	483 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->gen.scratch2, SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	484 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	485 native_to_zreg(opts, opts->gen.scratch2, Z80_A);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	486
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	487 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	488 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	489 for (int f = ZF_C; f < ZF_NUM; f+=2) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	490 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	491 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	492 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	493 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	494 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	495 } else {
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	496 if (opts->regs[Z80_DE] >= 0 && opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	497 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	498 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	499 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	500 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	501 native_to_zreg(opts, opts->gen.scratch1, Z80_HL);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	502 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	503 }
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	504 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	505 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	506 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	507 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	508 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	509 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	510 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	511 zreg_to_native(opts, inst->reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	512 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	513 native_to_zreg(opts, opts->gen.scratch2, inst->reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	514 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	515 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	516 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	517 cycles(&opts->gen, 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	518 uint8_t high_reg = z80_high_reg(inst->reg);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	519 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	520 add_ir(code, 1, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	521 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	522 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	523 //even though some of the upper halves can be used directly
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	524 //the limitations on mixing *H regs with the REX prefix
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	525 //prevent us from taking advantage of it
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	526 uint8_t use_reg = opts->regs[inst->reg];
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	527 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	528 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	529 //restore reg to normal rotation
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	530 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	531 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	532 zreg_to_native(opts, high_reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	533 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	534 native_to_zreg(opts, opts->gen.scratch2, high_reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	535 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	536 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	537 add_ir(code, 1, opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	538 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	539 cycles(&opts->gen, 2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	540 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	541 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	542 case Z80_EXX:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	543 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	544 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	545 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	546 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	547 native_to_zreg(opts, opts->gen.scratch2, Z80_BC);
840 5822c6e5642f Fix timing of IM instruction Michael Pavone <pavone@retrodev.com> parents: 828 diff changeset	548
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	549 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	550 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	551 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	552 native_to_zreg(opts, opts->gen.scratch2, Z80_HL);
840 5822c6e5642f Fix timing of IM instruction Michael Pavone <pavone@retrodev.com> parents: 828 diff changeset	553
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	554 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	555 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	556 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	557 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	558 break;
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	559 case Z80_LDI: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	560 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	561 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	562 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	563 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052 366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	564 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	565 call(code, opts->write_8);
1052 366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	566 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	567 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	568 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	569 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	570 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	571 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	572 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	573 cycles(&opts->gen, 2);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	574 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	575 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	576 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	577 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	578 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	579 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	580 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	581 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	582 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	583 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	584 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	585 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	586 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	587 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	588 }
821 21a69dfb6ee7 Implement half carry for a couple of the trivial cases Michael Pavone <pavone@retrodev.com> parents: 819 diff changeset	589 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	590 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	591 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	592 break;
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	593 }
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	594 case Z80_LDIR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	595 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	596 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	597 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	598 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052 366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	599 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	600 call(code, opts->write_8);
1052 366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	601 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	602 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	603 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	604 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	605 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	606 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	607 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	608 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	609 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	610 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	611 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	612 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	613 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	614 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	615 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	616 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	617 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	618 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	619 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	620 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	621 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	622 }
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	623 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	624 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	625 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	626 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	627 cycles(&opts->gen, 7);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	628 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	629 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	630 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	631 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	632 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	633 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	634 }
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	635 case Z80_LDD: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	636 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	637 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	638 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	639 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052 366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	640 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	641 call(code, opts->write_8);
1052 366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	642 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	643 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	644 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	645 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	646 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	647 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	648 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	649 cycles(&opts->gen, 2);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	650 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	651 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	652 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	653 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	654 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	655 if (opts->regs[Z80_HL] >= 0) {
828 22c3c52b9871 Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions. Michael Pavone <pavone@retrodev.com> parents: 821 diff changeset	656 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	657 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	658 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	659 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	660 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	661 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	662 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	663 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	664 }
821 21a69dfb6ee7 Implement half carry for a couple of the trivial cases Michael Pavone <pavone@retrodev.com> parents: 819 diff changeset	665 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	666 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	667 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	668 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	669 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	670 case Z80_LDDR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	671 cycles(&opts->gen, num_cycles);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	672 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	673 call(code, opts->read_8);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	674 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052 366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	675 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	676 call(code, opts->write_8);
1052 366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	677 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	678 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	679 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	680 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	681 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	682 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions Michael Pavone <pavone@retrodev.com> parents: 1051 diff changeset	683 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	684 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	685 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	686 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	687 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	688 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	689 if (opts->regs[Z80_HL] >= 0) {
828 22c3c52b9871 Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions. Michael Pavone <pavone@retrodev.com> parents: 821 diff changeset	690 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	691 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	692 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	693 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	694 if (opts->regs[Z80_BC] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	695 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	696 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	697 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	698 }
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	699 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	700 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	701 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	702 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	703 cycles(&opts->gen, 7);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	704 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	705 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	706 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	707 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	708 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	709 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	710 }
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	711 case Z80_CPI:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	712 cycles(&opts->gen, num_cycles);//T-States 4,4
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	713 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	714 call(code, opts->read_8);//T-States 3
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	715 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	716 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	717 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	718 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	719 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	720 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	721 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	722 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	723 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	724 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	725 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	726 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	727 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	728 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	729 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	730 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	731 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	732 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	733 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	734 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	735 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
1051 11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	736 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	737 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	738 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	739 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	740 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	741 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	742 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	743 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	744 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	745 case Z80_CPIR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	746 cycles(&opts->gen, num_cycles);//T-States 4,4
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	747 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	748 call(code, opts->read_8);//T-States 3
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	749 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	750 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	751 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	752 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	753 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	754 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	755 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	756 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	757 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	758 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	759 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	760 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	761 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	762 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	763 }
1051 11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	764 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	765 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	766 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	767 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	768 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	769 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	770 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	771 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	772 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	773 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	774 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	775 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	776 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	777 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	778 uint8_t * cont = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	779 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	780 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	781 uint8_t * cont2 = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	782 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	783 //repeat case
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	784 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	785 jmp(code, start);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	786 *cont = code->cur - (cont + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	787 *cont2 = code->cur - (cont2 + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	788 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	789 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	790 case Z80_CPD:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	791 cycles(&opts->gen, num_cycles);//T-States 4,4
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	792 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	793 call(code, opts->read_8);//T-States 3
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	794 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	795 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	796 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	797 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	798 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	799 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	800 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	801 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	802 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	803 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	804 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	805 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	806 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	807 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	808 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	809 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	810 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	811 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	812 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	813 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	814 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
1051 11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	815 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	816 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	817 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	818 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	819 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	820 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	821 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	822 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	823 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	824 case Z80_CPDR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	825 cycles(&opts->gen, num_cycles);//T-States 4,4
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	826 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	827 call(code, opts->read_8);//T-States 3
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	828 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	829 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	830 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	831 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	832 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	833 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	834 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	835 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	836 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	837 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	838 if (opts->regs[Z80_HL] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	839 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	840 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	841 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	842 }
1051 11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	843 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	844 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	845 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	846 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	847 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	848 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	849 and_ir(code, 0x20, opts->gen.scratch2, SZ_B);
11ff5726fd5e Implement undocumented flag bits for block CP instructions Michael Pavone <pavone@retrodev.com> parents: 1050 diff changeset	850 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1043 3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	851 if (opts->regs[Z80_BC] >= 0) {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	852 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	853 } else {
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	854 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	855 }
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	856 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	857 uint8_t * cont = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	858 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	859 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	860 uint8_t * cont2 = code->cur+1;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	861 jcc(code, CC_Z, code->cur+2);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	862 //repeat case
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	863 cycles(&opts->gen, 5);//T-States 5
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	864 jmp(code, start);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	865 *cont = code->cur - (cont + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	866 *cont2 = code->cur - (cont2 + 1);
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	867 break;
3980ef0f6307 Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through. Michael Pavone <pavone@retrodev.com> parents: 1042 diff changeset	868 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	869 case Z80_ADD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	870 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	871 num_cycles += 8;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	872 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	873 num_cycles += 3;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	874 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	875 num_cycles += 4;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	876 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	877 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	878 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	879 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	880 if (dst_op.mode == MODE_REG_DIRECT) {
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	881 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	882 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	883 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	884 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	885 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	886 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	887 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	888 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	889 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	890 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	891 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	892 if (dst_op.mode == MODE_REG_DIRECT) {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	893 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	894 add_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	895 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	896 add_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	897 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	898 add_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	899 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	900 if (z80_size(inst) == SZ_B) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	901 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	902 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	903 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	904 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	905 add_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	906 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	907 add_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	908 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	909 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	910 add_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	911 }
1057 ff46d8fc2de8 Fix handling of undocumented flag bits for ADD in 32-bit builds Michael Pavone <pavone@retrodev.com> parents: 1056 diff changeset	912 mov_rdispr(code, dst_op.base, dst_op.disp + (z80_size(inst) == SZ_B ? 0 : 1), opts->gen.scratch1, SZ_B);
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	913 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	914 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	915 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	916 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	917 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	918 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	919 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	920 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	921 }
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	922 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	923 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	924 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	925 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	926 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	927 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	928 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	929 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	930 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	931 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	932 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	933 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	934 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	935 z80_save_ea(code, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	936 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	937 case Z80_ADC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	938 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	939 num_cycles += 8;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	940 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	941 num_cycles += 3;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	942 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	943 num_cycles += 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	944 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	945 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	946 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	947 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	948 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	949 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	950 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	951 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	952 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	953 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	954 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	955 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	956 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	957 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	958 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	959 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	960 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	961 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	962 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	963 adc_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	964 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	965 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	966 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	967 adc_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	968 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	969 if (z80_size(inst) == SZ_B) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	970 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	971 }
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	972 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	973 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	974 adc_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	975 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	976 adc_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	977 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	978 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	979 adc_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	980 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	981 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	982 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	983 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	984 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	985 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	986 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	987 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	988 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	989 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	990 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	991 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	992 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	993 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	994 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	995 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	996 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	997 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	998 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	999 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1000 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1001 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1002 z80_save_ea(code, inst, opts);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1003 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1004 case Z80_SUB:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1005 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1006 num_cycles += 8;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1007 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1008 num_cycles += 3;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1009 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1010 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1011 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1012 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1013 if (dst_op.mode == MODE_REG_DIRECT) {
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1014 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1015 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1016 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1017 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1018 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1019 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1020 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1021 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1022 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1023 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1024 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1025 if (dst_op.mode == MODE_REG_DIRECT) {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1026 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1027 sub_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1028 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1029 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1030 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1031 sub_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1032 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1033 if (z80_size(inst) == SZ_B) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1034 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1035 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1036 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1037 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1038 sub_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1039 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1040 sub_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1041 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1042 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1043 sub_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1044 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1045 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1046 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1047 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1048 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1049 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1050 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1051 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1052 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1053 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1054 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1055 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1056 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1057 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1058 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1059 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1060 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1061 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1062 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1063 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1064 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1065 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1066 z80_save_ea(code, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1067 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1068 case Z80_SBC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1069 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1070 num_cycles += 8;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1071 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1072 num_cycles += 3;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1073 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1074 num_cycles += 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1075 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1076 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1077 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1078 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1079 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1080 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1081 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1082 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1083 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1084 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1085 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1086 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1087 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1088 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1089 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1090 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1091 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1092 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1093 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1094 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1095 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1096 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1097 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1098 sbb_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1099 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1100 if (z80_size(inst) == SZ_B) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1101 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1102 }
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1103 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1104 if (src_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1105 sbb_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1106 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1107 sbb_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1108 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1109 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1110 sbb_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1111 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1112 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1113 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1114 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1115 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1116 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1117 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1118 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1119 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1120 if (dst_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1121 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1122 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1123 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1124 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1125 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1126 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1127 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1128 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1129 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1130 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1131 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1132 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1133 z80_save_ea(code, inst, opts);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1134 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1135 case Z80_AND:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1136 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1137 num_cycles += 8;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1138 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1139 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1140 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1141 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1142 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1143 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1144 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1145 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1146 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1147 and_rr(code, src_op.base, dst_op.base, z80_size(inst));
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1148 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1149 and_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1150 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1151 and_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1152 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1153 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1154 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1155 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1156 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1157 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1158 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1159 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1160 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1161 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1162 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1163 case Z80_OR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1164 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1165 num_cycles += 8;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1166 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1167 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1168 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1169 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1170 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1171 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1172 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1173 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1174 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1175 or_rr(code, src_op.base, dst_op.base, z80_size(inst));
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1176 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1177 or_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1178 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1179 or_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1180 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1181 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1182 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1183 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1184 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1185 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1186 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1187 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1188 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1189 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1190 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1191 case Z80_XOR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1192 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1193 num_cycles += 8;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1194 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1195 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1196 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1197 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1198 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1199 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1200 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1201 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1202 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1203 xor_rr(code, src_op.base, dst_op.base, z80_size(inst));
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1204 } else if (src_op.mode == MODE_IMMED) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1205 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1206 } else {
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1207 xor_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1208 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1209 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1210 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1211 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1212 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1213 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1214 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1215 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1216 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1217 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1218 break;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1219 case Z80_CP:
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1220 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1221 num_cycles += 8;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1222 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1223 num_cycles += 3;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1224 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1225 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1226 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1227 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1228 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1229 if (src_op.mode == MODE_REG_DIRECT) {
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1230 sub_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1231 mov_rrdisp(code, src_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1232 } else if (src_op.mode == MODE_IMMED) {
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1233 sub_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1234 mov_irdisp(code, src_op.disp, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1235 } else {
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1236 sub_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1237 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1238 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1239 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1240 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1241 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1242 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1243 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1244 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1245 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1246 if (src_op.mode == MODE_REG_DIRECT) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1247 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1248 } else if (src_op.mode == MODE_IMMED) {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1249 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1250 } else {
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1251 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst));
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1252 }
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1253 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1254 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1255 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1256 z80_save_ea(code, inst, opts);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	1257 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1258 case Z80_INC:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1259 case Z80_DEC:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1260 if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1261 num_cycles += 2;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1262 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1263 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1264 translate_z80_reg(inst, &dst_op, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1265 if (dst_op.mode == MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1266 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1267 }
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1268 if (z80_size(inst) == SZ_B) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1269 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1270 if (dst_op.base >= AH && dst_op.base <= BH) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1271 mov_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1272 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1273 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1274 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1275 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1276 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1277 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1278 }
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1279 if (inst->op == Z80_INC) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1280 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1281 add_ir(code, 1, dst_op.base, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1282 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1283 add_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1284 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1285 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1286 if (dst_op.mode == MODE_REG_DIRECT) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1287 sub_ir(code, 1, dst_op.base, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1288 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1289 sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1290 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1291 }
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1292 if (z80_size(inst) == SZ_B) {
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1293 mov_irdisp(code, inst->op == Z80_DEC, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1294 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1295 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1296 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1297 int bit = 4;
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1298 if (dst_op.mode == MODE_REG_DIRECT) {
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1299 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1300 if (dst_op.base >= AH && dst_op.base <= BH) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1301 bit = 12;
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1302 xor_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1303 } else {
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1304 xor_rr(code, dst_op.base, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1305 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1306 } else {
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1307 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1308 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B);
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1309 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1310 }
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1311 bt_ir(code, bit, opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1312 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1313 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1314 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1315 z80_save_ea(code, inst, opts);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1316 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1317 break;
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1318 case Z80_DAA: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1319 cycles(&opts->gen, num_cycles);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1320 xor_rr(code, opts->gen.scratch2, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1321 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1322 and_ir(code, 0xF, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1323 cmp_ir(code, 0xA, opts->gen.scratch1, SZ_B);
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1324 mov_ir(code, 0xA0, opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1325 code_ptr corf_low_range = code->cur + 1;
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1326 jcc(code, CC_NC, code->cur+2);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1327 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1328 code_ptr corf_low = code->cur + 1;
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1329 jcc(code, CC_NZ, code->cur+2);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1330 code_ptr no_corf_low = code->cur + 1;
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1331 jmp(code, code->cur + 2);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1332
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1333 *corf_low_range = code->cur - (corf_low_range + 1);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1334 mov_ir(code, 0x90, opts->gen.scratch1, SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1335 *corf_low = code->cur - (corf_low + 1);
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1336 mov_ir(code, 0x06, opts->gen.scratch2, SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1337
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1338 *no_corf_low = code->cur - (no_corf_low + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1339 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1340 code_ptr corf_high = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1341 jcc(code, CC_NZ, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1342 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1343 code_ptr no_corf_high = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1344 jcc(code, CC_C, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1345 *corf_high = code->cur - (corf_high + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1346 or_ir(code, 0x60, opts->gen.scratch2, SZ_B);
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1347 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1348 *no_corf_high = code->cur - (no_corf_high + 1);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1349
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1350 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1351 xor_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1352
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1353 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1354 code_ptr not_sub = code->cur+1;
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1355 jcc(code, CC_Z, code->cur+2);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1356 neg_r(code, opts->gen.scratch2, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1357 *not_sub = code->cur - (not_sub + 1);
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1358
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1359 add_rr(code, opts->gen.scratch2, opts->regs[Z80_A], SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1360 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1361 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1362 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1363 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1364 bt_ir(code, 4, opts->gen.scratch1, SZ_B);
a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1365 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1050 d06c947a9a77 Implement undoumented flag bits for DAA, CPL, SCF and CCF Michael Pavone <pavone@retrodev.com> parents: 1049 diff changeset	1366 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1367 break;
1046 a27fdf43f1a7 Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC! Michael Pavone <pavone@retrodev.com> parents: 1045 diff changeset	1368 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1369 case Z80_CPL:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1370 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1371 not_r(code, opts->regs[Z80_A], SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1372 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1373 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1050 d06c947a9a77 Implement undoumented flag bits for DAA, CPL, SCF and CCF Michael Pavone <pavone@retrodev.com> parents: 1049 diff changeset	1374 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	1375 break;
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	1376 case Z80_NEG:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1377 cycles(&opts->gen, num_cycles);
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1378 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1379 neg_r(code, opts->regs[Z80_A], SZ_B);
1056 47c748455365 Fixed bug introduced in NEG with addition of undocumented flags Michael Pavone <pavone@retrodev.com> parents: 1055 diff changeset	1380 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1381 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1382 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1383 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1384 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1385 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1045 e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1386 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1387 bt_ir(code, 4, opts->gen.scratch2, SZ_B);
e0489abfdab0 Implement half-carry for INC, DEC and NEG Michael Pavone <pavone@retrodev.com> parents: 1044 diff changeset	1388 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	1389 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1390 case Z80_CCF:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1391 cycles(&opts->gen, num_cycles);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1392 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1393 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1394 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1395 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1050 d06c947a9a77 Implement undoumented flag bits for DAA, CPL, SCF and CCF Michael Pavone <pavone@retrodev.com> parents: 1049 diff changeset	1396 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	1397 break;
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	1398 case Z80_SCF:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1399 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1400 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1401 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1402 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1050 d06c947a9a77 Implement undoumented flag bits for DAA, CPL, SCF and CCF Michael Pavone <pavone@retrodev.com> parents: 1049 diff changeset	1403 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	1404 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1405 case Z80_NOP:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1406 cycles(&opts->gen, num_cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1407 break;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1408 case Z80_HALT: {
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1409 code_ptr loop_top = code->cur;
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1410 //this isn't terribly efficient, but it's good enough for now
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1411 cycles(&opts->gen, num_cycles);
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1412 check_cycles_int(&opts->gen, address);
30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1413 jmp(code, loop_top);
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	1414 break;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1415 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1416 case Z80_DI:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1417 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1418 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1419 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	1420 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	1421 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.scratch1, SZ_D);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1422 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	1423 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	1424 sub_rr(code, opts->gen.scratch1, opts->gen.cycles, SZ_D);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	1425 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1426 case Z80_EI:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1427 cycles(&opts->gen, num_cycles);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	1428 neg_r(code, opts->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	1429 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1430 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	1431 neg_r(code, opts->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	1432 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1433 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1434 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
335 14a937097c2b Some Z80 interrupt fixes Mike Pavone <pavone@retrodev.com> parents: 315 diff changeset	1435 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	1436 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1437 call(code, opts->do_sync);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	1438 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1439 case Z80_IM:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1440 cycles(&opts->gen, num_cycles);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1441 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	1442 break;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1443 case Z80_RLC:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1444 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1445 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1446 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1447 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1448 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1449 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1450 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1451 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1452 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1453 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1454 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1455 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1456 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1457 rol_ir(code, 1, dst_op.base, SZ_B);
1053 b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1458 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1459 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1460 rol_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1053 b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1461 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1462 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1463 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1464 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1465 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1466 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1467 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1468 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1469 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1470 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1471 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1472 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1473 //rlca does not set these flags
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1474 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1475 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1476 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1477 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1478 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1479 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1480 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1481 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1482 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1483 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1484 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1485 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1486 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1487 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1488 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1489 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1490 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1491 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1492 case Z80_RL:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1493 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1494 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1495 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1496 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1497 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1498 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1499 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1500 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1501 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1502 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1503 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1504 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1505 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1506 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1507 rcl_ir(code, 1, dst_op.base, SZ_B);
1053 b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1508 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1509 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1510 rcl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1053 b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1511 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1512 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1513 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1514 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1515 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1516 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1517 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1518 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1519 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1520 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1521 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1522 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1523 //rla does not set these flags
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1524 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1525 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1526 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1527 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1528 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1529 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1530 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1531 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1532 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1533 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1534 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1535 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1536 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1537 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1538 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1539 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1540 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1541 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1542 case Z80_RRC:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1543 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1544 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1545 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1546 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1547 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1548 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1549 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1550 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1551 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1552 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1553 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1554 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1555 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1556 ror_ir(code, 1, dst_op.base, SZ_B);
1053 b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1557 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1558 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1559 ror_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1053 b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1560 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1561 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1562 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1563 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1564 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1565 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1566 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1567 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1568 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1569 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1570 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1571 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1572 //rrca does not set these flags
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1573 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1574 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1575 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1576 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1577 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1578 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1579 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1580 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1581 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1582 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1583 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1584 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1585 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1586 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1587 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1588 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1589 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1590 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1591 case Z80_RR:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1592 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1593 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1594 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1595 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1596 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1597 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1598 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1599 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1600 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1601 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1602 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1603 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1604 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1605 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1606 rcr_ir(code, 1, dst_op.base, SZ_B);
1053 b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1607 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1608 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1609 rcr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1053 b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1610 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
b86c3ce007d9 Implemented undocumented flag bits for rotate instructions Michael Pavone <pavone@retrodev.com> parents: 1052 diff changeset	1611 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1612 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1613 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1614 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1615 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1616 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1617 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1618 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1619 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1620 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1621 if (inst->immed) {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1622 //rra does not set these flags
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1623 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1624 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1625 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1626 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1627 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1628 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1629 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1630 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
651 103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown. Michael Pavone <pavone@retrodev.com> parents: 644 diff changeset	1631 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1632 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1633 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1634 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1635 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1636 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1637 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1638 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1639 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1640 break;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1641 case Z80_SLA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1642 case Z80_SLL:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1643 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1644 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1645 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1646 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1647 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1648 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1649 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1650 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1651 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1652 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1653 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1654 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1655 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1656 shl_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1657 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1658 shl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1659 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1660 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1661 if (inst->op == Z80_SLL) {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1662 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1663 or_ir(code, 1, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1664 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1665 or_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1666 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1667 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1668 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1669 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1670 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1671 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1672 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1673 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1674 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1675 if (dst_op.mode == MODE_REG_DIRECT) {
1055 ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1676 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1677 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1678 } else {
1055 ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1679 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1680 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1681 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1682 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1683 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1684 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1685 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1686 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1687 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1688 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1689 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1690 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1691 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1692 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1693 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1694 break;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1695 case Z80_SRA:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1696 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1697 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1698 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1699 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1700 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1701 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1702 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1703 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1704 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1705 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1706 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1707 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1708 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1709 sar_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1710 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1711 sar_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1712 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1713 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1714 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1715 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1716 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1717 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1718 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1719 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1720 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1721 if (dst_op.mode == MODE_REG_DIRECT) {
1055 ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1722 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1723 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1724 } else {
1055 ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1725 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1726 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1727 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1728 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1729 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1730 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1731 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1732 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1733 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1734 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1735 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1736 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1737 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1738 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1739 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1740 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1741 case Z80_SRL:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1742 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1743 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1744 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1745 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1746 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1747 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1748 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1749 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1750 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1751 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1752 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1753 }
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1754 if (dst_op.mode == MODE_REG_DIRECT) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1755 shr_ir(code, 1, dst_op.base, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1756 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1757 shr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1758 }
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1759 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1760 mov_rr(code, dst_op.base, src_op.base, SZ_B);
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1761 } else if(src_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	1762 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1763 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1764 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1765 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1766 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1767 if (dst_op.mode == MODE_REG_DIRECT) {
1055 ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1768 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1769 cmp_ir(code, 0, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1770 } else {
1055 ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1771 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
ac4615d16226 Implement undocumented flag bits for shift instructions Michael Pavone <pavone@retrodev.com> parents: 1054 diff changeset	1772 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1773 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1774 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1775 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1776 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1777 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1778 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1779 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1780 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1781 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1782 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1783 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1784 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1785 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1786 break;
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1787 case Z80_RLD:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1788 cycles(&opts->gen, num_cycles);
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1789 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1790 call(code, opts->read_8);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1791 //Before: (HL) = 0x12, A = 0x34
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1792 //After: (HL) = 0x24, A = 0x31
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1793 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1794 shl_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1795 and_ir(code, 0xF, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1796 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1797 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1798 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1799 //opts->gen.scratch1 = 0x0124
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1800 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1801 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1802 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1803 //set flags
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1804 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1805 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1806 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1807 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1808 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1054 ca38a29d2d76 Implement undocumented flag bits for RLD and RRD Michael Pavone <pavone@retrodev.com> parents: 1053 diff changeset	1809 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1810
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1811 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1812 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1813 call(code, opts->write_8);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1814 break;
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1815 case Z80_RRD:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1816 cycles(&opts->gen, num_cycles);
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1817 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1818 call(code, opts->read_8);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1819 //Before: (HL) = 0x12, A = 0x34
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1820 //After: (HL) = 0x41, A = 0x32
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1821 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1822 ror_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1823 shl_ir(code, 4, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1824 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1825 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
967 1eb616b8cbe9 Fix bug in Z80 rrd implementation. This fixes the annoying high pitched wine in Afterburner II. Michael Pavone <pavone@retrodev.com> parents: 966 diff changeset	1826 and_ir(code, 0xF0, opts->gen.scratch2, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1827 //opts->gen.scratch1 = 0x2001
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1828 //opts->gen.scratch2 = 0x0040
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1829 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1830 //opts->gen.scratch1 = 0x2041
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1831 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1832 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1833 shr_ir(code, 4, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1834 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1835 //set flags
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1836 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1837 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1838 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1839 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1840 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1054 ca38a29d2d76 Implement undocumented flag bits for RLD and RRD Michael Pavone <pavone@retrodev.com> parents: 1053 diff changeset	1841 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1842
734 e21c274a008e Fix RLD and RRD for the case in which HL does not map to a native register Michael Pavone <pavone@retrodev.com> parents: 731 diff changeset	1843 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1844 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1845 call(code, opts->write_8);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1846 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1847 case Z80_BIT: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1848 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1849 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1850 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1851 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1852 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1853 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1854 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737 043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression Michael Pavone <pavone@retrodev.com> parents: 735 diff changeset	1855 src_op.mode = MODE_REG_DIRECT;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1856 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1857 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1858 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1859 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1860 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1861 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1862 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1863 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1864 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1865 cycles(&opts->gen, 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1866 }
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1867 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1868 bt_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1869 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1870 bt_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1871 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1872 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1873 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1874 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	1875 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1876 if (inst->immed == 7) {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1877 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1878 cmp_ir(code, 0, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1879 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1880 cmp_irdisp(code, 0, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1881 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1882 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1883 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1884 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1885 }
1049 ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1886
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1887 if ((inst->addr_mode & 0x1F) == Z80_REG) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1888 if (src_op.mode == MODE_REG_DIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1889 if (size == SZ_W) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1890 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1891 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1892 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1893 } else {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1894 mov_rrdisp(code, src_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1895 }
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1896 } else {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1897 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1898 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1899 }
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1900 } else if((inst->addr_mode & 0x1F) != Z80_REG_INDIRECT) {
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1901 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, opts->gen.scratch2);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1902 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1903 shr_ir(code, 8, opts->gen.scratch2, SZ_W);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1904 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits Michael Pavone <pavone@retrodev.com> parents: 1048 diff changeset	1905 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1906 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1907 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1908 case Z80_SET: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1909 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1910 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1911 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1912 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1913 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1914 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1915 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737 043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression Michael Pavone <pavone@retrodev.com> parents: 735 diff changeset	1916 src_op.mode = MODE_REG_DIRECT;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1917 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1918 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1919 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1920 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1921 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1922 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1923 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1924 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1925 translate_z80_reg(inst, &dst_op, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1926 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1927 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1928 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1929 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1930 }
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1931 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1932 bts_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1933 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1934 bts_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1935 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1936 if (inst->reg != Z80_USE_IMMED) {
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1937 if (size == SZ_W) {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1938 #ifdef X86_64
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1939 if (dst_op.base >= R8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1940 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1941 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1942 ror_ir(code, 8, src_op.base, SZ_W);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1943 } else {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1944 #endif
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1945 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1946 zreg_to_native(opts, inst->ea_reg, dst_op.base);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1947 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1948 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1949 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1950 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1951 #ifdef X86_64
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1952 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	1953 #endif
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1954 } else {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1955 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1956 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1957 mov_rr(code, src_op.base, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1958 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1959 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1960 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1961 } else if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1962 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1963 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1964 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1965 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	1966 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1967 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1968 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1969 if ((inst->addr_mode & 0x1F) != Z80_REG) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1970 z80_save_result(opts, inst);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1971 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1972 z80_save_reg(inst, opts);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1973 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1974 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1975 break;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1976 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1977 case Z80_RES: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1978 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1979 num_cycles += 8;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	1980 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1981 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1982 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1983 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1984 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
737 043393b79e28 Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression Michael Pavone <pavone@retrodev.com> parents: 735 diff changeset	1985 src_op.mode = MODE_REG_DIRECT;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1986 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1987 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1988 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1989 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1990 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1991 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1992 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1993 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1994 translate_z80_reg(inst, &dst_op, opts);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1995 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1996 if (inst->addr_mode != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1997 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1998 cycles(&opts->gen, 1);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1999 }
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2000 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2001 btr_ir(code, bit, src_op.base, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2002 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2003 btr_irdisp(code, bit, src_op.base, src_op.disp, size);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2004 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	2005 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	2006 if (size == SZ_W) {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2007 #ifdef X86_64
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	2008 if (dst_op.base >= R8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2009 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2010 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2011 ror_ir(code, 8, src_op.base, SZ_W);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	2012 } else {
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2013 #endif
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2014 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2015 zreg_to_native(opts, inst->ea_reg, dst_op.base);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2016 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2017 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2018 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2019 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2020 #ifdef X86_64
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	2021 }
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	2022 #endif
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	2023 } else {
731 0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2024 if (dst_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2025 if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2026 mov_rr(code, src_op.base, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2027 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2028 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2029 }
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2030 } else if (src_op.mode == MODE_REG_DIRECT) {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2031 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2032 } else {
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2033 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2034 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit Michael Pavone <pavone@retrodev.com> parents: 730 diff changeset	2035 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	2036 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	2037 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	2038 if (inst->addr_mode != Z80_REG) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2039 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	2040 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2041 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	2042 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	2043 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	2044 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	2045 }
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2046 case Z80_JP: {
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	2047 if (inst->addr_mode != Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2048 num_cycles += 6;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2049 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2050 cycles(&opts->gen, num_cycles);
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2051 if (inst->addr_mode != Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2052 code_ptr call_dst = z80_get_native_address(context, inst->immed);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2053 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2054 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2055 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2056 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2057 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2058 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2059 } else {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	2060 if (inst->addr_mode == Z80_REG_INDIRECT) {
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	2061 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2062 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2063 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2064 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2065 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2066 jmp_r(code, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2067 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2068 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2069 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2070 case Z80_JPCC: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2071 cycles(&opts->gen, num_cycles + 3);//T States: 4,3
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2072 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2073 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2074 {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2075 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2076 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2077 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2078 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2079 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2080 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2081 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2082 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2083 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2084 break;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2085 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2086 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2087 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2088 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2089 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2090 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	2091 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2092 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2093 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2094 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2095 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2096 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2097 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2098 cycles(&opts->gen, 5);//T States: 5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2099 uint16_t dest_addr = inst->immed;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2100 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2101 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2102 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2103 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2104 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2105 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2106 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2107 *no_jump_off = code->cur - (no_jump_off+1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2108 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2109 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2110 case Z80_JR: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2111 cycles(&opts->gen, num_cycles + 8);//T States: 4,3,5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2112 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2113 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2114 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2115 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2116 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2117 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2118 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2119 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2120 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	2121 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2122 case Z80_JRCC: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2123 cycles(&opts->gen, num_cycles + 3);//T States: 4,3
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2124 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2125 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2126 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2127 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2128 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2129 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2130 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2131 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2132 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2133 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2134 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2135 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2136 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2137 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2138 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2139 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2140 cycles(&opts->gen, 5);//T States: 5
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2141 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2142 code_ptr call_dst = z80_get_native_address(context, dest_addr);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2143 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2144 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2145 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2146 call_dst = code->cur + 256;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2147 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2148 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2149 *no_jump_off = code->cur - (no_jump_off+1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2150 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2151 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2152 case Z80_DJNZ: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2153 cycles(&opts->gen, num_cycles + 4);//T States: 5,3
730 38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	2154 if (opts->regs[Z80_B] >= 0) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	2155 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	2156 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	2157 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core Michael Pavone <pavone@retrodev.com> parents: 729 diff changeset	2158 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2159 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2160 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2161 cycles(&opts->gen, 5);//T States: 5
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	2162 uint16_t dest_addr = address + inst->immed + 2;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2163 code_ptr call_dst = z80_get_native_address(context, dest_addr);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	2164 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2165 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	2166 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2167 call_dst = code->cur + 256;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	2168 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2169 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2170 *no_jump_off = code->cur - (no_jump_off+1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	2171 break;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	2172 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2173 case Z80_CALL: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2174 cycles(&opts->gen, num_cycles + 7);//T States: 4,3,4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2175 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2176 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2177 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2178 call(code, opts->write_16_highfirst);//T States: 3, 3
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2179 code_ptr call_dst = z80_get_native_address(context, inst->immed);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2180 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2181 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2182 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2183 call_dst = code->cur + 256;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2184 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2185 jmp(code, call_dst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2186 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2187 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2188 case Z80_CALLCC: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2189 cycles(&opts->gen, num_cycles + 6);//T States: 4,3,3 (false case)
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2190 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2191 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2192 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2193 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2194 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2195 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2196 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2197 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2198 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2199 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2200 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2201 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2202 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2203 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2204 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2205 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2206 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2207 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2208 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	2209 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2210 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2211 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2212 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2213 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2214 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2215 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2216 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2217 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2218 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2219 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2220 call(code, opts->write_16_highfirst);//T States: 3, 3
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2221 code_ptr call_dst = z80_get_native_address(context, inst->immed);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2222 if (!call_dst) {
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2223 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2224 //fake address to force large displacement
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2225 call_dst = code->cur + 256;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2226 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	2227 jmp(code, call_dst);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2228 *no_call_off = code->cur - (no_call_off+1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	2229 break;
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	2230 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2231 case Z80_RET:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2232 cycles(&opts->gen, num_cycles);//T States: 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2233 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2234 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2235 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2236 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2237 jmp_r(code, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2238 break;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2239 case Z80_RETCC: {
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2240 cycles(&opts->gen, num_cycles + 1);//T States: 5
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2241 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2242 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2243 {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2244 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2245 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2246 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2247 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2248 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2249 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2250 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2251 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2252 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2253 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2254 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2255 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2256 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2257 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2258 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2259 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	2260 cond = CC_NZ;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2261 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2262 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2263 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2264 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2265 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2266 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2267 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2268 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2269 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2270 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2271 jmp_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2272 *no_call_off = code->cur - (no_call_off+1);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2273 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	2274 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2275 case Z80_RETI:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2276 //For some systems, this may need a callback for signalling interrupt routine completion
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2277 cycles(&opts->gen, num_cycles);//T States: 4, 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2278 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2279 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2280 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2281 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2282 jmp_r(code, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2283 break;
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2284 case Z80_RETN:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2285 cycles(&opts->gen, num_cycles);//T States: 4, 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2286 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2287 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2288 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2289 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2290 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2291 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2292 jmp_r(code, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	2293 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2294 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2295 //RST is basically CALL to an address in page 0
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2296 cycles(&opts->gen, num_cycles + 1);//T States: 5
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2297 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2298 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2299 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2300 call(code, opts->write_16_highfirst);//T States: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2301 code_ptr call_dst = z80_get_native_address(context, inst->immed);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2302 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2303 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2304 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2305 call_dst = code->cur + 256;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2306 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2307 jmp(code, call_dst);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2308 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	2309 }
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2310 case Z80_IN:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2311 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2312 num_cycles += 3;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2313 }
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2314 cycles(&opts->gen, num_cycles);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2315 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2316 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2317 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2318 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2319 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2320 call(code, opts->read_io);
1042 a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2321 if (inst->addr_mode != Z80_IMMED_INDIRECT) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2322 or_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2323 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2324 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2325 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2326 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2327 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2328 }
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2329 if (inst->reg != Z80_UNUSED) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2330 translate_z80_reg(inst, &dst_op, opts);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2331 if (dst_op.mode == MODE_REG_DIRECT) {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2332 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2333 } else {
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2334 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
a6c6b621d0dc Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case Michael Pavone <pavone@retrodev.com> parents: 1040 diff changeset	2335 }
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2336 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2337 z80_save_reg(inst, opts);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2338 break;
1060 56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2339 case Z80_INI:
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2340 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2341 //read from IO (C)
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2342 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2343 call(code, opts->read_io);//T states 3
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2344
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2345 //undocumented N flag behavior
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2346 //flag set on bit 7 of value written
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2347 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2348 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2349 //save value to be written for flag calculation, as the write func does not
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2350 //guarantee that it's preserved across the call
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2351 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2352
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2353 //write to (HL)
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2354 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2355 call(code, opts->write_8);//T states 4
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2356 cycles(&opts->gen, 1);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2357
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2358 //increment HL
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2359 if (opts->regs[Z80_HL] >= 0) {
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2360 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2361 } else {
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2362 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2363 }
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2364 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2365 if (opts->regs[Z80_C] >= 0) {
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2366 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2367 } else {
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2368 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2369 }
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2370 add_ir(code, 1, opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2371 //undocumented C and H flag behavior
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2372 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2373 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2374 //decrement B
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2375 if (opts->regs[Z80_B] >= 0) {
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2376 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2377 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2378 } else {
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2379 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2380 }
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2381 //undocumented Z and S flag behavior, set based on decrement of B
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2382 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2383 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2384 //crazy undocumented P/V flag behavior
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2385 and_ir(code, 7, opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2386 if (opts->regs[Z80_B] >= 0) {
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2387 //deal with silly x86-64 restrictions on *H registers
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2388 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2389 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2390 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2391 } else {
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2392 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2393 }
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2394 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
56713dac6a69 Implement INI Michael Pavone <pavone@retrodev.com> parents: 1057 diff changeset	2395 break;
1061 9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2396 case Z80_INIR: {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2397 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2398 //read from IO (C)
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2399 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2400 call(code, opts->read_io);//T states 3
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2401
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2402 //undocumented N flag behavior
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2403 //flag set on bit 7 of value written
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2404 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2405 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2406 //save value to be written for flag calculation, as the write func does not
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2407 //guarantee that it's preserved across the call
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2408 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2409
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2410 //write to (HL)
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2411 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2412 call(code, opts->write_8);//T states 4
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2413 cycles(&opts->gen, 1);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2414
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2415 //increment HL
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2416 if (opts->regs[Z80_HL] >= 0) {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2417 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2418 } else {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2419 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2420 }
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2421 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2422 if (opts->regs[Z80_C] >= 0) {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2423 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2424 } else {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2425 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2426 }
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2427 add_ir(code, 1, opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2428 //undocumented C and H flag behavior
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2429 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2430 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2431 //decrement B
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2432 if (opts->regs[Z80_B] >= 0) {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2433 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2434 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2435 } else {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2436 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2437 }
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2438 //undocumented Z and S flag behavior, set based on decrement of B
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2439 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2440 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2441 //crazy undocumented P/V flag behavior
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2442 and_ir(code, 7, opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2443 if (opts->regs[Z80_B] >= 0) {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2444 //deal with silly x86-64 restrictions on *H registers
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2445 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2446 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2447 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2448 } else {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2449 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2450 }
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2451 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2452 if (opts->regs[Z80_B] >= 0) {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2453 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2454 } else {
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2455 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2456 }
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2457 code_ptr done = code->cur+1;
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2458 jcc(code, CC_Z, code->cur+2);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2459 cycles(&opts->gen, 5);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2460 jmp(code, start);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2461 *done = code->cur - (done + 1);
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2462 break;
9b5bb50098d2 Implemented INIR Michael Pavone <pavone@retrodev.com> parents: 1060 diff changeset	2463 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2464 case Z80_IND:
1062 779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2465 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2466 //read from IO (C)
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2467 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2468 call(code, opts->read_io);//T states 3
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2469
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2470 //undocumented N flag behavior
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2471 //flag set on bit 7 of value written
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2472 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2473 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2474 //save value to be written for flag calculation, as the write func does not
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2475 //guarantee that it's preserved across the call
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2476 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2477
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2478 //write to (HL)
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2479 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2480 call(code, opts->write_8);//T states 4
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2481 cycles(&opts->gen, 1);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2482
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2483 //decrement HL
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2484 if (opts->regs[Z80_HL] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2485 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2486 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2487 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2488 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2489 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2490 if (opts->regs[Z80_C] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2491 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2492 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2493 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2494 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2495 add_ir(code, 1, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2496 //undocumented C and H flag behavior
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2497 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2498 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2499 //decrement B
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2500 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2501 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2502 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2503 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2504 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2505 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2506 //undocumented Z and S flag behavior, set based on decrement of B
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2507 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2508 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2509 //crazy undocumented P/V flag behavior
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2510 and_ir(code, 7, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2511 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2512 //deal with silly x86-64 restrictions on *H registers
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2513 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2514 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2515 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2516 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2517 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2518 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2519 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2520 break;
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2521 case Z80_INDR: {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2522 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2523 //read from IO (C)
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2524 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2525 call(code, opts->read_io);//T states 3
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2526
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2527 //undocumented N flag behavior
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2528 //flag set on bit 7 of value written
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2529 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2530 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2531 //save value to be written for flag calculation, as the write func does not
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2532 //guarantee that it's preserved across the call
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2533 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2534
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2535 //write to (HL)
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2536 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2537 call(code, opts->write_8);//T states 4
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2538 cycles(&opts->gen, 1);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2539
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2540 //decrement HL
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2541 if (opts->regs[Z80_HL] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2542 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2543 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2544 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2545 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2546 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2547 if (opts->regs[Z80_C] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2548 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2549 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2550 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2551 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2552 add_ir(code, 1, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2553 //undocumented C and H flag behavior
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2554 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2555 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2556 //decrement B
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2557 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2558 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2559 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2560 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2561 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2562 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2563 //undocumented Z and S flag behavior, set based on decrement of B
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2564 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2565 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2566 //crazy undocumented P/V flag behavior
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2567 and_ir(code, 7, opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2568 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2569 //deal with silly x86-64 restrictions on *H registers
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2570 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2571 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2572 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2573 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2574 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2575 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2576 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2577 if (opts->regs[Z80_B] >= 0) {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2578 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2579 } else {
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2580 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2581 }
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2582 code_ptr done = code->cur+1;
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2583 jcc(code, CC_Z, code->cur+2);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2584 cycles(&opts->gen, 5);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2585 jmp(code, start);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2586 *done = code->cur - (done + 1);
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2587 break;
779acbfb74d0 Implemented IND and INDR Michael Pavone <pavone@retrodev.com> parents: 1061 diff changeset	2588 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2589 case Z80_OUT:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2590 if (inst->reg == Z80_A) {
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2591 num_cycles += 3;
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2592 }
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2593 cycles(&opts->gen, num_cycles);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2594 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2595 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2596 } else {
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2597 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2598 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2599 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2600 translate_z80_reg(inst, &src_op, opts);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2601 if (src_op.mode == MODE_REG_DIRECT) {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2602 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2603 } else if (src_op.mode == MODE_IMMED) {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2604 mov_ir(code, src_op.disp, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2605 } else {
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2606 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	2607 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2608 call(code, opts->write_io);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2609 z80_save_reg(inst, opts);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	2610 break;
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2611 case Z80_OUTI:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2612 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2613 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2614 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2615 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2616 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2617 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2618 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2619 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2620 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2621 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2622 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2623 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2624 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2625 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2626 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2627 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2628 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2629 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2630 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2631 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2632 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2633 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2634 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2635 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2636 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2637 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2638 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2639 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2640 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2641 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2642 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2643 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2644 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2645 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2646 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2647 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2648 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2649 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2650 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2651 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2652 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2653 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2654 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2655 case Z80_OTIR: {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2656 code_ptr start = code->cur;
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2657 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2658 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2659 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2660 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2661 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2662 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2663 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2664 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2665 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2666 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2667 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2668 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2669 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2670 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2671 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2672 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2673 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2674 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2675 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2676 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2677 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2678 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2679 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2680 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2681 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2682 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2683 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2684 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2685 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2686 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2687 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2688 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2689 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2690 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2691 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2692 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2693 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2694 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2695 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2696 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2697 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2698 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2699 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2700 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2701 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2702 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2703 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2704 code_ptr done = code->cur+1;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2705 jcc(code, CC_Z, code->cur+2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2706 cycles(&opts->gen, 5);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2707 jmp(code, start);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2708 *done = code->cur - (done + 1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2709 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2710 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2711 case Z80_OUTD:
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2712 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2713 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2714 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2715 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2716 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2717 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2718 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2719 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2720 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2721 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2722 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2723 //decrement HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2724 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2725 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2726 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2727 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2728 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2729 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2730 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2731 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2732 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2733 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2734 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2735 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2736 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2737 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2738 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2739 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2740 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2741 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2742 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2743 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2744 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2745 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2746 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2747 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2748 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2749 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2750 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2751 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2752 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2753 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2754 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2755 case Z80_OTDR: {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2756 code_ptr start = code->cur;
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2757 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
1040 fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2758 //read from (HL)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2759 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2760 call(code, opts->read_8);//T states 3
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2761 //undocumented N flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2762 //flag set on bit 7 of value written
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2763 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2764 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2765 //write to IO (C)
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2766 zreg_to_native(opts, Z80_C, opts->gen.scratch2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2767 call(code, opts->write_io);//T states 4
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2768 //increment HL
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2769 if (opts->regs[Z80_HL] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2770 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2771 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2772 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2773 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2774 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2775 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2776 //undocumented C and H flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2777 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2778 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2779 //decrement B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2780 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2781 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2782 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2783 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2784 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2785 //undocumented Z and S flag behavior, set based on decrement of B
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2786 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2787 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2788 //crazy undocumented P/V flag behavior
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2789 and_ir(code, 7, opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2790 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2791 //deal with silly x86-64 restrictions on *H registers
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2792 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2793 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2794 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2795 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2796 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2797 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2798 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2799 if (opts->regs[Z80_B] >= 0) {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2800 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2801 } else {
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2802 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2803 }
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2804 code_ptr done = code->cur+1;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2805 jcc(code, CC_Z, code->cur+2);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2806 cycles(&opts->gen, 5);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2807 jmp(code, start);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2808 *done = code->cur - (done + 1);
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2809 break;
fbfb821e92a8 Implement Z80 block OUT instructions. Fixes Power Monger Michael Pavone <pavone@retrodev.com> parents: 967 diff changeset	2810 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2811 default: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2812 char disbuf[80];
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	2813 z80_disasm(inst, disbuf, address);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2814 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2815 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2816 fclose(f);
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	2817 fatal_error("unimplemented Z80 instruction: %s at %X\nZ80 RAM has been saved to zram.bin for debugging", disbuf, address);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2818 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2819 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2820 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2821
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2822 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context)
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2823 {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2824 if (!context->interp_code[opcode]) {
755 7306b3967c51 Cleanup some warnings under clang through a combination of code fixes and supressing specific warnings Michael Pavone <pavone@retrodev.com> parents: 737 diff changeset	2825 if (opcode == 0xCB \|\| (opcode >= 0xDD && (opcode & 0xF) == 0xD)) {
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	2826 fatal_error("Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2827 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2828 uint8_t codebuf[8];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2829 memset(codebuf, 0, sizeof(codebuf));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2830 codebuf[0] = opcode;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2831 z80inst inst;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2832 uint8_t * after = z80_decode(codebuf, &inst);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2833 if (after - codebuf > 1) {
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	2834 fatal_error("Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2835 }
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2836
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2837 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2838 code_info *code = &opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2839 check_alloc_code(code, ZMAX_NATIVE_SIZE);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2840 context->interp_code[opcode] = code->cur;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2841 translate_z80inst(&inst, context, 0, 1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2842 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2843 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2844 call(code, opts->native_addr);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2845 jmp_r(code, opts->gen.scratch1);
715 1c2020d3e275 Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly Michael Pavone <pavone@retrodev.com> parents: 712 diff changeset	2846 z80_handle_deferred(context);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2847 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2848 return context->interp_code[opcode];
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2849 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2850
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2851 code_info z80_make_interp_stub(z80_context * context, uint16_t address)
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2852 {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2853 z80_options *opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2854 code_info * code = &opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2855 check_alloc_code(code, 32);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2856 code_info stub = {code->cur, NULL};
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2857 //TODO: make this play well with the breakpoint code
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2858 mov_ir(code, address, opts->gen.scratch1, SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2859 call(code, opts->read_8);
1044 1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2860 //opcode fetch M-cycles have one extra T-state
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2861 cycles(&opts->gen, 1);
1625555e346e Properly handle redundant prefixes Michael Pavone <pavone@retrodev.com> parents: 1043 diff changeset	2862 //TODO: increment R
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2863 check_cycles_int(&opts->gen, address);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2864 call(code, opts->gen.save_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2865 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2866 push_r(code, opts->gen.context_reg);
712 382a2b5b70c0 Fix crash bug in Z80 interpreter Michael Pavone <pavone@retrodev.com> parents: 702 diff changeset	2867 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.context_reg);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	2868 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2869 pop_r(code, opts->gen.context_reg);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2870 call(code, opts->gen.load_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2871 jmp_r(code, opts->gen.scratch1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2872 stub.last = code->cur;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	2873 return stub;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2874 }
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2875
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2876
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2877 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2878 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2879 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2880 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2881 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2882 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2883 } else {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2884 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2885 map = context->banked_code_map;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2886 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2887 if (!map->base \|\| !map->offsets \|\| map->offsets[address] == INVALID_OFFSET \|\| map->offsets[address] == EXTENSION_WORD) {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	2888 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2889 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2890 }
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	2891 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2892 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2893 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2894
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2895 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2896 {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2897 //TODO: Fix for addresses >= 0x4000
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2898 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2899 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2900 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2901 return opts->gen.ram_inst_sizes[0][address & 0x1FFF];
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2902 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2903
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2904 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2905 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2906 uint32_t orig_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2907 native_map_slot *map;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2908 z80_options * opts = context->options;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2909 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2910 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2911 map = context->static_code_map;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2912 opts->gen.ram_inst_sizes[0][address] = native_size;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2913 context->ram_code_flags[(address & 0x1C00) >> 10] \|= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2914 context->ram_code_flags[((address + size) & 0x1C00) >> 10] \|= 1 << (((address + size) & 0x380) >> 7);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2915 } else {
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2916 //HERE
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2917 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2918 map = context->banked_code_map;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2919 if (!map->offsets) {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2920 map->offsets = malloc(sizeof(int32_t) * 0xC000);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2921 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2922 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2923 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2924 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2925 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2926 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2927 map->offsets[address] = native_address - map->base;
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	2928 for(--size, orig_address++; size; --size, orig_address++) {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2929 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2930 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2931 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2932 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2933 } else {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2934 address -= 0x4000;
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2935 map = context->banked_code_map;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2936 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2937 if (!map->offsets) {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2938 map->offsets = malloc(sizeof(int32_t) * 0xC000);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2939 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2940 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2941 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2942 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2943 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2944
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2945 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2946
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2947 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2948 {
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	2949 //TODO: Fixme for address >= 0x4000
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2950 if (!static_code_map->base \|\| address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2951 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2952 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2953 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2954 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2955 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2956 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2957 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2958 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2959 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2960 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2961 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2962 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2963
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2964 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2965 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2966 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2967 if (inst_start != INVALID_INSTRUCTION_START) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2968 code_ptr dst = z80_get_native_address(context, inst_start);
899 07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	2969 code_info code = {dst, dst+32, 0};
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2970 z80_options * opts = context->options;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	2971 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code.cur, inst_start, address);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2972 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2973 call(&code, opts->retrans_stub);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2974 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2975 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2976 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	2977
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2978 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2979 {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2980 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2981 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2982 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2983 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2984 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2985 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2986 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2987 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2988 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2989 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	2990
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2991 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2992 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2993 z80_options * opts = context->options;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2994 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2995 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2996 translate_z80_stream(context, opts->gen.deferred->address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2997 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2998 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	2999
559 6b248602ab84 blastem builds and almost works on OS X now Mike Pavone <pavone@retrodev.com> parents: 506 diff changeset	3000 extern void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) asm("z80_retranslate_inst");
390 561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word Mike Pavone <pavone@retrodev.com> parents: 389 diff changeset	3001 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start)
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3002 {
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3003 char disbuf[80];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3004 z80_options * opts = context->options;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3005 uint8_t orig_size = z80_get_native_inst_size(opts, address);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3006 code_info *code = &opts->gen.code;
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3007 uint8_t after, inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3008 z80inst instbuf;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	3009 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3010 after = z80_decode(inst, &instbuf);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	3011 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	3012 z80_disasm(&instbuf, disbuf, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3013 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3014 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3015 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3016 printf("%X\t%s\n", address, disbuf);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	3017 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	3018 #endif
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3019 if (orig_size != ZMAX_NATIVE_SIZE) {
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	3020 check_alloc_code(code, ZMAX_NATIVE_SIZE);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3021 code_ptr start = code->cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3022 deferred_addr * orig_deferred = opts->gen.deferred;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3023 translate_z80inst(&instbuf, context, address, 0);
644 2d7e84ae818c Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one Michael Pavone <pavone@retrodev.com> parents: 628 diff changeset	3024 /*
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3025 if ((native_end - dst) <= orig_size) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3026 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3027 if (native_next && ((native_next == orig_start + orig_size) \|\| (orig_size - (native_end - dst)) > 5)) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3028 remove_deferred_until(&opts->gen.deferred, orig_deferred);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	3029 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3030 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3031 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3032 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3033 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3034 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3035 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3036 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3037 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3038 return orig_start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3039 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3040 }*/
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3041 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3042 code_info tmp_code = {orig_start, orig_start + 16};
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3043 jmp(&tmp_code, start);
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	3044 tmp_code = *code;
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	3045 code->cur = start + ZMAX_NATIVE_SIZE;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	3046 if (!z80_is_terminal(&instbuf)) {
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	3047 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst));
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	3048 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3049 z80_handle_deferred(context);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3050 return start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3051 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3052 code_info tmp_code = *code;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3053 code->cur = orig_start;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3054 code->last = orig_start + ZMAX_NATIVE_SIZE;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3055 translate_z80inst(&instbuf, context, address, 0);
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	3056 code_info tmp2 = *code;
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	3057 *code = tmp_code;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	3058 if (!z80_is_terminal(&instbuf)) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3059
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	3060 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst));
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3061 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	3062 z80_handle_deferred(context);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3063 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	3064 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3065 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3066
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3067 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3068 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3069 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3070 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3071 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3072 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3073 z80_options * opts = context->options;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	3074 uint32_t start_address = address;
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	3075
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3076 do
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3077 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3078 z80inst inst;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	3079 dprintf("translating Z80 code at address %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3080 do {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3081 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3082 if (existing) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3083 jmp(&opts->gen.code, existing);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3084 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3085 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3086 uint8_t * encoded, *next;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3087 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3088 if (!encoded) {
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3089 code_info stub = z80_make_interp_stub(context, address);
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3090 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3091 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3092 }
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	3093 //make sure prologue is in a contiguous chunk of code
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	3094 check_code_prologue(&opts->gen.code);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3095 next = z80_decode(encoded, &inst);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	3096 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	3097 z80_disasm(&inst, disbuf, address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3098 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3099 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3100 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3101 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3102 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	3103 #endif
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3104 code_ptr start = opts->gen.code.cur;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3105 translate_z80inst(&inst, context, address, 0);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3106 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3107 address += next-encoded;
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	3108 address &= 0xFFFF;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	3109 } while (!z80_is_terminal(&inst));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3110 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3111 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3112 address = opts->gen.deferred->address;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	3113 dprintf("defferred address: %X\n", address);
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	3114 }
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3115 } while (opts->gen.deferred);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	3116 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	3117
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3118 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	3119 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3120 memset(options, 0, sizeof(*options));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3121
653 a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3122 options->gen.memmap = chunks;
a18e3923481e Remove some of the hard coded assumptions about the memory map from the CPU cores Michael Pavone <pavone@retrodev.com> parents: 652 diff changeset	3123 options->gen.memmap_chunks = num_chunks;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3124 options->gen.address_size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3125 options->gen.address_mask = 0xFFFF;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3126 options->gen.max_address = 0x10000;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3127 options->gen.bus_cycles = 3;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	3128 options->gen.clock_divider = clock_divider;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3129 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3130 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags);
620 9d6fed6501ba Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken. Michael Pavone <pavone@retrodev.com> parents: 601 diff changeset	3131 options->gen.ram_flags_shift = 7;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3132
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3133 options->flags = 0;
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3134 #ifdef X86_64
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3135 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3136 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3137 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3138 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3139 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3140 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3141 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3142 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3143 options->regs[Z80_IYH] = -1;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	3144 options->regs[Z80_IYL] = R8;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3145 options->regs[Z80_I] = -1;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3146 options->regs[Z80_R] = RDI;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3147 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3148 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3149 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3150 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3151 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3152 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3153 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3154 options->regs[Z80_IY] = R8;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	3155
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3156 options->gen.scratch1 = R13;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3157 options->gen.scratch2 = R14;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3158 #else
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3159 memset(options->regs, -1, sizeof(options->regs));
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3160 options->regs[Z80_A] = RAX;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3161 options->regs[Z80_R] = AH;
1048 05ecef6c73b6 More efficient register usage in 32-bit mode Michael Pavone <pavone@retrodev.com> parents: 1047 diff changeset	3162 options->regs[Z80_H] = BH;
05ecef6c73b6 More efficient register usage in 32-bit mode Michael Pavone <pavone@retrodev.com> parents: 1047 diff changeset	3163 options->regs[Z80_L] = RBX;
05ecef6c73b6 More efficient register usage in 32-bit mode Michael Pavone <pavone@retrodev.com> parents: 1047 diff changeset	3164 options->regs[Z80_HL] = RBX;
05ecef6c73b6 More efficient register usage in 32-bit mode Michael Pavone <pavone@retrodev.com> parents: 1047 diff changeset	3165
05ecef6c73b6 More efficient register usage in 32-bit mode Michael Pavone <pavone@retrodev.com> parents: 1047 diff changeset	3166 options->regs[Z80_SP] = RDI;
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	3167
666 b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3168 options->gen.scratch1 = RCX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3169 options->gen.scratch2 = RDX;
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed Michael Pavone <pavone@retrodev.com> parents: 665 diff changeset	3170 #endif
667 30ccf56842d6 All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working Michael Pavone <pavone@retrodev.com> parents: 666 diff changeset	3171
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3172 options->gen.context_reg = RSI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3173 options->gen.cycles = RBP;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3174 options->gen.limit = -1;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3175
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3176 options->gen.native_code_map = malloc(sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3177 memset(options->gen.native_code_map, 0, sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3178 options->gen.deferred = NULL;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3179 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3180 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3181 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3182
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3183 code_info *code = &options->gen.code;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3184 init_code_info(code);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3185
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3186 options->save_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3187 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3188 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3189
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3190 options->gen.save_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3191 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3192 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3193 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3194 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3195 if (i < Z80_I) {
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3196 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3197 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3198 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3199 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3200 size = SZ_B;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3201 }
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3202 if (reg == Z80_R) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3203 and_ir(code, 0x7F, options->regs[Z80_R], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3204 or_rrdisp(code, options->regs[Z80_R], options->gen.context_reg, zr_off(Z80_R), SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3205 } else if (options->regs[reg] >= 0) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3206 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, zr_off(reg), size);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3207 if (reg == Z80_R) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3208 and_irdisp(code, 0x80, options->gen.context_reg, zr_off(reg), SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3209 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3210 }
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3211 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3212 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3213 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3214 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3215 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3216 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3217 }
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3218 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3219 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3220 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3221 retn(code);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3222
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3223 options->load_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3224 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3225 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3226 options->gen.load_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3227 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3228 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3229 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3230 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3231 if (i < Z80_I) {
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3232 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3233 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3234 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3235 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3236 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3237 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3238 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3239 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3240 }
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3241 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3242 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3243 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3244 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3245 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3246 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3247 }
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3248 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3249 sub_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3250 retn(code);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3251
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3252 options->native_addr = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3253 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3254 push_r(code, options->gen.context_reg);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	3255 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D);
92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	3256 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3257 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3258 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3259 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3260 retn(code);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3261
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3262 uint32_t tmp_stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3263
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3264 options->gen.handle_cycle_limit = code->cur;
900 30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3265 //calculate call/stack adjust size
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3266 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3267 call_noalign(code, options->gen.handle_cycle_limit);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3268 uint32_t call_adjust_size = code->cur - options->gen.handle_cycle_limit;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3269 code->cur = options->gen.handle_cycle_limit;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3270
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3271 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3272 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3273 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3274 code_ptr no_sync = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3275 jcc(code, CC_B, no_sync);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3276 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3277 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3278 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3279 call(code, options->save_context_scratch);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3280 tmp_stack_off = code->stack_off;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3281 pop_r(code, RAX); //return address in read/write func
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3282 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3283 pop_r(code, RBX); //return address in translated code
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3284 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
900 30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3285 sub_ir(code, call_adjust_size, RAX, SZ_PTR); //adjust return address to point to the call + stack adjust that got us here
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3286 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3287 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	3288 restore_callee_save_regs(code);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3289 //return to caller of z80_run
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3290 retn(code);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3291
598 faad1927d836 Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80 Michael Pavone <pavone@retrodev.com> parents: 597 diff changeset	3292 *no_sync = code->cur - (no_sync + 1);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3293 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3294 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3295 retn(code);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3296 code->stack_off = tmp_stack_off;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3297
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3298 options->gen.handle_code_write = (code_ptr)z80_handle_code_write;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3299
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3300 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3301 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3302
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3303 code_ptr skip_int = code->cur;
900 30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3304 //calculate adjust size
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3305 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3306 uint32_t adjust_size = code->cur - skip_int;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3307 code->cur = skip_int;
30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3308
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3309 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3310 code_ptr skip_sync = code->cur + 1;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3311 jcc(code, CC_B, skip_sync);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3312 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3313 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3314 //save PC
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3315 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, pc), SZ_D);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3316 options->do_sync = code->cur;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3317 call(code, options->gen.save_context);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3318 tmp_stack_off = code->stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3319 //pop return address off the stack and save for resume later
898 2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	3320 //pop_rind(code, options->gen.context_reg);
2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	3321 pop_r(code, RAX);
900 30efd12b1be1 Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts Michael Pavone <pavone@retrodev.com> parents: 899 diff changeset	3322 add_ir(code, adjust_size, RAX, SZ_PTR);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3323 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
898 2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	3324 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	3325
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3326 //restore callee saved registers
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3327 restore_callee_save_regs(code);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3328 //return to caller of z80_run
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3329 retn(code);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3330 *skip_sync = code->cur - (skip_sync+1);
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3331 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3332 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3333 retn(code);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3334 code->stack_off = tmp_stack_off;
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3335
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3336 options->gen.handle_cycle_limit_int = code->cur;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3337 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3338 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3339 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3340 jcc(code, CC_B, skip_int);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3341 //set limit to the cycle limit
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3342 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.scratch2, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3343 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3344 neg_r(code, options->gen.cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3345 add_rr(code, options->gen.scratch2, options->gen.cycles, SZ_D);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3346 //disable interrupts
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3347 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	3348 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3349 cycles(&options->gen, 7);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3350 //save return address (in scratch1) to Z80 stack
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3351 sub_ir(code, 2, options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3352 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3353 //we need to do check_cycles and cycles outside of the write_8 call
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3354 //so that the stack has the correct depth if we need to return to C
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3355 //for a synchronization
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3356 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3357 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3358 //save word to write before call to write_8_noinc
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3359 push_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3360 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3361 //restore word to write
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3362 pop_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3363 //write high byte to SP+1
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3364 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3365 add_ir(code, 1, options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3366 shr_ir(code, 8, options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3367 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3368 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3369 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3370 //dispose of return address as we'll be jumping somewhere else
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3371 add_ir(code, 16, RSP, SZ_PTR);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3372 //TODO: Support interrupt mode 0 and 2
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3373 mov_ir(code, 0x38, options->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3374 call(code, options->native_addr);
663 7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	3375 mov_rrind(code, options->gen.scratch1, options->gen.context_reg, SZ_PTR);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3376 tmp_stack_off = code->stack_off;
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	3377 restore_callee_save_regs(code);
663 7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	3378 //return to caller of z80_run to sync
7a5461001242 Sync Z80 when taking an interrupt so that int_cycle gets updated Michael Pavone <pavone@retrodev.com> parents: 662 diff changeset	3379 retn(code);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3380 code->stack_off = tmp_stack_off;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3381
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3382 //HACK
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3383 options->gen.address_size = SZ_D;
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3384 options->gen.address_mask = 0xFF;
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3385 options->read_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, READ_8, NULL);
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3386 options->write_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, WRITE_8, NULL);
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3387 options->gen.address_size = SZ_W;
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3388 options->gen.address_mask = 0xFFFF;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3389
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3390 options->read_16 = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3391 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3392 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3393 //TODO: figure out how to handle the extra wait state for word reads to bank area
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	3394 //may also need special handling to avoid too much stack depth when access is blocked
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3395 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3396 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3397 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	3398 #ifndef X86_64
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	3399 //scratch 2 is a caller save register in 32-bit builds and may be clobbered by something called from the read8 fun
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	3400 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	3401 #endif
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3402 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3403 add_ir(code, 1, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3404 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3405 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3406 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3407 shl_ir(code, 8, options->gen.scratch1, SZ_W);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	3408 #ifdef X86_64
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3409 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B);
735 539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	3410 #else
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	3411 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch1, SZ_B);
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function. Michael Pavone <pavone@retrodev.com> parents: 734 diff changeset	3412 #endif
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3413 retn(code);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3414
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3415 options->write_16_highfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3416 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3417 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3418 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3419 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3420 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3421 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3422 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3423 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3424 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3425 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3426 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3427 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3428 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3429 retn(code);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3430
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3431 options->write_16_lowfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3432 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3433 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3434 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3435 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3436 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3437 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3438 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3439 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3440 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3441 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3442 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3443 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3444 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3445 retn(code);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3446
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3447 options->retrans_stub = code->cur;
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3448 tmp_stack_off = code->stack_off;
899 07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3449 //calculate size of patch
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3450 mov_ir(code, 0x7FFF, options->gen.scratch1, SZ_D);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3451 code->stack_off += sizeof(void *);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3452 if (code->stack_off & 0xF) {
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3453 sub_ir(code, 16 - (code->stack_off & 0xF), RSP, SZ_PTR);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3454 }
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3455 call_noalign(code, options->retrans_stub);
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3456 uint32_t patch_size = code->cur - options->retrans_stub;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3457 code->cur = options->retrans_stub;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3458 code->stack_off = tmp_stack_off;
07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3459
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3460 //pop return address
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3461 pop_r(code, options->gen.scratch2);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3462 add_ir(code, 16-sizeof(void*), RSP, SZ_PTR);
13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3463 code->stack_off = tmp_stack_off;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3464 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3465 //adjust pointer before move and call instructions that got us here
899 07bfbbbb4b2e Fix for Z80 retranslation post alignment rework Michael Pavone <pavone@retrodev.com> parents: 898 diff changeset	3466 sub_ir(code, patch_size, options->gen.scratch2, SZ_PTR);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3467 push_r(code, options->gen.context_reg);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	3468 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3469 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3470 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3471 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3472 jmp_r(code, options->gen.scratch1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3473
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3474 options->run = (z80_run_fun)code->cur;
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3475 tmp_stack_off = code->stack_off;
665 d0943769353b Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64 Michael Pavone <pavone@retrodev.com> parents: 664 diff changeset	3476 save_callee_save_regs(code);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	3477 #ifdef X86_64
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3478 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR);
729 9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	3479 #else
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	3480 mov_rdispr(code, RSP, 5 * sizeof(int32_t), options->gen.context_reg, SZ_PTR);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken Michael Pavone <pavone@retrodev.com> parents: 716 diff changeset	3481 #endif
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	3482 call(code, options->load_context_scratch);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3483 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3484 code_ptr no_extra = code->cur+1;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3485 jcc(code, CC_Z, no_extra);
898 2f1157f00dc6 Z80 core is now slightly less broken Michael Pavone <pavone@retrodev.com> parents: 895 diff changeset	3486 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3487 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc));
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3488 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3489 *no_extra = code->cur - (no_extra + 1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	3490 jmp_rind(code, options->gen.context_reg);
895 13388ab6d78a Get Z80 core sort of working again post alignment change Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	3491 code->stack_off = tmp_stack_off;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	3492 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3493
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	3494 void init_z80_context(z80_context * context, z80_options * options)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3495 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3496 memset(context, 0, sizeof(*context));
360 c42fae88d346 Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error Mike Pavone <pavone@retrodev.com> parents: 335 diff changeset	3497 context->static_code_map = malloc(sizeof(*context->static_code_map));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	3498 context->static_code_map->base = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3499 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3500 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
627 c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	3501 context->banked_code_map = malloc(sizeof(native_map_slot));
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses Michael Pavone <pavone@retrodev.com> parents: 626 diff changeset	3502 memset(context->banked_code_map, 0, sizeof(native_map_slot));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3503 context->options = options;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3504 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3505 context->int_pulse_start = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3506 context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3507 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3508
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3509 void z80_run(z80_context * context, uint32_t target_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3510 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3511 if (context->reset \|\| context->busack) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3512 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3513 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3514 if (context->current_cycle < target_cycle) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3515 //busreq is sampled at the end of an m-cycle
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3516 //we can approximate that by running for a single m-cycle after a bus request
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3517 context->sync_cycle = context->busreq ? context->current_cycle + 3*context->options->gen.clock_divider : target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3518 if (!context->native_pc) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3519 context->native_pc = z80_get_native_address_trans(context, context->pc);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3520 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3521 while (context->current_cycle < context->sync_cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3522 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3523 if (context->int_pulse_end < context->current_cycle \|\| context->int_pulse_end == CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3524 z80_next_int_pulse(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3525 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3526 if (context->iff1) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3527 context->int_cycle = context->int_pulse_start < context->int_enable_cycle ? context->int_enable_cycle : context->int_pulse_start;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3528 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3529 context->int_cycle = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3530 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3531 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
670 f4f3e74b0ce6 Restore Z80 interrupt pulse duration and make a small improvement to debug print output Michael Pavone <pavone@retrodev.com> parents: 668 diff changeset	3532 dprintf("Running Z80 from cycle %d to cycle %d. Int cycle: %d (%d - %d)\n", context->current_cycle, context->sync_cycle, context->int_cycle, context->int_pulse_start, context->int_pulse_end);
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3533 context->options->run(context);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3534 dprintf("Z80 ran to cycle %d\n", context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3535 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3536 if (context->busreq) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3537 context->busack = 1;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3538 context->current_cycle = target_cycle;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3539 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3540 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3541 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3542 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3543
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	3544 void z80_options_free(z80_options *opts)
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	3545 {
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	3546 free(opts->gen.native_code_map);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	3547 free(opts->gen.ram_inst_sizes);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	3548 free(opts);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	3549 }
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 854 diff changeset	3550
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3551 void z80_assert_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3552 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3553 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3554 context->reset = 1;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3555 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3556
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3557 void z80_clear_reset(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3558 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3559 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3560 if (context->reset) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3561 //TODO: Handle case where reset is not asserted long enough
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	3562 context->im = 0;
200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	3563 context->iff1 = context->iff2 = 0;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3564 context->native_pc = NULL;
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	3565 context->extra_pc = NULL;
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3566 context->pc = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3567 context->reset = 0;
676 41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	3568 if (context->busreq) {
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	3569 //TODO: Figure out appropriate delay
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	3570 context->busack = 1;
41a399c11ef1 When going directly from reset to busreq, do not allow the Z80 to run Michael Pavone <pavone@retrodev.com> parents: 670 diff changeset	3571 }
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3572 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3573 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3574
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3575 void z80_assert_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3576 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3577 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3578 context->busreq = 1;
854 adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3579 //this is an imperfect aproximation since most M-cycles take less tstates than the max
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3580 //and a short 3-tstate m-cycle can take an unbounded number due to wait states
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3581 if (context->current_cycle - cycle > MAX_MCYCLE_LENGTH * context->options->gen.clock_divider) {
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3582 context->busack = 1;
adeb6465ad53 Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time Michael Pavone <pavone@retrodev.com> parents: 844 diff changeset	3583 }
701 200ee73c7210 Remove/comment verbose logging added for tracking down sync bug Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	3584 }
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3585
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3586 void z80_clear_busreq(z80_context * context, uint32_t cycle)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3587 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3588 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3589 context->busreq = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3590 context->busack = 0;
844 74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests Michael Pavone <pavone@retrodev.com> parents: 842 diff changeset	3591 //there appears to be at least a 1 Z80 cycle delay between busreq
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests Michael Pavone <pavone@retrodev.com> parents: 842 diff changeset	3592 //being released and resumption of execution
74e161fe7d39 Small tweaks to timing of 68K/Z80 interactions based on latest tests Michael Pavone <pavone@retrodev.com> parents: 842 diff changeset	3593 context->current_cycle += context->options->gen.clock_divider;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3594 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3595
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3596 uint8_t z80_get_busack(z80_context * context, uint32_t cycle)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3597 {
668 5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3598 z80_run(context, cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3599 return context->busack;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3600 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3601
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3602 void z80_adjust_cycles(z80_context * context, uint32_t deduction)
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3603 {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3604 if (context->current_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3605 fprintf(stderr, "WARNING: Deduction of %u cycles when Z80 cycle counter is only %u\n", deduction, context->current_cycle);
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3606 context->current_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3607 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3608 context->current_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3609 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3610 if (context->int_enable_cycle != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3611 if (context->int_enable_cycle < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3612 context->int_enable_cycle = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3613 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3614 context->int_enable_cycle -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3615 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3616 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3617 if (context->int_pulse_start != CYCLE_NEVER) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3618 if (context->int_pulse_end < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3619 context->int_pulse_start = context->int_pulse_end = CYCLE_NEVER;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3620 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3621 context->int_pulse_end -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3622 if (context->int_pulse_start < deduction) {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3623 context->int_pulse_start = 0;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3624 } else {
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3625 context->int_pulse_start -= deduction;
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3626 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3627 }
5439ae7946ca Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	3628 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3629 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3630
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3631 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3632 {
966 f765c2fc7508 Fix crash bug in Z80 debugger introduced with stack alignment changes Michael Pavone <pavone@retrodev.com> parents: 900 diff changeset	3633 code_info code = {dst, dst+32};
659 759c38bf97f8 Minor Z80 core cleanup Michael Pavone <pavone@retrodev.com> parents: 657 diff changeset	3634 mov_ir(&code, address, context->options->gen.scratch1, SZ_W);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3635 call(&code, context->bp_stub);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3636 return code.cur-dst;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3637 }
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3638
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3639 void zcreate_stub(z80_context * context)
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3640 {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3641 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3642 code_info *code = &opts->gen.code;
894 a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted. Michael Pavone <pavone@retrodev.com> parents: 884 diff changeset	3643 uint32_t start_stack_off = code->stack_off;
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3644 check_code_prologue(code);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3645 context->bp_stub = code->cur;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3646
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3647 //Calculate length of prologue
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3648 check_cycles_int(&opts->gen, 0);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3649 int check_int_size = code->cur-context->bp_stub;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3650 code->cur = context->bp_stub;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3651
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3652 //Calculate length of patch
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3653 int patch_size = zbreakpoint_patch(context, 0, code->cur);
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3654
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3655 //Save context and call breakpoint handler
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3656 call(code, opts->gen.save_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3657 push_r(code, opts->gen.scratch1);
657 92ce5ea5ffc9 Use call_args and call_args_abi in Z80 core Michael Pavone <pavone@retrodev.com> parents: 653 diff changeset	3658 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	3659 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3660 //Restore context
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3661 call(code, opts->gen.load_context);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3662 pop_r(code, opts->gen.scratch1);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3663 //do prologue stuff
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3664 or_rr(code, opts->gen.cycles, opts->gen.cycles, SZ_D);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3665 uint8_t * jmp_off = code->cur+1;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 1046 diff changeset	3666 jcc(code, CC_NS, code->cur + 7);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3667 pop_r(code, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	3668 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3669 push_r(code, opts->gen.scratch1);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3670 jmp(code, opts->gen.handle_cycle_limit_int);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3671 *jmp_off = code->cur - (jmp_off+1);
682 7ed1dbb48f61 Merge Michael Pavone <pavone@retrodev.com> parents: 676 559 diff changeset	3672 //jump back to body of translated instruction
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3673 pop_r(code, opts->gen.scratch1);
664 bca748422bf0 Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat Michael Pavone <pavone@retrodev.com> parents: 663 diff changeset	3674 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR);
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3675 jmp_r(code, opts->gen.scratch1);
894 a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted. Michael Pavone <pavone@retrodev.com> parents: 884 diff changeset	3676 code->stack_off = start_stack_off;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3677 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3678
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3679 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3680 {
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3681 context->bp_handler = bp_handler;
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3682 uint8_t bit = 1 << (address % 8);
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3683 if (!(bit & context->breakpoint_flags[address / 8])) {
ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3684 context->breakpoint_flags[address / 8] \|= bit;
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3685 if (!context->bp_stub) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3686 zcreate_stub(context);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3687 }
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3688 uint8_t * native = z80_get_native_address(context, address);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3689 if (native) {
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3690 zbreakpoint_patch(context, address, native);
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3691 }
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3692 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3693 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	3694
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3695 void zremove_breakpoint(z80_context * context, uint16_t address)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3696 {
819 ab017fb09e77 Added support for an IO memory map in Z80 core Michael Pavone <pavone@retrodev.com> parents: 792 diff changeset	3697 context->breakpoint_flags[address / 8] &= ~(1 << (address % 8));
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3698 uint8_t * native = z80_get_native_address(context, address);
626 7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded Michael Pavone <pavone@retrodev.com> parents: 625 diff changeset	3699 if (native) {
652 f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3700 z80_options * opts = context->options;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3701 code_info tmp_code = opts->gen.code;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3702 opts->gen.code.cur = native;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3703 opts->gen.code.last = native + 16;
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3704 check_cycles_int(&opts->gen, address);
f822d9216968 Merge Michael Pavone <pavone@retrodev.com> parents: 620 651 diff changeset	3705 opts->gen.code = tmp_code;
792 724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows). Michael Pavone <pavone@retrodev.com> parents: 755 diff changeset	3706 }
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3707 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	3708

Mercurial > repos > blastem

annotate z80_to_x86.c @ 1086:f0a1e0a2263c