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annotate vdp.c @ 1334:7757d605e365

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Adjust how the invalid size is handled for the horizontal dimmension of a plane. Fixes some garbage on the spinning cube scene of Overdrive 2
author Michael Pavone <pavone@retrodev.com>
date Thu, 27 Apr 2017 09:32:21 -0700
parents 69c25e1188e5
children 26e72126f9d1
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1 /*
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2 Copyright 2013 Michael Pavone
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include "vdp.h"
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7 #include "blastem.h"
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8 #include "genesis.h"
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9 #include <stdlib.h>
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10 #include <string.h>
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11 #include "render.h"
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12 #include "util.h"
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13
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14 #define NTSC_INACTIVE_START 224
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15 #define PAL_INACTIVE_START 240
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16 #define MODE4_INACTIVE_START 192
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17 #define BUF_BIT_PRIORITY 0x40
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18 #define MAP_BIT_PRIORITY 0x8000
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19 #define MAP_BIT_H_FLIP 0x800
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20 #define MAP_BIT_V_FLIP 0x1000
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21
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3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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22 #define SCROLL_BUFFER_SIZE 32
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23 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
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24 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
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25
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26 #define MCLKS_SLOT_H40 16
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27 #define MCLKS_SLOT_H32 20
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28 #define VINT_SLOT_H40 0 //21 slots before HSYNC, 16 during, 10 after
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29 #define VINT_SLOT_H32 0 //old value was 23, but recent tests suggest the actual value is close to the H40 one
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30 #define VINT_SLOT_MODE4 4
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31 #define HSYNC_SLOT_H40 230
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32 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17)
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33 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results
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34 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results
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35 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result
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36 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results
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37 #define LINE_CHANGE_H40 165
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38 #define LINE_CHANGE_H32 133
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39 #define LINE_CHANGE_MODE4 249
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40 #define VBLANK_START_H40 (LINE_CHANGE_H40+2)
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41 #define VBLANK_START_H32 (LINE_CHANGE_H32+2)
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42 #define FIFO_LATENCY 3
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43
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44 #define BORDER_TOP_V24 27
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45 #define BORDER_TOP_V28 11
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46 #define BORDER_TOP_V24_PAL 54
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47 #define BORDER_TOP_V28_PAL 38
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48 #define BORDER_TOP_V30_PAL 30
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49
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50 #define BORDER_BOT_V24 24
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51 #define BORDER_BOT_V28 8
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52 #define BORDER_BOT_V24_PAL 48
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53 #define BORDER_BOT_V28_PAL 32
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54 #define BORDER_BOT_V30_PAL 24
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55
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56 #define INVALID_LINE 0x200
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57
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58 enum {
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59 INACTIVE = 0,
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60 PREPARING, //used for line 0x1FF
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61 ACTIVE
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62 };
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63
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64 static int32_t color_map[1 << 12];
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65 static uint16_t mode4_address_map[0x4000];
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66 static uint32_t planar_to_chunky[256];
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67 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
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68
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69 static uint8_t debug_base[][3] = {
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70 {127, 127, 127}, //BG
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71 {0, 0, 127}, //A
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72 {127, 0, 0}, //Window
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73 {0, 127, 0}, //B
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74 {127, 0, 127} //Sprites
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75 };
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76
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77 static void update_video_params(vdp_context *context)
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78 {
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79 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
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80 if (context->regs[REG_MODE_2] & BIT_PAL) {
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81 if (context->flags2 & FLAG2_REGION_PAL) {
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82 context->inactive_start = PAL_INACTIVE_START;
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83 context->border_top = BORDER_TOP_V30_PAL;
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84 context->border_bot = BORDER_BOT_V30_PAL;
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85 } else {
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86 //the behavior here is rather weird and needs more investigation
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87 context->inactive_start = 0xF0;
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88 context->border_top = 1;
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89 context->border_bot = 3;
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90 }
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91 } else {
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92 context->inactive_start = NTSC_INACTIVE_START;
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93 if (context->flags2 & FLAG2_REGION_PAL) {
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94 context->border_top = BORDER_TOP_V28_PAL;
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95 context->border_bot = BORDER_BOT_V28_PAL;
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96 } else {
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97 context->border_top = BORDER_TOP_V28;
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98 context->border_bot = BORDER_TOP_V28;
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99 }
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100 }
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101 if (context->state == INACTIVE) {
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102 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active
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103 if (context->vcounter < context->inactive_start) {
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104 context->state = ACTIVE;
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105 } else if (context->vcounter == 0x1FF) {
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106 context->state = PREPARING;
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107 }
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108 }
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109 } else {
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110 context->inactive_start = MODE4_INACTIVE_START;
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111 if (context->flags2 & FLAG2_REGION_PAL) {
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112 context->border_top = BORDER_TOP_V24_PAL;
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113 context->border_bot = BORDER_BOT_V24_PAL;
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114 } else {
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115 context->border_top = BORDER_TOP_V24;
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116 context->border_bot = BORDER_BOT_V24;
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117 }
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118 if (!(context->regs[REG_MODE_1] & BIT_MODE_4)){
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
119 context->state = INACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
120 } else if (context->state == INACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
121 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
122 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
123 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
124 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
125 /*
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
126 FIXME: uncomment this once mode 4 renderer is updated to handle this
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
127 else if (context->vcounter == 0x1FF) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
128 context->state = PREPARING;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
129 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
130 */
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
131 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
132 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
133 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
134
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
135 static uint8_t color_map_init_done;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
136
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
137 void init_vdp_context(vdp_context * context, uint8_t region_pal)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
138 {
58
a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents: 56
diff changeset
139 memset(context, 0, sizeof(*context));
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
140 context->vdpmem = malloc(VRAM_SIZE);
58
a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents: 56
diff changeset
141 memset(context->vdpmem, 0, VRAM_SIZE);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
142 /*
488
32f053ad9b02 Basic OpenGL rendering is working
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
143 */
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
144 if (headless) {
1168
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
145 context->output = malloc(LINEBUF_SIZE * sizeof(uint32_t));
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
146 context->output_pitch = 0;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
147 } else {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
148 context->fb = render_get_framebuffer(FRAMEBUFFER_ODD, &context->output_pitch);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
149 }
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
150 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
151 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
152 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE;
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
153 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE;
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
154 context->sprite_draws = MAX_DRAWS;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
155 context->fifo_write = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
156 context->fifo_read = -1;
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
157 context->regs[REG_HINT] = context->hint_counter = 0xFF;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
158
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
159 if (!color_map_init_done) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
160 uint8_t b,g,r;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
161 for (uint16_t color = 0; color < (1 << 12); color++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
162 if (color & FBUF_SHADOW) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
163 b = levels[(color >> 9) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
164 g = levels[(color >> 5) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
165 r = levels[(color >> 1) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
166 } else if(color & FBUF_HILIGHT) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
167 b = levels[((color >> 9) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
168 g = levels[((color >> 5) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
169 r = levels[((color >> 1) & 0x7) + 7];
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
170 } else if(color & FBUF_MODE4) {
1127
cb4771f4543a Fix Mode 4 color mapping
Michael Pavone <pavone@retrodev.com>
parents: 1125
diff changeset
171 b = levels[(color >> 4 & 0xC) | (color >> 6 & 0x2)];
1125
fba485949723 Brighten up Mode 4 colors
Michael Pavone <pavone@retrodev.com>
parents: 1124
diff changeset
172 g = levels[(color >> 2 & 0x8) | (color >> 1 & 0x4) | (color >> 4 & 0x2)];
fba485949723 Brighten up Mode 4 colors
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parents: 1124
diff changeset
173 r = levels[(color << 1 & 0xC) | (color >> 1 & 0x2)];
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
174 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
175 b = levels[(color >> 8) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
176 g = levels[(color >> 4) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
177 r = levels[color & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
178 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
179 color_map[color] = render_map_color(r, g, b);
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
180 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
181 for (uint16_t mode4_addr = 0; mode4_addr < 0x4000; mode4_addr++)
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
182 {
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
183 uint16_t mode5_addr = mode4_addr & 0x3DFD;
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
184 mode5_addr |= mode4_addr << 8 & 0x200;
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
185 mode5_addr |= mode4_addr >> 8 & 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
186 mode4_address_map[mode4_addr] = mode5_addr;
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
187 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
188 for (uint32_t planar = 0; planar < 256; planar++)
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
189 {
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
190 uint32_t chunky = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
191 for (int bit = 7; bit >= 0; bit--)
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
192 {
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
193 chunky = chunky << 4;
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
194 chunky |= planar >> bit & 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
195 }
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
196 planar_to_chunky[planar] = chunky;
e9369d6f0101 Somewhat broken implementation of Mode 4
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parents: 1117
diff changeset
197 }
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
198 color_map_init_done = 1;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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parents: 424
diff changeset
199 }
437
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
200 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++)
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
201 {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
202 uint8_t src = color & DBG_SRC_MASK;
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
203 if (src > DBG_SRC_S) {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
204 context->debugcolors[color] = 0;
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
205 } else {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
206 uint8_t r,g,b;
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parents: 436
diff changeset
207 b = debug_base[src][0];
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parents: 436
diff changeset
208 g = debug_base[src][1];
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parents: 436
diff changeset
209 r = debug_base[src][2];
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
210 if (color & DBG_PRIORITY)
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
211 {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
212 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
213 b += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
214 }
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
215 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
216 g += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
217 }
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
218 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
219 r += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
220 }
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
221 }
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
222 if (color & DBG_SHADOW) {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
223 b /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
224 g /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
225 r /=2 ;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
226 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
227 if (color & DBG_HILIGHT) {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
228 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
229 b += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
230 }
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
231 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
232 g += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
233 }
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
234 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
235 r += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
236 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
237 }
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
238 context->debugcolors[color] = render_map_color(r, g, b);
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
239 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
240 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
241 if (region_pal) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
242 context->flags2 |= FLAG2_REGION_PAL;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
243 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
244 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
245 if (!headless) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
246 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * context->border_top);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
247 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
248 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
249
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
250 void vdp_free(vdp_context *context)
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
251 {
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
252 free(context->vdpmem);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
253 free(context->linebuf);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
254 free(context);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
255 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
256
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
257 static int is_refresh(vdp_context * context, uint32_t slot)
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
258 {
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
259 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
260 return slot == 250 || slot == 26 || slot == 59 || slot == 90 || slot == 122 || slot == 154;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
261 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
262 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
263 //These numbers are guesses based on H40 numbers
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
264 return slot == 243 || slot == 19 || slot == 51 || slot == 83 || slot == 115;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
265 //The numbers below are the refresh slots during active display
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
266 //return (slot == 29 || slot == 61 || slot == 93 || slot == 125);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
267 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
268 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
269
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
270 static void increment_address(vdp_context *context)
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
271 {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
272 context->address += context->regs[REG_AUTOINC];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
273 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
274 context->address++;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
275 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
276 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
277
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
278 static void render_sprite_cells(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
279 {
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
280 if (context->cur_slot >= context->sprite_draws) {
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
281 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
282
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
283 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
284 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
285 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
286 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
287 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
288 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
289 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
290 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
291 }
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
292 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
293 context->cur_slot--;
143
e5487ef04619 Fix infinite loop bug in sprite rendering
Mike Pavone <pavone@retrodev.com>
parents: 142
diff changeset
294 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
1029
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
295 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
296 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
297 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
298 } else if (context->vdpmem[address] >> 4) {
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
299 context->flags2 |= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
300 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
301 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 x += dir;
1029
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
303 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
304 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
305 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
306 } else if (context->vdpmem[address] & 0xF) {
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
307 context->flags2 |= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
308 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
312 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
313 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
315 static void fetch_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
316 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
317 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
318 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
319 uint32_t address = mode4_address_map[d->address & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
320 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
321 context->fetch_tmp[1] = context->vdpmem[address + 1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
322 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
323 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
324
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
325 static void render_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
326 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
327 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
328 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
329 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
330 pixels |= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
331 uint32_t address = mode4_address_map[(d->address + 2) & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
332 pixels |= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
333 pixels |= planar_to_chunky[context->vdpmem[address + 1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
334 int x = d->x_pos & 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
335 for (int i = 28; i >= 0; i -= 4, x++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
336 {
1155
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
337 if (context->linebuf[x] && (pixels >> i & 0xF)) {
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
338 if (
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
339 ((context->regs[REG_MODE_1] & BIT_SPRITE_8PX) && x > 8)
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
340 || ((!(context->regs[REG_MODE_1] & BIT_SPRITE_8PX)) && x < 256)
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
341 ) {
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
342 context->flags2 |= FLAG2_SPRITE_COLLIDE;
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
343 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
344 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
345 context->linebuf[x] = pixels >> i & 0xF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
346 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
347 }
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
348 context->sprite_index--;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
349 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
350 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
351
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
352 static uint32_t mode5_sat_address(vdp_context *context)
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
353 {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
354 uint32_t addr = context->regs[REG_SAT] << 9;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
355 if (!(context->regs[REG_MODE_2] & BIT_128K_VRAM)) {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
356 addr &= 0xFFFF;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
357 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
358 if (context->regs[REG_MODE_4] & BIT_H40) {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
359 addr &= 0x1FC00;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
360 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
361 return addr;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
362 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
363
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
364 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
365 {
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
366 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
367 uint16_t sat_address = mode5_sat_address(context);
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
368 uint16_t current_index = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
369 uint8_t count = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
370 do {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
371 uint16_t address = current_index * 8 + sat_address;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
372 uint16_t cache_address = current_index * 4;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
373 uint8_t height = ((context->sat_cache[cache_address+2] & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
374 uint8_t width = (((context->sat_cache[cache_address+2] >> 2) & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
375 int16_t y = ((context->sat_cache[cache_address] & 0x3) << 8 | context->sat_cache[cache_address+1]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
376 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
377 uint16_t link = context->sat_cache[cache_address+3] & 0x7F;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
378 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
379 uint8_t pri = context->vdpmem[address + 4] >> 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
380 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
381 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
382 current_index = link;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
383 count++;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
384 } while (current_index != 0 && count < 80);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
385 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
386 uint16_t sat_address = (context->regs[REG_SAT] & 0x7E) << 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
387 for (int i = 0; i < 64; i++)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
388 {
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
389 uint8_t y = context->vdpmem[mode4_address_map[sat_address + (i ^ 1)]];
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
390 if (y == 0xD0) {
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
391 break;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
392 }
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
393 uint8_t x = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2 + 1]];
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
394 uint16_t tile_address = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2]] * 32
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
395 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
396 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
397 tile_address &= ~32;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
398 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
399 printf("Sprite %d: X=%d, Y=%d, Pat=%X\n", i, x, y, tile_address);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
400 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
401 }
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
402 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
403
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
404 #define VRAM_READ 0 //0000
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
405 #define VRAM_WRITE 1 //0001
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
406 //2 would trigger register write 0010
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
407 #define CRAM_WRITE 3 //0011
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
408 #define VSRAM_READ 4 //0100
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
409 #define VSRAM_WRITE 5//0101
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
410 //6 would trigger regsiter write 0110
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
411 //7 is a mystery //0111
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
412 #define CRAM_READ 8 //1000
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
413 //9 is also a mystery //1001
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
414 //A would trigger register write 1010
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
415 //B is a mystery 1011
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
416 #define VRAM_READ8 0xC //1100
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
417 //D is a mystery 1101
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
418 //E would trigger register write 1110
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
419 //F is a mystery 1111
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
420
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
421 //Possible theory on how bits work
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
422 //CD0 = Read/Write flag
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
423 //CD2,(CD1|CD3) = RAM type
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
424 // 00 = VRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
425 // 01 = CRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
426 // 10 = VSRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
427 // 11 = VRAM8
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
428 //Would result in
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
429 // 7 = VRAM8 write
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
430 // 9 = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
431 // B = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
432 // D = VRAM8 write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
433 // F = VRAM8 write alais
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
434
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
435 #define DMA_START 0x20
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
436
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
437 static const char * cd_name(uint8_t cd)
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
438 {
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
439 switch (cd & 0xF)
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
440 {
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
441 case VRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
442 return "VRAM read";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
443 case VRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
444 return "VRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
445 case CRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
446 return "CRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
447 case VSRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
448 return "VSRAM read";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
449 case VSRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
450 return "VSRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
451 case VRAM_READ8:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
452 return "VRAM read (undocumented 8-bit mode)";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
453 default:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
454 return "invalid";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
455 }
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
456 }
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
457
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
458 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
459 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
460 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
461 printf("**Mode Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
462 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1331
9bba5ff5beb8 Add 128K VRAM bit to VDP register print in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1325
diff changeset
463 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d, %dK VRAM\n"
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
464 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
465 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n",
757
483f7e7926a6 More clang warning cleanup
Michael Pavone <pavone@retrodev.com>
parents: 748
diff changeset
466 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", (context->regs[REG_MODE_1] & BIT_PAL_SEL) != 0,
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
467 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
468 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
1331
9bba5ff5beb8 Add 128K VRAM bit to VDP register print in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1325
diff changeset
469 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, context->regs[REG_MODE_1] & BIT_128K_VRAM ? 128 : 64,
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
470 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
471 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
472 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
473 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
474 printf("\n**Table Group**\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
475 "02: %.2X | Scroll A Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
476 "03: %.2X | Window Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
477 "04: %.2X | Scroll B Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
478 "05: %.2X | Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
479 "0D: %.2X | HScroll Data Table: $%.4X\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
480 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
481 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
482 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
483 context->regs[REG_SAT], mode5_sat_address(context),
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
484 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
485 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
486 printf("\n**Table Group**\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
487 "02: %.2X | Background Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
488 "05: %.2X | Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
489 "06: %.2X | Sprite Tile Base: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
490 "08: %.2X | Background X Scroll: %d\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
491 "09: %.2X | Background Y Scroll: %d\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
492 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0xE) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
493 context->regs[REG_SAT], (context->regs[REG_SAT] & 0x7E) << 7,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
494 context->regs[REG_STILE_BASE], (context->regs[REG_STILE_BASE] & 2) << 11,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
495 context->regs[REG_X_SCROLL], context->regs[REG_X_SCROLL],
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
496 context->regs[REG_Y_SCROLL], context->regs[REG_Y_SCROLL]);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
497
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
498 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
499 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
500 printf("\n**Misc Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
501 "07: %.2X | Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
502 "0A: %.2X | H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
503 "0F: %.2X | Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
504 "10: %.2X | Scroll A/B Size: %sx%s\n",
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
505 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR],
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
506 context->regs[REG_HINT], context->regs[REG_HINT],
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
507 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
508 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
509 char * src_types[] = {"68K", "68K", "Copy", "Fill"};
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
510 printf("\n**DMA Group**\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
511 "13: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
512 "14: %.2X | DMA Length: $%.4X words\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
513 "15: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
514 "16: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
515 "17: %.2X | DMA Source Address: $%.6X, Type: %s\n",
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
516 context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
517 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
518 context->regs[REG_DMASRC_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
519 context->regs[REG_DMASRC_M],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
520 context->regs[REG_DMASRC_H],
629
9089951a1994 Small fix to display of DMA source address in vr debug command
Michael Pavone <pavone@retrodev.com>
parents: 624
diff changeset
521 context->regs[REG_DMASRC_H] << 17 | context->regs[REG_DMASRC_M] << 9 | context->regs[REG_DMASRC_L] << 1,
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
522 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]);
438
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
523 printf("\n**Internal Group**\n"
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
524 "Address: %X\n"
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
525 "CD: %X - %s\n"
647
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
526 "Pending: %s\n"
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
527 "VCounter: %d\n"
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
528 "HCounter: %d\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
529 "VINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
530 "HINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
531 "Status: %X\n",
1150
322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1149
diff changeset
532 context->address, context->cd, cd_name(context->cd),
322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1149
diff changeset
533 (context->flags & FLAG_PENDING) ? "word" : (context->flags2 & FLAG2_BYTE_PENDING) ? "byte" : "none",
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
534 context->vcounter, context->hslot*2, (context->flags2 & FLAG2_VINT_PENDING) ? "true" : "false",
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
535 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context));
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
536
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
537 //TODO: Window Group, DMA Group
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
538 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
539
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
540 static uint8_t is_active(vdp_context *context)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
541 {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
542 return context->state != INACTIVE && (context->regs[REG_MODE_2] & BIT_DISP_EN) != 0;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
543 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
544
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
545 static void scan_sprite_table(uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
547 if (context->sprite_index && context->slot_counter) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
548 line += 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
549 line &= 0xFF;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
550 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
551 uint8_t height_mult;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
552 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
553 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
554 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
555 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
556 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
557 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
558 ymin = 256;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
559 height_mult = 16;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
560 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
561 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
562 ymin = 128;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
563 height_mult = 8;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
564 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
565 context->sprite_index &= 0x7F;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
566 if (context->regs[REG_MODE_4] & BIT_H40) {
38
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
567 if (context->sprite_index >= MAX_SPRITES_FRAME) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
568 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
569 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
570 }
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
571 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) {
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
572 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
573 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
574 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
575 uint16_t address = context->sprite_index * 4;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
576 line += ymin;
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
577 uint16_t y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
578 uint8_t height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
579 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
580 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
581 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
582 context->sprite_info_list[--(context->slot_counter)].size = context->sat_cache[address+2];
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
583 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
584 context->sprite_info_list[context->slot_counter].y = y-ymin;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
585 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
586 context->sprite_index = context->sat_cache[address+3] & 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
587 if (context->sprite_index && context->slot_counter)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
588 {
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
589 if (context->regs[REG_MODE_4] & BIT_H40) {
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
590 if (context->sprite_index >= MAX_SPRITES_FRAME) {
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
591 context->sprite_index = 0;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
592 return;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
593 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
594 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) {
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
595 context->sprite_index = 0;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
596 return;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
597 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
598 address = context->sprite_index * 4;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
599 y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
600 height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
601 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
602 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
603 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
604 context->sprite_info_list[--(context->slot_counter)].size = context->sat_cache[address+2];
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
605 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
606 context->sprite_info_list[context->slot_counter].y = y-ymin;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
607 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
608 context->sprite_index = context->sat_cache[address+3] & 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
609 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
610 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
611 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
612
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
613 static void scan_sprite_table_mode4(vdp_context * context)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
614 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
615 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
616 uint32_t line = context->vcounter;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
617 line &= 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
618
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
619 uint32_t sat_address = mode4_address_map[(context->regs[REG_SAT] << 7 & 0x3F00) + context->sprite_index];
1138
25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping
Michael Pavone <pavone@retrodev.com>
parents: 1137
diff changeset
620 uint32_t y = context->vdpmem[sat_address+1];
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
621 uint32_t size = (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) ? 16 : 8;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
622
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
623 if (y == 0xd0) {
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
624 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
625 return;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
626 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
627 if (y <= line && line < (y + size)) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
628 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
629 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
630 context->flags |= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
631 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
632 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
633 context->sprite_info_list[--(context->slot_counter)].size = size;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
634 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
635 context->sprite_info_list[context->slot_counter].y = y;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
636 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
637 context->sprite_index++;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
638 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
639
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
640 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1138
25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping
Michael Pavone <pavone@retrodev.com>
parents: 1137
diff changeset
641 y = context->vdpmem[sat_address];
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
642 if (y == 0xd0) {
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
643 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
644 return;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
645 } else {
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
646 if (y <= line && line < (y + size)) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
647 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
648 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
649 context->flags |= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
650 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
651 }
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
652 context->sprite_info_list[--(context->slot_counter)].size = size;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
653 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
654 context->sprite_info_list[context->slot_counter].y = y;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
655 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
656 context->sprite_index++;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
657 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
658 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
659
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
660 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
661 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
662
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
663 static void read_sprite_x(uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
664 {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
665 if (context->cur_slot >= context->slot_counter) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
666 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
667 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
668 line &= 0xFF;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
669 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
670 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
671 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
672 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
673 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
674 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
675 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
676 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
677 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
678 height *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
679 }
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
680 uint16_t att_addr = mode5_sat_address(context) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
681 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1];
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
682 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
683 uint8_t row;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
684 if (tileinfo & MAP_BIT_V_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
685 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
686 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
687 row = line-context->sprite_info_list[context->cur_slot].y;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
688 }
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
689 uint16_t address;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
690 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
691 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
692 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
693 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
694 }
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
695 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
696 if (x) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
697 context->flags |= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
698 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
699 context->flags |= FLAG_MASKED;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
700 }
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
701
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
702 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
703 int16_t i;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
704 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
705 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
706 --context->sprite_draws;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
707 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
708 }
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
709 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
710 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
711 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
712 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
713 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
714 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
715 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
716 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
717 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
718 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
719 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35
233c7737c152 Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents: 34
diff changeset
720 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
721 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
722 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
723 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
724 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
725 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
726 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
727 }
1000
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
728 //Used to be i < width
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
729 //TODO: Confirm this is the right condition on hardware
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
730 if (!context->sprite_draws) {
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
731 context->flags |= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
732 }
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
733 context->cur_slot--;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
734 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
735 context->flags |= FLAG_DOT_OFLOW;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
736 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
737 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
738 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
739
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
740 static void read_sprite_x_mode4(vdp_context * context)
427
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
741 {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
742 if (context->cur_slot >= context->slot_counter) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
743 uint32_t address = (context->regs[REG_SAT] << 7 & 0x3F00) + 0x80 + context->sprite_info_list[context->cur_slot].index * 2;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
744 address = mode4_address_map[address];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
745 --context->sprite_draws;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
746 uint32_t tile_address = context->vdpmem[address] * 32 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
747 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
748 tile_address &= ~32;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
749 }
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
750 tile_address += (context->vcounter - context->sprite_info_list[context->cur_slot].y)* 4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
751 context->sprite_draw_list[context->sprite_draws].x_pos = context->vdpmem[address + 1];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
752 context->sprite_draw_list[context->sprite_draws].address = tile_address;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
753 context->cur_slot--;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
754 }
427
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
755 }
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
756
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
757 #define CRAM_BITS 0xEEE
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
758 #define VSRAM_BITS 0x7FF
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
759 #define VSRAM_DIRTY_BITS 0xF800
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
760
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
761 //rough estimate of slot number at which border display starts
1270
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
762 #define BG_START_SLOT 6
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
763
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
764 void write_cram(vdp_context * context, uint16_t address, uint16_t value)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
765 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
766 uint16_t addr;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
767 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
768 addr = (address/2) & (CRAM_SIZE-1);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
769 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
770 addr = address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
771 value = (value << 1 & 0xE) | (value << 2 & 0xE0) | (value & 0xE00);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
772 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
773 context->cram[addr] = value;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
774 context->colors[addr] = color_map[value & CRAM_BITS];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
775 context->colors[addr + CRAM_SIZE] = color_map[(value & CRAM_BITS) | FBUF_SHADOW];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
776 context->colors[addr + CRAM_SIZE*2] = color_map[(value & CRAM_BITS) | FBUF_HILIGHT];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
777 context->colors[addr + CRAM_SIZE*3] = color_map[(value & CRAM_BITS) | FBUF_MODE4];
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
778
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
779 if (context->hslot >= BG_START_SLOT && (
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
780 context->vcounter < context->inactive_start + context->border_bot
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
781 || context->vcounter > 0x200 - context->border_top
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
782 )) {
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
783 uint8_t bg_end_slot = BG_START_SLOT + (context->regs[REG_MODE_4] & BIT_H40) ? LINEBUF_SIZE/2 : (256+HORIZ_BORDER)/2;
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
784 if (context->hslot < bg_end_slot) {
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
785 uint32_t color = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->colors[addr] : context->colors[addr + CRAM_SIZE*3];
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
786 context->output[(context->hslot - BG_START_SLOT)*2 + 1] = color;
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
787 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
788 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
789 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
790
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
791 static void vdp_advance_dma(vdp_context * context)
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
792 {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
793 context->regs[REG_DMASRC_L] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
794 if (!context->regs[REG_DMASRC_L]) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
795 context->regs[REG_DMASRC_M] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
796 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
797 context->address += context->regs[REG_AUTOINC];
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
798 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
799 context->regs[REG_DMALEN_H] = dma_len >> 8;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
800 context->regs[REG_DMALEN_L] = dma_len;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
801 if (!dma_len) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
802 context->flags &= ~FLAG_DMA_RUN;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
803 context->cd &= 0xF;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
804 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
805 }
1019
e34334e6c682 Fix GST savestate loading to deal with SAT cache to fix sprite corruption on savestate load. Clear out Z80 native_pc so the Z80 state does not get hosed when loading a savestate while the emulator is already running
Michael Pavone <pavone@retrodev.com>
parents: 1001
diff changeset
806
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
807 static void vdp_check_update_sat(vdp_context *context, uint32_t address, uint16_t value)
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
808 {
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
809 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
810 if (!(address & 4)) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
811 uint32_t sat_address = mode5_sat_address(context);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
812 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
813 uint16_t cache_address = address - sat_address;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
814 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
815 context->sat_cache[cache_address] = value >> 8;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
816 context->sat_cache[cache_address^1] = value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
817 }
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
818 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
819 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
820 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
821
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
822 void vdp_check_update_sat_byte(vdp_context *context, uint32_t address, uint8_t value)
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
823 {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
824 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
825 if (!(address & 4)) {
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
826 uint32_t sat_address = mode5_sat_address(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
827 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
828 uint16_t cache_address = address - sat_address;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
829 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
830 context->sat_cache[cache_address] = value;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
831 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
832 }
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
833 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
834 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
835
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
836 static void write_vram_word(vdp_context *context, uint32_t address, uint16_t value)
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
837 {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
838 address = (address & 0x3FC) | (address >> 1 & 0xFC01) | (address >> 9 & 0x2);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
839 address ^= 1;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
840 //TODO: Support an option to actually have 128KB of VRAM
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
841 context->vdpmem[address] = value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
842 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
843
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
844 static void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value)
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
845 {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
846 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
847 address &= 0xFFFF;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
848 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
849 address = mode4_address_map[address & 0x3FFF];
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
850 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
851 context->vdpmem[address] = value;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
852 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
853
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
854 static void external_slot(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
855 {
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
856 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && context->fifo_read < 0) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
857 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
858 fifo_entry * cur = context->fifo + context->fifo_read;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
859 cur->cycle = context->cycles;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
860 cur->address = context->address;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
861 cur->partial = 2;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
862 vdp_advance_dma(context);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
863 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
864 fifo_entry * start = context->fifo + context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
865 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
866 switch (start->cd & 0xF)
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
867 {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
868 case VRAM_WRITE:
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
869 if ((context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) == (BIT_128K_VRAM|BIT_MODE_5)) {
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
870 vdp_check_update_sat(context, start->address, start->value);
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
871 write_vram_word(context, start->address, start->value);
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
872 } else if (start->partial) {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
873 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
874 uint8_t byte = start->partial == 2 ? start->value >> 8 : start->value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
875 if (start->partial > 1) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
876 vdp_check_update_sat_byte(context, start->address ^ 1, byte);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
877 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
878 write_vram_byte(context, start->address ^ 1, byte);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
879 } else {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
880 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
881 vdp_check_update_sat(context, start->address, start->value);
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
882 write_vram_byte(context, start->address, start->value >> 8);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
883 start->partial = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
884 //skip auto-increment and removal of entry from fifo
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
885 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
886 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
887 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
888 case CRAM_WRITE: {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
889 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
890 if (start->partial == 3) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
891 uint16_t val;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
892 if ((start->address & 1) && (context->regs[REG_MODE_2] & BIT_MODE_5)) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
893 val = (context->cram[start->address >> 1 & (CRAM_SIZE-1)] & 0xFF) | start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
894 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
895 uint16_t address = (context->regs[REG_MODE_2] & BIT_MODE_5) ? start->address >> 1 & (CRAM_SIZE-1) : start->address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
896 val = (context->cram[address] & 0xFF00) | start->value;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
897 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
898 write_cram(context, start->address, val);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
899 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
900 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
901 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
902 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
903 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
904 case VSRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
905 if (((start->address/2) & 63) < VSRAM_SIZE) {
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
906 //printf("VSRAM Write: %X to %X @ vcounter: %d, hslot: %d, cycle: %d\n", start->value, context->address, context->vcounter, context->hslot, context->cycles);
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
907 if (start->partial == 3) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
908 if (start->address & 1) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
909 context->vsram[(start->address/2) & 63] &= 0xFF;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
910 context->vsram[(start->address/2) & 63] |= start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
911 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
912 context->vsram[(start->address/2) & 63] &= 0xFF00;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
913 context->vsram[(start->address/2) & 63] |= start->value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
914 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
915 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
916 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
917 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
918 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
919
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
920 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
921 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
922 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
923 if (context->fifo_read == context->fifo_write) {
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
924 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
925 context->flags |= FLAG_DMA_RUN;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
926 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
927 context->fifo_read = -1;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
928 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
929 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
930 if (context->flags & FLAG_READ_FETCHED) {
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
931 write_vram_byte(context, context->address ^ 1, context->prefetch);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
932
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
933 //Update DMA state
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
934 vdp_advance_dma(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
935
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
936 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
937 } else {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
938 context->prefetch = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
939
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
940 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
941 }
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
942 } else if (!(context->cd & 1) && !(context->flags & (FLAG_READ_FETCHED|FLAG_PENDING))) {
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
943 switch(context->cd & 0xF)
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
944 {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
945 case VRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
946 if (context->flags2 & FLAG2_READ_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
947 context->prefetch |= context->vdpmem[context->address | 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
948 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
949 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
950 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
951 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
952 } else {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
953 //TODO: 128K VRAM Mode
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
954 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
955 context->flags2 |= FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
956 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
957 break;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
958 case VRAM_READ8: {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
959 uint32_t address = context->address ^ 1;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
960 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
961 address = mode4_address_map[address & 0x3FFF];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
962 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
963 context->prefetch = context->vdpmem[address];
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
964 context->prefetch |= context->fifo[context->fifo_write].value & 0xFF00;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
965 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
966 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
967 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
968 break;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
969 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
970 case CRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
971 context->prefetch = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
972 context->prefetch |= context->fifo[context->fifo_write].value & ~CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
973 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
974 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
975 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
976 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
977 case VSRAM_READ: {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
978 uint16_t address = (context->address /2) & 63;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
979 if (address >= VSRAM_SIZE) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
980 address = 0;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
981 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
982 context->prefetch = context->vsram[address] & VSRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
983 context->prefetch |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
984 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
985 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
986 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
987 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
988 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
989 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
990 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
991 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
992
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
993 static void run_dma_src(vdp_context * context, int32_t slot)
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
994 {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
995 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
996 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
997 if (context->fifo_write == context->fifo_read) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
998 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
999 }
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1000 fifo_entry * cur = NULL;
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1001 if (!(context->regs[REG_DMASRC_H] & 0x80))
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1002 {
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1003 //68K -> VDP
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
1004 if (slot == -1 || !is_refresh(context, slot-1)) {
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1005 cur = context->fifo + context->fifo_write;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
1006 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1007 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1008 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1009 cur->cd = context->cd;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1010 cur->partial = 0;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1011 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1012 context->fifo_read = context->fifo_write;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1013 }
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1014 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1015 vdp_advance_dma(context);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1016 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1017 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1018 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1019
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1020 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1021 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1022
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1023 static void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1024 {
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1025 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1026 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1027 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
1028 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1029 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1030 }
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1031 window_line_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1032 v_offset_mask = 0xF;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1033 vscroll_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1034 } else {
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1035 window_line_shift = 3;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1036 v_offset_mask = 0x7;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1037 vscroll_shift = 3;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1038 }
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1039 if (!vsram_off) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1040 uint16_t left_col, right_col;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1041 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
920
e64168bb2b25 Fix calculation of window start column when it's on the right side. This removes graphical glitches in Afterburner 2, Fireshark and Dungeons and Dragons: Warriors of the Eternal Sun and probably others
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
1042 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2 + 2;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1043 right_col = 42;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1044 } else {
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1045 left_col = 0;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1046 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1047 if (right_col) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1048 right_col += 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1049 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1050 }
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1051 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1052 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1053 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1054 bottom_line = context->double_res ? 481 : 241;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1055 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1056 top_line = 0;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1057 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1058 }
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1059 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1060 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1061 uint16_t line_offset, offset, mask;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
1062 if (context->regs[REG_MODE_4] & BIT_H40) {
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1063 address &= 0xF000;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1064 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1065 mask = 0x7F;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
1066
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1067 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1068 address &= 0xF800;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1069 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1070 mask = 0x3F;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1071 }
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1072 if (context->double_res) {
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1073 mask <<= 1;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1074 mask |= 1;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1075 }
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
1076 offset = address + line_offset + (((column - 2) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1077 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1078 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
1079 offset = address + line_offset + (((column - 1) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1080 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1081 context->v_offset = (line) & v_offset_mask;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1082 context->flags |= FLAG_WINDOW;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1083 return;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1084 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1085 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1086 }
1290
aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk
Michael Pavone <pavone@retrodev.com>
parents: 1289
diff changeset
1087 //TODO: Verify behavior for 0x20 case
aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk
Michael Pavone <pavone@retrodev.com>
parents: 1289
diff changeset
1088 uint16_t vscroll = 0xFF | (context->regs[REG_SCROLL] & 0x30) << 4;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1089 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1090 vscroll <<= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1091 vscroll |= 1;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1092 }
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1093 //TODO: Further research on vscroll latch behavior and the "first column bug"
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1094 if (!column) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1095 if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1096 if (context->regs[REG_MODE_4] & BIT_H40) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1097 //Based on observed behavior documented by Eke-Eke, I'm guessing the VDP
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1098 //ends up fetching the last value on the VSRAM bus in the H40 case
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1099 //getting the last latched value should be close enough for now
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1100 if (!vsram_off) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1101 context->vscroll_latch[0] = context->vscroll_latch[1];
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1102 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1103 } else {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1104 //supposedly it's always forced to 0 in the H32 case
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1105 context->vscroll_latch[0] = context->vscroll_latch[1] = 0;
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1106 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1107 } else {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1108 context->vscroll_latch[vsram_off] = context->vsram[vsram_off];
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1109 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
1110 } else if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
710
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents: 708
diff changeset
1111 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off];
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents: 708
diff changeset
1112 }
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents: 708
diff changeset
1113 vscroll &= context->vscroll_latch[vsram_off] + line;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1114 context->v_offset = vscroll & v_offset_mask;
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
1115 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1116 vscroll >>= vscroll_shift;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1117 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1118 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1119 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1120 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1121 case 0:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1122 hscroll_mask = 0x1F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1123 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1124 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1125 case 0x1:
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1126 hscroll_mask = 0x3F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1127 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1128 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1129 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1130 //TODO: Verify this behavior
1334
7757d605e365 Adjust how the invalid size is handled for the horizontal dimmension of a plane. Fixes some garbage on the spinning cube scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1333
diff changeset
1131 hscroll_mask = 0x1F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1132 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1133 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1134 case 0x3:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1135 hscroll_mask = 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1136 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1137 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1138 }
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1139 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1140 for (int i = 0; i < 2; i++) {
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1141 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1142 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1143 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1144 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1145 if (i) {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1146 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1147 } else {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1148 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1149 }
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1150 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1151 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1152
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1153 static void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1154 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
1155 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1156 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1157
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1158 static void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1159 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
1160 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1161 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1162
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1163 static void read_map_mode4(uint16_t column, uint32_t line, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1164 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1165 uint32_t address = (context->regs[REG_SCROLL_A] & 0xE) << 10;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1166 //add row
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1167 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1168 if (column < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1169 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1170 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1171 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1172 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1173 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1174 address += (vscroll >> 3) * 2 * 32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1175 //add column
1136
52f25c41abdd Fix horizontal scrolling in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1135
diff changeset
1176 address += ((column - (context->hscroll_a >> 3)) & 31) * 2;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1177 //adjust for weird VRAM mapping in Mode 4
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1178 address = mode4_address_map[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1179 context->col_1 = (context->vdpmem[address] << 8) | context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1180 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1181
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1182 static void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1183 {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1184 uint16_t address;
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1185 uint16_t vflip_base;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1186 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1187 address = ((col & 0x3FF) << 6);
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1188 vflip_base = 60;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1189 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1190 address = ((col & 0x7FF) << 5);
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1191 vflip_base = 28;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1192 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1193 if (col & MAP_BIT_V_FLIP) {
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1194 address += vflip_base - 4 * context->v_offset;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1195 } else {
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1196 address += 4 * context->v_offset;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1197 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1198 uint16_t pal_priority = (col >> 9) & 0x70;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1199 int32_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1200 if (col & MAP_BIT_H_FLIP) {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1201 offset += 7;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1202 offset &= SCROLL_BUFFER_MASK;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1203 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1204 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1205 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1206 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1207 for (uint32_t i=0; i < 4; i++, address++)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1208 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1209 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1210 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1211 offset &= SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1212 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1213 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1214 offset &= SCROLL_BUFFER_MASK;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1215 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1216 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1217
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1218 static void render_map_1(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1219 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1220 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1221 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1222
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1223 static void render_map_2(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1224 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1225 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1226 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1227
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1228 static void render_map_3(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1229 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1230 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1231 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1232
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1233 static void fetch_map_mode4(uint16_t col, uint32_t line, vdp_context *context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1234 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1235 //calculate pixel row to fetch
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1236 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1237 if (col < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1238 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1239 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1240 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1241 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1242 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1243 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1244 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1245 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1246 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1247
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1248 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1249 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1250 context->fetch_tmp[1] = context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1251 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1252
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1253 static void render_map_output(uint32_t line, int32_t col, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1254 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1255 uint32_t *dst;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1256 if (context->state == PREPARING) {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1257 if (!col) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1258 return;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1259 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1260 col -= 2;
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1261 if (col) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1262 dst = context->output + BORDER_LEFT + col * 8;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1263 } else {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1264 dst = context->output;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1265 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1266 for (int i = 0; i < BORDER_LEFT; i++, dst++)
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1267 {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1268 *dst = bg_color;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1269 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1270 }
1170
9170fc4d9835 Don't adjust cycles every frame. Only when we start getting close to UINT_MAX. Don't adjust all the way down to zero when we do adjust. Shouldn't fix anything, but may make debugging current issues easier.
Michael Pavone <pavone@retrodev.com>
parents: 1169
diff changeset
1271 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1272 for (int i = 0; i < 16; i++)
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1273 {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1274 *(dst++) = color;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1275 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1276 return;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1277 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1278 line &= 0xFF;
1180
e2b81a0f8fd8 Undo poorly thought out minor optimization that screwed up rendering
Michael Pavone <pavone@retrodev.com>
parents: 1179
diff changeset
1279 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1280 uint8_t *sprite_buf, *plane_a, *plane_b;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1281 int plane_a_off, plane_b_off;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1282 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1283 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1284 col-=2;
1270
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1285 if (col) {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1286 dst = context->output + BORDER_LEFT + col * 8;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1287 } else {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1288 dst = context->output;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1289 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1290 for (int i = 0; i < BORDER_LEFT; i++, dst++)
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1291 {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1292 *dst = bg_color;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1293 }
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
1294 }
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1295 if (context->debug < 2) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1296 sprite_buf = context->linebuf + col * 8;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1297 uint8_t a_src, src;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1298 if (context->flags & FLAG_WINDOW) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1299 plane_a_off = context->buf_a_off;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1300 a_src = DBG_SRC_W;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1301 } else {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1302 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF);
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1303 a_src = DBG_SRC_A;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1304 }
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1305 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF);
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1306 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1307 uint8_t output_disabled = (context->test_port & TEST_BIT_DISABLE) != 0;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1308 uint8_t test_layer = context->test_port >> 7 & 3;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
1309
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1310 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1311 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1312 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1313 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
748
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1314 uint8_t pixel = context->regs[REG_BG_COLOR];
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1315 uint32_t *colors = context->colors;
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1316 src = DBG_SRC_BG;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1317 if (*plane_b & 0xF) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1318 pixel = *plane_b;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1319 src = DBG_SRC_B;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1320 }
748
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1321 uint8_t intensity = *plane_b & BUF_BIT_PRIORITY;
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1322 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1323 pixel = *plane_a;
1315
810ae0287d66 Fix minor bug that displayed window plane as if it were plane A In plane debug view
Michael Pavone <pavone@retrodev.com>
parents: 1299
diff changeset
1324 src = a_src;
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1325 }
748
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1326 intensity |= *plane_a & BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1327 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1328 if ((*sprite_buf & 0x3F) == 0x3E) {
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1329 intensity += BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1330 } else if ((*sprite_buf & 0x3F) == 0x3F) {
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1331 intensity = 0;
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1332 } else {
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1333 pixel = *sprite_buf;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1334 src = DBG_SRC_S;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1335 if ((pixel & 0xF) == 0xE) {
748
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1336 intensity = BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1337 } else {
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1338 intensity |= pixel & BUF_BIT_PRIORITY;
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1339 }
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1340 }
748
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1341 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1342 if (output_disabled) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1343 pixel = 0x3F;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1344 }
748
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1345 if (!intensity) {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
1346 src |= DBG_SHADOW;
748
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1347 colors += CRAM_SIZE;
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1348 } else if (intensity == BUF_BIT_PRIORITY*2) {
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1349 src |= DBG_HILIGHT;
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1350 colors += CRAM_SIZE*2;
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1351 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1352 //TODO: Verify how test register stuff interacts with shadow/highlight
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1353 //TODO: Simulate CRAM corruption from bus fight
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1354 switch (test_layer)
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1355 {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1356 case 1:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1357 pixel &= *sprite_buf;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1358 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1359 src = DBG_SRC_S;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1360 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1361 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1362 case 2:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1363 pixel &= *plane_a;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1364 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1365 src = DBG_SRC_A;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1366 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1367 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1368 case 3:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1369 pixel &= *plane_b;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1370 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1371 src = DBG_SRC_B;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1372 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1373 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1374 }
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
1375
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1376 uint32_t outpixel;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1377 if (context->debug) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1378 outpixel = context->debugcolors[src];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1379 } else {
748
45b62d237b7b Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents: 724
diff changeset
1380 outpixel = colors[pixel & 0x3F];
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1381 }
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1382 *(dst++) = outpixel;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1383 }
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1384 } else {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1385 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1386 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1387 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1388 uint8_t pixel = context->regs[REG_BG_COLOR];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1389 src = DBG_SRC_BG;
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1390 if (output_disabled) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1391 pixel = 0x3F;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1392 } else {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1393 if (*plane_b & 0xF) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1394 pixel = *plane_b;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1395 src = DBG_SRC_B;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1396 }
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1397 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1398 pixel = *plane_a;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1399 src = a_src;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1400 }
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1401 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1402 pixel = *sprite_buf;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1403 src = DBG_SRC_S;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1404 }
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1405 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1406 //TODO: Simulate CRAM corruption from bus fight
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1407 switch (test_layer)
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1408 {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1409 case 1:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1410 pixel &= *sprite_buf;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1411 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1412 src = DBG_SRC_S;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1413 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1414 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1415 case 2:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1416 pixel &= *plane_a;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1417 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1418 src = DBG_SRC_A;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1419 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1420 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1421 case 3:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1422 pixel &= *plane_b;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1423 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1424 src = DBG_SRC_B;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1425 }
1322
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents: 1321
diff changeset
1426 break;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
1427 }
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1428 uint32_t outpixel;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1429 if (context->debug) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1430 outpixel = context->debugcolors[src];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1431 } else {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1432 outpixel = context->colors[pixel & 0x3F];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1433 }
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1434 *(dst++) = outpixel;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
1435 }
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1436 }
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1437 } else if (context->debug == 2) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1438 if (col < 32) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1439 *(dst++) = context->colors[col * 2];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1440 *(dst++) = context->colors[col * 2];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1441 *(dst++) = context->colors[col * 2];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1442 *(dst++) = context->colors[col * 2];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1443 *(dst++) = context->colors[col * 2 + 1];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1444 *(dst++) = context->colors[col * 2 + 1];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1445 *(dst++) = context->colors[col * 2 + 1];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1446 *(dst++) = context->colors[col * 2 + 1];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1447 *(dst++) = context->colors[col * 2 + 2];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1448 *(dst++) = context->colors[col * 2 + 2];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1449 *(dst++) = context->colors[col * 2 + 2];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1450 *(dst++) = context->colors[col * 2 + 2];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1451 *(dst++) = context->colors[col * 2 + 3];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1452 *(dst++) = context->colors[col * 2 + 3];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1453 *(dst++) = context->colors[col * 2 + 3];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1454 *(dst++) = context->colors[col * 2 + 3];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1455 } else if (col == 32 || line >= 192) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1456 for (int32_t i = 0; i < 16; i ++) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1457 *(dst++) = 0;
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
1458 }
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1459 } else {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1460 for (int32_t i = 0; i < 16; i ++) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1461 *(dst++) = context->colors[line / 3 + (col - 34) * 0x20];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1462 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1463 }
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
1464 } else {
771
0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents: 757
diff changeset
1465 uint32_t base = (context->debug - 3) * 0x200;
0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents: 757
diff changeset
1466 uint32_t cell = base + (line / 8) * (context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32) + col;
0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents: 757
diff changeset
1467 uint32_t address = (cell * 32 + (line % 8) * 4) & 0xFFFF;
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1468 for (int32_t i = 0; i < 4; i ++) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1469 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] >> 4)];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1470 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] & 0xF)];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1471 address++;
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1472 }
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1473 cell++;
771
0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents: 757
diff changeset
1474 address = (cell * 32 + (line % 8) * 4) & 0xFFFF;
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1475 for (int32_t i = 0; i < 4; i ++) {
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1476 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] >> 4)];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1477 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] & 0xF)];
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1478 address++;
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
1479 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1480 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1481 }
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1482 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1483 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1484 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1485
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1486 static void render_map_mode4(uint32_t line, int32_t col, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1487 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1488 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1489 if (col < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1490 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1491 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1492 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1493 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1494 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1495 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1496 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1497 //vflip
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1498 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1499 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1500
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1501 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1502 pixels |= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1503
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1504 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4 + 2];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1505 pixels |= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1506 pixels |= planar_to_chunky[context->vdpmem[address+1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1507
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1508 int i, i_inc, i_limit;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1509 if (context->col_1 & 0x200) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1510 //hflip
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1511 i = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1512 i_inc = 4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1513 i_limit = 32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1514 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1515 i = 28;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1516 i_inc = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1517 i_limit = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1518 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1519 uint8_t pal_priority = (context->col_1 >> 7 & 0x10) | (context->col_1 >> 6 & 0x40);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1520 for (uint8_t *dst = context->tmp_buf_a + context->buf_a_off; i != i_limit; i += i_inc, dst++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1521 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1522 *dst = (pixels >> i & 0xF) | pal_priority;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1523 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1524 context->buf_a_off = (context->buf_a_off + 8) & 15;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1525
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1526 uint8_t bgcolor = 0x10 | (context->regs[REG_BG_COLOR] & 0xF) + CRAM_SIZE*3;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1527 uint32_t *dst = context->output + col * 8;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1528 if (context->debug < 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1529 if (col || !(context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1530 uint8_t *sprite_src = context->linebuf + col * 8;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1531 if (context->regs[REG_MODE_1] & BIT_SPRITE_8PX) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1532 sprite_src += 8;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1533 }
1121
1913f9c28003 Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents: 1120
diff changeset
1534 for (int i = 0; i < 8; i++, sprite_src++)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1535 {
1121
1913f9c28003 Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents: 1120
diff changeset
1536 uint8_t *bg_src = context->tmp_buf_a + ((8 + i + col * 8 - (context->hscroll_a & 0x7)) & 15);
1132
fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents: 1127
diff changeset
1537 if ((*bg_src & 0x4F) > 0x40 || !*sprite_src) {
fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents: 1127
diff changeset
1538 //background plane has priority and is opaque or sprite layer is transparent
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1539 if (context->debug) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1540 *(dst++) = context->debugcolors[DBG_SRC_A];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1541 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1542 *(dst++) = context->colors[(*bg_src & 0x1F) + CRAM_SIZE*3];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1543 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1544 } else {
1132
fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents: 1127
diff changeset
1545 //sprite layer is opaque and not covered by high priority BG pixels
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1546 if (context->debug) {
1132
fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents: 1127
diff changeset
1547 *(dst++) = context->debugcolors[DBG_SRC_S];
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1548 } else {
1132
fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents: 1127
diff changeset
1549 *(dst++) = context->colors[*sprite_src | 0x10 + CRAM_SIZE*3];
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1550 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1551 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1552 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1553 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1554 for (int i = 0; i < 8; i++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1555 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1556 *(dst++) = context->colors[bgcolor];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1557 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1558 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1559 } else if (context->debug == 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1560 for (int i = 0; i < 8; i++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1561 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1562 *(dst++) = context->colors[CRAM_SIZE*3 + col];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1563 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1564 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1565 uint32_t cell = (line / 8) * 32 + col;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1566 uint32_t address = cell * 32 + (line % 8) * 4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1567 uint32_t m4_address = mode4_address_map[address & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1568 uint32_t pixel = planar_to_chunky[context->vdpmem[m4_address]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1569 pixel |= planar_to_chunky[context->vdpmem[m4_address + 1]];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1570 m4_address = mode4_address_map[(address + 2) & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1571 pixel |= planar_to_chunky[context->vdpmem[m4_address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1572 pixel |= planar_to_chunky[context->vdpmem[m4_address + 1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1573 if (context->debug_pal < 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1574 for (int i = 28; i >= 0; i -= 4)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1575 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1576 *(dst++) = context->colors[CRAM_SIZE*3 | (context->debug_pal << 4) | (pixel >> i & 0xF)];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1577 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1578 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1579 for (int i = 28; i >= 0; i -= 4)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1580 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1581 uint8_t value = (pixel >> i & 0xF) * 17;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1582 if (context->debug_pal == 3) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1583 value = 255 - value;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1584 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1585 *(dst++) = render_map_color(value, value, value);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1586 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1587 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1588 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1589 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1590
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1591 static uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19};
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1592
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1593 static void vdp_advance_line(vdp_context *context)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1594 {
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1595 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1596 static uint32_t last_line = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1597 if (last_line != 0xFFFFFFFF) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1598 uint32_t diff = context->cycles - last_line;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1599 if (diff != MCLKS_LINE) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1600 printf("Line %d took %d cycles\n", context->vcounter, diff);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1601 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1602 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1603 last_line = context->cycles;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1604 #endif
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1605 context->vcounter++;
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1606
1156
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1607 uint8_t is_mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1608 if (is_mode_5) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1609 if (context->flags2 & FLAG2_REGION_PAL) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1610 if (context->regs[REG_MODE_2] & BIT_PAL) {
1156
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1611 if (context->vcounter == 0x10B) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1612 context->vcounter = 0x1D2;
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1613 }
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1614 } else if (context->vcounter == 0x103){
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1615 context->vcounter = 0x1CA;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1616 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1617 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1618 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1619 if (context->vcounter == 0x100) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1620 context->vcounter = 0x1FA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1621 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1622 } else if (context->vcounter == 0xEB) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1623 context->vcounter = 0x1E5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1624 }
1299
da1ffc4026c4 Fix latching of V32 mode bit
Michael Pavone <pavone@retrodev.com>
parents: 1290
diff changeset
1625 }
1156
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1626 } else if (context->vcounter == 0xDB) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1627 context->vcounter = 0x1D5;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1628 }
1273
6dedaa645843 Fix graphical corruption and sprite flickering introduced into some games by the last change for horizontal border support
Michael Pavone <pavone@retrodev.com>
parents: 1272
diff changeset
1629 context->vcounter &= 0x1FF;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1630 if (context->state == PREPARING) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1631 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1632 }
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1633
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1634 if (context->state != ACTIVE) {
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1635 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1636 } else if (context->hint_counter) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1637 context->hint_counter--;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1638 } else {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1639 context->flags2 |= FLAG2_HINT_PENDING;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1640 context->pending_hint_start = context->cycles;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1641 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1642 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1643 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1644
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1645 static void advance_output_line(vdp_context *context)
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1646 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1647 if (headless) {
1168
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
1648 if (context->vcounter == context->inactive_start) {
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
1649 context->frame++;
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
1650 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1651 context->vcounter &= 0x1FF;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1652 } else {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1653 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1654 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1655 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1656
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1657 if (context->output_lines == lines_max) {
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
1658 render_framebuffer_updated(context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN: FRAMEBUFFER_ODD, context->h40_lines > (context->inactive_start + context->border_top) / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
1659 if (context->double_res) {
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
1660 context->flags2 ^= FLAG2_EVEN_FIELD;
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
1661 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1662 context->fb = render_get_framebuffer(context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN : FRAMEBUFFER_ODD, &context->output_pitch);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1663 context->h40_lines = 0;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1664 context->frame++;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1665 context->output_lines = 0;
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1666 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1667 uint32_t output_line;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1668 if (context->vcounter < context->inactive_start + context->border_bot && context->output_lines > 0) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1669 output_line = context->output_lines++;//context->border_top + context->vcounter;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1670 } else if (context->vcounter >= 0x200 - context->border_top) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1671 output_line = context->output_lines++;//context->vcounter - (0x200 - context->border_top);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1672 } else {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1673 output_line = INVALID_LINE;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1674 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1675 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * output_line);
1271
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1676 #ifdef DEBUG_FB_FILL
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1677 for (int i = 0; i < LINEBUF_SIZE; i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1678 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1679 context->output[i] = 0xFFFF00FF;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1680 }
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1681 #endif
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1682 if (output_line != INVALID_LINE && (context->regs[REG_MODE_4] & BIT_H40)) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1683 context->h40_lines++;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
1684 }
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
1685 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1686 }
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1687
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1688 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; }
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
1689 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1690
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1691 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1692 case startcyc:\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1693 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1694 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1695 case ((startcyc+1)&0xFF):\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1696 external_slot(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1697 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1698 case ((startcyc+2)&0xFF):\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1699 render_map_1(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1700 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1701 case ((startcyc+3)&0xFF):\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1702 render_map_2(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1703 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1704 case ((startcyc+4)&0xFF):\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1705 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1706 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1707 case ((startcyc+5)&0xFF):\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1708 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1709 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1710 case ((startcyc+6)&0xFF):\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1711 render_map_3(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1712 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1713 case ((startcyc+7)&0xFF):\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1714 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1715 CHECK_LIMIT
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1716
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1717 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1718 case startcyc:\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1719 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1720 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1721 case (startcyc+1):\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1722 /* refresh, no don't run dma src */\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1723 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1724 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1725 CHECK_ONLY\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1726 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1727 render_map_1(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1728 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1729 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1730 render_map_2(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1731 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1732 case (startcyc+4):\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1733 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1734 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1735 case (startcyc+5):\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1736 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1737 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1738 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1739 render_map_3(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1740 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1741 case (startcyc+7):\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1742 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1743 CHECK_LIMIT
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1744
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1745 #define COLUMN_RENDER_BLOCK_MODE4(column, startcyc) \
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1746 case startcyc:\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1747 read_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1748 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1749 case ((startcyc+1)&0xFF):\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
1750 if (column & 3) {\
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
1751 scan_sprite_table_mode4(context);\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1752 } else {\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1753 external_slot(context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1754 }\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1755 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1756 case ((startcyc+2)&0xFF):\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1757 fetch_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1758 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1759 case ((startcyc+3)&0xFF):\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1760 render_map_mode4(context->vcounter, column, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1761 CHECK_LIMIT
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1762
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1763 #define CHECK_LIMIT_HSYNC(slot) \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1764 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1765 if (slot >= HSYNC_SLOT_H40 && slot < HSYNC_END_H40) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1766 context->cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1767 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1768 context->cycles += slot_cycles;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1769 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1770 if (slot == 182) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1771 context->hslot = 229;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1772 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1773 context->hslot++;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1774 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1775 CHECK_ONLY
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
1776
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1777 #define SPRITE_RENDER_H40(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1778 case slot:\
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1779 if ((slot) == BG_START_SLOT + LINEBUF_SIZE/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1780 advance_output_line(context);\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1781 }\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1782 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1783 scan_sprite_table(context->vcounter, context);\
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1784 CHECK_LIMIT_HSYNC(slot)
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
1785
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1786 //Note that the line advancement check will fail if BG_START_SLOT is > 6
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1787 //as we're bumping up against the hcounter jump
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1788 #define SPRITE_RENDER_H32(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1789 case slot:\
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1790 if ((slot) == BG_START_SLOT + (256+HORIZ_BORDER)/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1791 advance_output_line(context);\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1792 }\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1793 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1794 scan_sprite_table(context->vcounter, context);\
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
1795 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1796 if (slot == 147) {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1797 context->hslot = 233;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1798 } else {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1799 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1800 }\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1801 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1802 CHECK_ONLY
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1803
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1804 #define MODE4_CHECK_SLOT_LINE(slot) \
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1805 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1806 if ((slot) == 147) {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1807 context->hslot = 233;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1808 } else {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1809 context->hslot++;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1810 }\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1811 context->cycles += slot_cycles;\
1163
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
1812 if ((slot+1) == LINE_CHANGE_MODE4) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
1813 vdp_advance_line(context);\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
1814 if (context->vcounter == 192) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
1815 return;\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
1816 }\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
1817 }\
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1818 CHECK_ONLY
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1819
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1820 #define CALC_SLOT(slot, increment) ((slot+increment) > 147 && (slot+increment) < 233 ? (slot+increment-148+233): (slot+increment))
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1821
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1822 #define SPRITE_RENDER_H32_MODE4(slot) \
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1823 case slot:\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
1824 read_sprite_x_mode4(context);\
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
1825 MODE4_CHECK_SLOT_LINE(slot)\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1826 case CALC_SLOT(slot, 1):\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
1827 read_sprite_x_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1828 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot,1))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1829 case CALC_SLOT(slot, 2):\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1830 fetch_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1831 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 2))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1832 case CALC_SLOT(slot, 3):\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1833 render_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1834 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 3))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1835 case CALC_SLOT(slot, 4):\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
1836 fetch_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1837 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 4))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1838 case CALC_SLOT(slot, 5):\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
1839 render_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
1840 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 5))
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1841
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1842 static void vdp_h40(vdp_context * context, uint32_t target_cycles)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1843 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1844 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1845 uint32_t mask;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1846 uint32_t const slot_cycles = MCLKS_SLOT_H40;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1847 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1848 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1849 for (;;)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1850 {
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1851 case 165:
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1852 if (context->state == PREPARING) {
1185
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1853 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1854 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1855 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1856 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1857 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1858 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1859 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1860 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1861 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1862 *dst = bg_color;
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1863 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1864 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1865 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1866 }
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1867 CHECK_LIMIT
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1868 case 166:
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1869 if (context->state == PREPARING) {
1185
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1870 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1871 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1872 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1873 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1874 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1875 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1876 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1877 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1878 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1879 *dst = bg_color;
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1880 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1881 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1882 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1883 }
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1884 CHECK_LIMIT
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1885 //sprite attribute table scan starts
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1886 case 167:
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1887 if (context->state == PREPARING) {
1185
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1888 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1889 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1890 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1891 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1892 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1893 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1894 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1895 }
1271
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1896 for (int i = 0; i < LINEBUF_SIZE - 2 * (context->hslot - BG_START_SLOT); i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1897 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1898 *(dst++) = bg_color;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
1899 }
1185
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
1900 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1901 context->sprite_index = 0x80;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1902 context->slot_counter = MAX_SPRITES_LINE;
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
1903 render_sprite_cells( context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1904 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1905 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1906 SPRITE_RENDER_H40(168)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1907 SPRITE_RENDER_H40(169)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1908 SPRITE_RENDER_H40(170)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1909 SPRITE_RENDER_H40(171)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1910 SPRITE_RENDER_H40(172)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1911 SPRITE_RENDER_H40(173)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1912 SPRITE_RENDER_H40(174)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1913 SPRITE_RENDER_H40(175)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1914 SPRITE_RENDER_H40(176)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1915 SPRITE_RENDER_H40(177)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1916 SPRITE_RENDER_H40(178)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1917 SPRITE_RENDER_H40(179)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1918 SPRITE_RENDER_H40(180)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1919 SPRITE_RENDER_H40(181)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1920 SPRITE_RENDER_H40(182)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1921 SPRITE_RENDER_H40(229)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1922 //!HSYNC asserted
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1923 SPRITE_RENDER_H40(230)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1924 SPRITE_RENDER_H40(231)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1925 case 232:
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1926 external_slot(context);
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1927 CHECK_LIMIT_HSYNC(232)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1928 SPRITE_RENDER_H40(233)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1929 SPRITE_RENDER_H40(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1930 SPRITE_RENDER_H40(235)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1931 SPRITE_RENDER_H40(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1932 SPRITE_RENDER_H40(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1933 SPRITE_RENDER_H40(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1934 SPRITE_RENDER_H40(239)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1935 SPRITE_RENDER_H40(240)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1936 SPRITE_RENDER_H40(241)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1937 SPRITE_RENDER_H40(242)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1938 SPRITE_RENDER_H40(243)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1939 case 244:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1940 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1941 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1942 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1943 mask |= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1944 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1945 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1946 mask |= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1947 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1948 address += (context->vcounter & mask) * 4;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1949 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1950 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1951 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
1952 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1953 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1954 context->cycles += h40_hsync_cycles[14];
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1955 CHECK_ONLY
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1956 //!HSYNC high
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1957 SPRITE_RENDER_H40(245)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1958 SPRITE_RENDER_H40(246)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1959 SPRITE_RENDER_H40(247)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1960 SPRITE_RENDER_H40(248)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1961 case 249:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1962 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1963 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1964 SPRITE_RENDER_H40(250)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1965 case 251:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1966 render_map_1(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1967 scan_sprite_table(context->vcounter, context);//Just a guess
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
1968 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1969 case 252:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1970 render_map_2(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1971 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1972 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1973 case 253:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1974 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1975 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1976 SPRITE_RENDER_H40(254)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1977 case 255:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1978 render_map_3(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1979 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1980 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1981 case 0:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1982 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1983 scan_sprite_table(context->vcounter, context);//Just a guess
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1984 //reverse context slot counter so it counts the number of sprite slots
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1985 //filled rather than the number of available slots
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
1986 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
1987 context->cur_slot = MAX_SPRITES_LINE-1;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1988 context->sprite_draws = MAX_DRAWS;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
1989 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1990 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1991 COLUMN_RENDER_BLOCK(2, 1)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1992 COLUMN_RENDER_BLOCK(4, 9)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1993 COLUMN_RENDER_BLOCK(6, 17)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1994 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1995 COLUMN_RENDER_BLOCK(10, 33)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1996 COLUMN_RENDER_BLOCK(12, 41)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1997 COLUMN_RENDER_BLOCK(14, 49)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1998 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
1999 COLUMN_RENDER_BLOCK(18, 65)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2000 COLUMN_RENDER_BLOCK(20, 73)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2001 COLUMN_RENDER_BLOCK(22, 81)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2002 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2003 COLUMN_RENDER_BLOCK(26, 97)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2004 COLUMN_RENDER_BLOCK(28, 105)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2005 COLUMN_RENDER_BLOCK(30, 113)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2006 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2007 COLUMN_RENDER_BLOCK(34, 129)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2008 COLUMN_RENDER_BLOCK(36, 137)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2009 COLUMN_RENDER_BLOCK(38, 145)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2010 COLUMN_RENDER_BLOCK_REFRESH(40, 153)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2011 case 161:
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2012 external_slot(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2013 CHECK_LIMIT
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2014 case 162: {
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2015 external_slot(context);
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2016 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2017 for (int i = LINEBUF_SIZE-BORDER_RIGHT; i < LINEBUF_SIZE; i++)
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2018 {
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2019 context->output[i] = bg_color;
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2020 }
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2021 CHECK_LIMIT
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2022 }
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2023 //sprite render to line buffer starts
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2024 case 163:
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2025 context->cur_slot = MAX_DRAWS-1;
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2026 memset(context->linebuf, 0, LINEBUF_SIZE);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2027 render_sprite_cells(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2028 CHECK_LIMIT
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2029 case 164:
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2030 render_sprite_cells(context);
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2031 if (context->flags & FLAG_DMA_RUN) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2032 run_dma_src(context, -1);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2033 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2034 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2035 context->cycles += slot_cycles;
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2036 vdp_advance_line(context);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2037 if (context->vcounter == context->inactive_start) {
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2038 return;
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2039 }
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2040 CHECK_ONLY
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2041 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2042 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2043 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2044 context->cycles += slot_cycles;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2045 return;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2046 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2047 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2048
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
2049 static void vdp_h32(vdp_context * context, uint32_t target_cycles)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2050 {
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2051 uint16_t address;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2052 uint32_t mask;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2053 uint32_t const slot_cycles = MCLKS_SLOT_H32;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2054 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2055 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2056 for (;;)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2057 {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2058 case 133:
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2059 if (context->state == PREPARING) {
1185
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2060 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2061 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2062 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2063 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2064 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2065 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2066 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2067 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2068 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2069 *dst = bg_color;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2070 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2071 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2072 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2073 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2074 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2075 case 134:
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2076 if (context->state == PREPARING) {
1185
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2077 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2078 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2079 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2080 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2081 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2082 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2083 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2084 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2085 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2086 *dst = bg_color;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2087 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2088 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2089 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2090 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2091 CHECK_LIMIT
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2092 //sprite attribute table scan starts
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2093 case 135: //FIXME - Here
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2094 if (context->state == PREPARING) {
1185
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2095 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2096 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2097 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2098 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2099 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2100 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2101 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2102 }
1271
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2103 for (int i = 0; i < (256+HORIZ_BORDER) - 2 * (context->hslot - BG_START_SLOT); i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2104 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2105 *(dst++) = bg_color;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2106 }
1185
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents: 1183
diff changeset
2107 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2108 context->sprite_index = 0x80;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2109 context->slot_counter = MAX_SPRITES_LINE_H32;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2110 render_sprite_cells( context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2111 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2112 CHECK_LIMIT
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2113 SPRITE_RENDER_H32(136)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2114 SPRITE_RENDER_H32(137)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2115 SPRITE_RENDER_H32(138)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2116 SPRITE_RENDER_H32(139)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2117 SPRITE_RENDER_H32(140)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2118 SPRITE_RENDER_H32(141)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2119 SPRITE_RENDER_H32(142)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2120 SPRITE_RENDER_H32(143)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2121 SPRITE_RENDER_H32(144)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2122 case 145:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2123 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2124 CHECK_LIMIT
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2125 SPRITE_RENDER_H32(146)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2126 SPRITE_RENDER_H32(147)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2127 SPRITE_RENDER_H32(233)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2128 SPRITE_RENDER_H32(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2129 SPRITE_RENDER_H32(235)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2130 //HSYNC start
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2131 SPRITE_RENDER_H32(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2132 SPRITE_RENDER_H32(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2133 SPRITE_RENDER_H32(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2134 SPRITE_RENDER_H32(239)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2135 SPRITE_RENDER_H32(240)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2136 SPRITE_RENDER_H32(241)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2137 SPRITE_RENDER_H32(242)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2138 case 243:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2139 external_slot(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2140 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2141 case 244:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2142 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2143 mask = 0;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2144 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2145 mask |= 0xF8;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2146 }
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2147 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2148 mask |= 0x7;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2149 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2150 address += (context->vcounter & mask) * 4;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2151 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2152 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2153 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2154 CHECK_LIMIT
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2155 SPRITE_RENDER_H32(245)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2156 SPRITE_RENDER_H32(246)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2157 SPRITE_RENDER_H32(247)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2158 SPRITE_RENDER_H32(248)
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2159 //!HSYNC high
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2160 case 249:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2161 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2162 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2163 SPRITE_RENDER_H32(250)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2164 case 251:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2165 render_map_1(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2166 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2167 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2168 case 252:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2169 render_map_2(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2170 scan_sprite_table(context->vcounter, context);//Just a guess
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2171 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2172 case 253:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2173 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2174 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2175 case 254:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2176 render_sprite_cells(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2177 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2178 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2179 case 255:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2180 render_map_3(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2181 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2182 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2183 case 0:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2184 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2185 scan_sprite_table(context->vcounter, context);//Just a guess
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2186 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2187 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2188 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2189 context->cur_slot = MAX_SPRITES_LINE_H32-1;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2190 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2191 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2192 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2193 COLUMN_RENDER_BLOCK(2, 1)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2194 COLUMN_RENDER_BLOCK(4, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2195 COLUMN_RENDER_BLOCK(6, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2196 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2197 COLUMN_RENDER_BLOCK(10, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2198 COLUMN_RENDER_BLOCK(12, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2199 COLUMN_RENDER_BLOCK(14, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2200 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2201 COLUMN_RENDER_BLOCK(18, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2202 COLUMN_RENDER_BLOCK(20, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2203 COLUMN_RENDER_BLOCK(22, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2204 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2205 COLUMN_RENDER_BLOCK(26, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2206 COLUMN_RENDER_BLOCK(28, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2207 COLUMN_RENDER_BLOCK(30, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2208 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2209 case 129:
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2210 external_slot(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2211 CHECK_LIMIT
1269
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2212 case 130: {
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2213 external_slot(context);
1269
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2214 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2215 for (int i = 256+BORDER_LEFT; i < 256+HORIZ_BORDER; i++)
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2216 {
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2217 context->output[i] = bg_color;
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2218 }
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2219 CHECK_LIMIT
1269
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2220 }
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2221 //sprite render to line buffer starts
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2222 case 131:
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2223 context->cur_slot = MAX_DRAWS_H32-1;
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2224 memset(context->linebuf, 0, LINEBUF_SIZE);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2225 render_sprite_cells(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2226 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2227 case 132:
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2228 render_sprite_cells(context);
1173
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2229 if (context->flags & FLAG_DMA_RUN) {
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2230 run_dma_src(context, -1);
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2231 }
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2232 context->hslot++;
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2233 context->cycles += slot_cycles;
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2234 vdp_advance_line(context);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2235 if (context->vcounter == context->inactive_start) {
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2236 return;
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2237 }
1173
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2238 CHECK_ONLY
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2239 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2240 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2241 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2242 context->cycles += MCLKS_SLOT_H32;
503
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2243 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2244 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2245
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2246 static void vdp_h32_mode4(vdp_context * context, uint32_t target_cycles)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2247 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2248 uint16_t address;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2249 uint32_t mask;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2250 uint32_t const slot_cycles = MCLKS_SLOT_H32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2251 switch(context->hslot)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2252 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2253 for (;;)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2254 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2255 //sprite rendering starts
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2256 SPRITE_RENDER_H32_MODE4(137)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2257 SPRITE_RENDER_H32_MODE4(143)
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2258 case 234:
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2259 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2260 CHECK_LIMIT
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2261 case 235:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2262 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2263 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2264 //!HSYNC low
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2265 case 236:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2266 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2267 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2268 case 237:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2269 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2270 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2271 case 238:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2272 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2273 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2274 SPRITE_RENDER_H32_MODE4(239)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2275 SPRITE_RENDER_H32_MODE4(245)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2276 case 251:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2277 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2278 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2279 case 252:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2280 external_slot(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2281 if (context->regs[REG_MODE_1] & BIT_HSCRL_LOCK && context->vcounter < 16) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2282 context->hscroll_a = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2283 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2284 context->hscroll_a = context->regs[REG_X_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2285 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2286 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2287 case 253:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2288 context->sprite_index = 0;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2289 context->slot_counter = MAX_DRAWS_H32_MODE4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2290 scan_sprite_table_mode4(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2291 CHECK_LIMIT
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2292 case 254:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2293 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2294 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2295 case 255:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2296 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2297 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2298 case 0:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2299 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2300 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2301 case 1:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2302 scan_sprite_table_mode4(context);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2303 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2304 case 2:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2305 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2306 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2307 case 3:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2308 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2309 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2310 case 4:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2311 scan_sprite_table_mode4(context);
1121
1913f9c28003 Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents: 1120
diff changeset
2312 context->buf_a_off = 8;
1913f9c28003 Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents: 1120
diff changeset
2313 memset(context->tmp_buf_a, 0, 8);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2314 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2315 COLUMN_RENDER_BLOCK_MODE4(0, 5)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2316 COLUMN_RENDER_BLOCK_MODE4(1, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2317 COLUMN_RENDER_BLOCK_MODE4(2, 13)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2318 COLUMN_RENDER_BLOCK_MODE4(3, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2319 COLUMN_RENDER_BLOCK_MODE4(4, 21)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2320 COLUMN_RENDER_BLOCK_MODE4(5, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2321 COLUMN_RENDER_BLOCK_MODE4(6, 29)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2322 COLUMN_RENDER_BLOCK_MODE4(7, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2323 COLUMN_RENDER_BLOCK_MODE4(8, 37)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2324 COLUMN_RENDER_BLOCK_MODE4(9, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2325 COLUMN_RENDER_BLOCK_MODE4(10, 45)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2326 COLUMN_RENDER_BLOCK_MODE4(11, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2327 COLUMN_RENDER_BLOCK_MODE4(12, 53)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2328 COLUMN_RENDER_BLOCK_MODE4(13, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2329 COLUMN_RENDER_BLOCK_MODE4(14, 61)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2330 COLUMN_RENDER_BLOCK_MODE4(15, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2331 COLUMN_RENDER_BLOCK_MODE4(16, 69)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2332 COLUMN_RENDER_BLOCK_MODE4(17, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2333 COLUMN_RENDER_BLOCK_MODE4(18, 77)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2334 COLUMN_RENDER_BLOCK_MODE4(19, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2335 COLUMN_RENDER_BLOCK_MODE4(20, 85)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2336 COLUMN_RENDER_BLOCK_MODE4(21, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2337 COLUMN_RENDER_BLOCK_MODE4(22, 93)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2338 COLUMN_RENDER_BLOCK_MODE4(23, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2339 COLUMN_RENDER_BLOCK_MODE4(24, 101)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2340 COLUMN_RENDER_BLOCK_MODE4(25, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2341 COLUMN_RENDER_BLOCK_MODE4(26, 109)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2342 COLUMN_RENDER_BLOCK_MODE4(27, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2343 COLUMN_RENDER_BLOCK_MODE4(28, 117)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2344 COLUMN_RENDER_BLOCK_MODE4(29, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2345 COLUMN_RENDER_BLOCK_MODE4(30, 125)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2346 COLUMN_RENDER_BLOCK_MODE4(31, 129)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2347 case 133:
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2348 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2349 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2350 case 134:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2351 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2352 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2353 case 135:
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2354 external_slot(context);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2355 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2356 case 136:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2357 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2358 //set things up for sprite rendering in the next slot
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2359 memset(context->linebuf, 0, LINEBUF_SIZE);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2360 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2361 context->sprite_draws = MAX_DRAWS_H32_MODE4;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2362 CHECK_LIMIT
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2363 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2364 default:
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2365 context->hslot++;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2366 context->cycles += MCLKS_SLOT_H32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2367 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2368 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2369
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2370 static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2371 {
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2372 uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2373 uint8_t index_reset_value, max_draws, max_sprites;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2374 uint16_t vint_line, active_line;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2375 uint32_t bg_color;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2376
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2377 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2378 if (is_h40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2379 buf_clear_slot = 161;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2380 index_reset_slot = 165;
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2381 bg_end_slot = BG_START_SLOT + LINEBUF_SIZE/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2382 max_draws = MAX_DRAWS-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2383 max_sprites = MAX_SPRITES_LINE;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2384 index_reset_value = 0x80;
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
2385 vint_slot = VINT_SLOT_H40;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2386 line_change = LINE_CHANGE_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2387 jump_start = 182;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2388 jump_dest = 229;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2389 } else {
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2390 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2391 max_draws = MAX_DRAWS_H32-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2392 max_sprites = MAX_SPRITES_LINE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2393 buf_clear_slot = 128;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2394 index_reset_slot = 132;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2395 index_reset_value = 0x80;
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
2396 vint_slot = VINT_SLOT_H32;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2397 line_change = LINE_CHANGE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2398 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2399 jump_dest = 233;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2400 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2401 vint_line = context->inactive_start;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2402 active_line = 0x1FF;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2403 } else {
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2404 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2405 max_draws = MAX_DRAWS_H32_MODE4;
1278
34d3cb05014d Fix VDP buffer overrun that was causing sprite flickering in some games
Michael Pavone <pavone@retrodev.com>
parents: 1273
diff changeset
2406 max_sprites = 8;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2407 buf_clear_slot = 136;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2408 index_reset_slot = 253;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2409 index_reset_value = 0;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2410 vint_line = context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2411 vint_slot = VINT_SLOT_MODE4;
1177
67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency
Michael Pavone <pavone@retrodev.com>
parents: 1175
diff changeset
2412 line_change = LINE_CHANGE_MODE4;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2413 bg_color = render_map_color(0, 0, 0);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2414 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2415 jump_dest = 233;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2416 if (context->regs[REG_MODE_1] & BIT_MODE_4) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2417 //FIXME: This is actually 0x1FF like in Mode 5
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2418 active_line = 0;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2419 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2420 //never active unless either mode 4 or mode 5 is turned on
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2421 active_line = 0x200;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2422 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2423 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2424 uint32_t *dst = (
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2425 context->vcounter < context->inactive_start + context->border_bot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2426 || context->vcounter > 0x200 - context->border_top
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2427 ) && context->hslot >= BG_START_SLOT && context->hslot < bg_end_slot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2428 ? context->output + 2 * (context->hslot - BG_START_SLOT)
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2429 : NULL;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2430
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2431 while(context->cycles < target_cycles)
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2432 {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2433 if (context->hslot == BG_START_SLOT && (
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2434 context->vcounter < context->inactive_start + context->border_bot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2435 || context->vcounter > 0x200 - context->border_top
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2436 )) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2437 dst = context->output + (context->hslot - BG_START_SLOT) * 2;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2438 } else if (context->hslot == bg_end_slot) {
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2439 advance_output_line(context);
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2440 dst = NULL;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2441 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2442
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2443 if (context->hslot == buf_clear_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2444 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2445 context->cur_slot = max_draws;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2446 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2447 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2448 context->sprite_draws = MAX_DRAWS_H32_MODE4;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2449 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2450 memset(context->linebuf, 0, LINEBUF_SIZE);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2451 } else if (context->hslot == index_reset_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2452 context->sprite_index = index_reset_value;
1278
34d3cb05014d Fix VDP buffer overrun that was causing sprite flickering in some games
Michael Pavone <pavone@retrodev.com>
parents: 1273
diff changeset
2453 context->slot_counter = max_sprites;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2454 } else if (context->vcounter == vint_line && context->hslot == vint_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2455 context->flags2 |= FLAG2_VINT_PENDING;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2456 context->pending_vint_start = context->cycles;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2457 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2458
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2459 if (dst) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2460 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2461 bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2462 } else if (context->regs[REG_MODE_1] & BIT_MODE_4) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2463 bg_color = context->colors[CRAM_SIZE * 3 + 0x10 + (context->regs[REG_BG_COLOR] & 0xF)];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2464 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2465 *(dst++) = bg_color;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2466 *(dst++) = bg_color;
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2467 if (context->hslot == (bg_end_slot-1)) {
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2468 *(dst++) = bg_color;
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
2469 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2470 }
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
2471
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
2472 if (!is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
2473 external_slot(context);
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
2474 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
2475 run_dma_src(context, context->hslot);
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
2476 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
2477 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
2478
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2479 if (is_h40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2480 if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2481 context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2482 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2483 context->cycles += MCLKS_SLOT_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2484 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2485 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2486 context->cycles += MCLKS_SLOT_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2487 }
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2488 if (context->hslot == jump_start) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2489 context->hslot = jump_dest;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2490 } else {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2491 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2492 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2493 if (context->hslot == line_change) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2494 vdp_advance_line(context);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2495 if (context->vcounter == active_line) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2496 context->state = PREPARING;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2497 return;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2498 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2499 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2500 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2501 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2502
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2503 void vdp_run_context(vdp_context * context, uint32_t target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2504 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2505 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2506 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2507 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2508 {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2509 if (context->state == ACTIVE && context->vcounter == context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2510 context->state = INACTIVE;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2511 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2512
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2513 if (is_active(context)) {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2514 if (mode_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2515 if (is_h40) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2516 vdp_h40(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2517 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2518 vdp_h32(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2519 }
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
2520 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2521 vdp_h32_mode4(context, target_cycles);
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
2522 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
2523 } else {
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
2524 vdp_inactive(context, target_cycles, is_h40, mode_5);
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2525 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2526 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2527 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2528
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2529 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2530 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2531 uint32_t old_frame = context->frame;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2532 while (context->frame == old_frame) {
1179
1271b240b9c2 Fix vdp_run_to_vblank
Michael Pavone <pavone@retrodev.com>
parents: 1178
diff changeset
2533 vdp_run_context(context, context->cycles + MCLKS_LINE);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2534 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2535 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2536 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2537
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2538 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2539 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2540 for(;;) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2541 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2542 if (!dmalen) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2543 dmalen = 0x10000;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2544 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2545 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20);
1321
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
2546 if (
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
2547 (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
2548 || (((context->cd & 0xF) == VRAM_WRITE) && !(context->regs[REG_MODE_2] & BIT_128K_VRAM))) {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2549 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2550 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
1321
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
2551 //unless 128KB mode is enabled
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2552 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2553 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2554 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2555 if (target_cycles < min_dma_complete) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2556 vdp_run_context(context, target_cycles);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2557 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2558 } else {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2559 vdp_run_context(context, min_dma_complete);
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2560 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2561 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2562 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2563 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2564 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2565 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2566
1154
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2567 static uint16_t get_ext_vcounter(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2568 {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2569 uint16_t line= context->vcounter & 0xFF;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2570 if (context->double_res) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2571 line <<= 1;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2572 if (line & 0x100) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2573 line |= 1;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2574 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2575 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2576 return line << 8;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2577 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2578
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2579 void vdp_latch_hv(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2580 {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2581 context->hv_latch = context->hslot | get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2582 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2583
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2584 uint16_t vdp_hv_counter_read(vdp_context * context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2585 {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2586 if ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_1] & BIT_HVC_LATCH)) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2587 return context->hv_latch;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2588 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2589 uint16_t hv;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2590 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2591 hv = context->hslot;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2592 } else {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2593 hv = context->hv_latch & 0xFF;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2594 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2595 hv |= get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2596
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2597 return hv;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2598 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2599
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2600 int vdp_control_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2601 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2602 //printf("control port write: %X at %d\n", value, context->cycles);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
2603 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
2604 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
2605 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2606 if (context->flags & FLAG_PENDING) {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
2607 context->address = (context->address & 0x3FFF) | (value << 14 & 0x1C000);
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
2608 //It seems like the DMA enable bit doesn't so much enable DMA so much
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
2609 //as it enables changing CD5 from control port writes
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
2610 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
2611 context->cd = (context->cd & preserve) | ((value >> 2) & ~preserve & 0xFF);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2612 context->flags &= ~FLAG_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2613 //Should these be taken care of here or after the first write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2614 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2615 context->flags2 &= ~FLAG2_READ_PENDING;
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
2616 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
2617 if (context->cd & 0x20) {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
2618 //
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2619 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2620 //DMA copy or 68K -> VDP, transfer starts immediately
131
8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents: 109
diff changeset
2621 context->dma_cd = context->cd;
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2622 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot);
1191
8dc50e50ced6 Remove accidentally committed debug logging
Michael Pavone <pavone@retrodev.com>
parents: 1189
diff changeset
2623 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
8dc50e50ced6 Remove accidentally committed debug logging
Michael Pavone <pavone@retrodev.com>
parents: 1189
diff changeset
2624 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]);
1289
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
2625 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
2626 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
2627 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
2628 //sticking with 3 slots for now until I can do some more captures
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
2629 vdp_run_context(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5));
1285
76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation
Michael Pavone <pavone@retrodev.com>
parents: 1278
diff changeset
2630 context->flags |= FLAG_DMA_RUN;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2631 return 1;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
2632 } else {
1285
76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation
Michael Pavone <pavone@retrodev.com>
parents: 1278
diff changeset
2633 context->flags |= FLAG_DMA_RUN;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
2634 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2635 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
2636 } else {
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
2637 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2638 }
63
a6dd5b7a971b Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents: 58
diff changeset
2639 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2640 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2641 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
2642 context->address = (context->address &0xC000) | (value & 0x3FFF);
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2643 context->cd = (context->cd & 0x3C) | (value >> 14);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2644 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2645 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2646 uint8_t reg = (value >> 8) & 0x1F;
1123
d5412f76accc Fix inactive start line for Mode 4 in vdp_next_hint. Fix an off by one error in the range of registers allowed to be written in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1122
diff changeset
2647 if (reg < (mode_5 ? VDP_REGS : 0xB)) {
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
2648 //printf("register %d set to %X\n", reg, value & 0xFF);
480
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
2649 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) {
1154
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
2650 vdp_latch_hv(context);
480
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
2651 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
2652 if (reg == REG_BG_COLOR) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
2653 value &= 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
2654 }
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
2655 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2656 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame);
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
2657 }*/
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2658 context->regs[reg] = value;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
2659 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
2660 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES);
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
2661 if (!context->double_res) {
1106
cacbd3f18f03 Fix field flag handling bug introduced with VDP/render interface cleanup
Michael Pavone <pavone@retrodev.com>
parents: 1103
diff changeset
2662 context->flags2 &= ~FLAG2_EVEN_FIELD;
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
2663 }
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
2664 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2665 if (reg == REG_MODE_2) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2666 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2667 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2668 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2669 } else if (mode_5) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2670 context->flags |= FLAG_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2671 //Should these be taken care of here or after the second write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2672 //context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2673 //context->flags2 &= ~FLAG2_READ_PENDING;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2674 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2675 context->flags &= ~FLAG_READ_FETCHED;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2676 context->flags2 &= ~FLAG2_READ_PENDING;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2677 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2678 }
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2679 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2680 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2681
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2682 void vdp_control_port_write_pbc(vdp_context *context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2683 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2684 if (context->flags2 & FLAG2_BYTE_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2685 uint16_t full_val = value << 8 | context->pending_byte;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2686 context->flags2 &= ~FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2687 //TODO: Deal with fact that Vbus->VDP DMA doesn't do anything in PBC mode
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2688 vdp_control_port_write(context, full_val);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
2689 if (context->cd == VRAM_READ) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
2690 context->cd = VRAM_READ8;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
2691 }
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2692 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2693 context->pending_byte = value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2694 context->flags2 |= FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2695 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2696 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2697
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
2698 int vdp_data_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2699 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2700 //printf("data port write: %X at %d\n", value, context->cycles);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
2701 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
2702 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
2703 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2704 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2705 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2706 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2707 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2708 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2709 }
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
2710 /*if (context->fifo_cur == context->fifo_end) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2711 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
2712 }*/
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
2713 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
2714 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
2715 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2716 while (context->fifo_write == context->fifo_read) {
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2717 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2718 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2719 fifo_entry * cur = context->fifo + context->fifo_write;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2720 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2721 cur->address = context->address;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2722 cur->value = value;
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2723 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2724 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2725 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2726 cur->cd = (context->cd & 2) | 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2727 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2728 cur->partial = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2729 if (context->fifo_read < 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2730 context->fifo_read = context->fifo_write;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2731 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2732 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
2733 increment_address(context);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
2734 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2735 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2736
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2737 void vdp_data_port_write_pbc(vdp_context * context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2738 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2739 if (context->flags & FLAG_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2740 context->flags &= ~FLAG_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2741 //Should these be cleared here?
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2742 context->flags &= ~FLAG_READ_FETCHED;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2743 context->flags2 &= ~FLAG2_READ_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2744 }
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2745 context->flags2 &= ~FLAG2_BYTE_PENDING;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2746 /*if (context->fifo_cur == context->fifo_end) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2747 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2748 }*/
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2749 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2750 context->flags &= ~FLAG_DMA_RUN;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2751 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2752 while (context->fifo_write == context->fifo_read) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2753 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2754 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2755 fifo_entry * cur = context->fifo + context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2756 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2757 cur->address = context->address;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2758 cur->value = value;
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2759 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2760 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2761 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2762 cur->cd = (context->cd & 2) | 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2763 }
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
2764 cur->partial = 3;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2765 if (context->fifo_read < 0) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2766 context->fifo_read = context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2767 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2768 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
2769 increment_address(context);
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2770 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2771
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2772 void vdp_test_port_write(vdp_context * context, uint16_t value)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2773 {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
2774 context->test_port = value;
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2775 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2776
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2777 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2778 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2779 context->flags &= ~FLAG_PENDING;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
2780 context->flags2 &= ~FLAG2_BYTE_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2781 //Bits 15-10 are not fixed like Charles MacDonald's doc suggests, but instead open bus values that reflect 68K prefetch
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
2782 uint16_t value = context->system->get_open_bus_value(context->system) & 0xFC00;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2783 if (context->fifo_read < 0) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2784 value |= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2785 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2786 if (context->fifo_read == context->fifo_write) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2787 value |= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2788 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2789 if (context->flags2 & FLAG2_VINT_PENDING) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
2790 value |= 0x80;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
2791 }
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
2792 if (context->flags & FLAG_DOT_OFLOW) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
2793 value |= 0x40;
1156
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
2794 context->flags &= ~FLAG_DOT_OFLOW;
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
2795 }
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
2796 if (context->flags2 & FLAG2_SPRITE_COLLIDE) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
2797 value |= 0x20;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
2798 context->flags2 &= ~FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
2799 }
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
2800 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && !(context->flags2 & FLAG2_EVEN_FIELD)) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
2801 value |= 0x10;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2802 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2803 uint32_t slot = context->hslot;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2804 if (!is_active(context)) {
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
2805 value |= 0x8;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
2806 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2807 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2808 if (slot < HBLANK_END_H40 || slot > HBLANK_START_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2809 value |= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2810 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2811 } else {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2812 if (slot < HBLANK_END_H32 || slot > HBLANK_START_H32) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2813 value |= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2814 }
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
2815 }
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
2816 if (context->cd & 0x20) {
141
576f55711d8d Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents: 138
diff changeset
2817 value |= 0x2;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
2818 }
714
e29bc2918f69 Fix VDP status register PAL bit based on observations of the Titan Overdrive demo
Michael Pavone <pavone@retrodev.com>
parents: 711
diff changeset
2819 if (context->flags2 & FLAG2_REGION_PAL) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2820 value |= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2821 }
459
c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
2822 //printf("status read at cycle %d returned %X\n", context->cycles, value);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2823 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2824 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2825
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2826 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2827 {
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2828 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2829 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2830 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2831 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2832 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2833 }
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
2834 if (context->cd & 1) {
991
f9ee6f746cb4 Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents: 984
diff changeset
2835 warning("Read from VDP data port while writes are configured, CPU is now frozen. VDP Address: %X, CD: %X\n", context->address, context->cd);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2836 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2837 while (!(context->flags & FLAG_READ_FETCHED)) {
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
2838 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2839 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2840 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
2841 return context->prefetch;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2842 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
2843
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
2844 uint8_t vdp_data_port_read_pbc(vdp_context * context)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
2845 {
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2846 context->flags &= ~(FLAG_PENDING | FLAG_READ_FETCHED);
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
2847 context->flags2 &= ~FLAG2_BYTE_PENDING;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
2848
1152
ddbb61be6119 Fix to pass a couple more tests in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1151
diff changeset
2849 context->cd = VRAM_READ8;
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
2850 return context->prefetch;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
2851 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
2852
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2853 uint16_t vdp_test_port_read(vdp_context * context)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2854 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2855 //TODO: Find out what actually gets returned here
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
2856 return context->test_port;
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2857 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2858
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
2859 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
2860 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
2861 context->cycles -= deduction;
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2862 if (context->pending_vint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2863 context->pending_vint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2864 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2865 context->pending_vint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2866 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2867 if (context->pending_hint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2868 context->pending_hint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2869 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2870 context->pending_hint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2871 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2872 if (context->fifo_read >= 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2873 int32_t idx = context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2874 do {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2875 if (context->fifo[idx].cycle >= deduction) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2876 context->fifo[idx].cycle -= deduction;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2877 } else {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2878 context->fifo[idx].cycle = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2879 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2880 idx = (idx+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
2881 } while(idx != context->fifo_write);
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
2882 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
2883 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
2884
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
2885 static uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context)
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2886 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2887 if (context->hslot < 183) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2888 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2889 } else if (context->hslot < HSYNC_END_H40) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2890 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2891 uint32_t hsync = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2892 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2893 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2894 hsync += h40_hsync_cycles[i];
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2895 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2896 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2897 return before_hsync + hsync + after_hsync;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2898 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2899 return (256-context->hslot) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2900 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2901 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2902
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
2903 static uint32_t vdp_cycles_next_line(vdp_context * context)
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2904 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2905 if (context->regs[REG_MODE_4] & BIT_H40) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2906 //TODO: Handle "illegal" Mode 4/H40 combo
647
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
2907 if (context->hslot < LINE_CHANGE_H40) {
697
7f96bd1cb1be Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents: 680
diff changeset
2908 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2909 } else {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2910 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2911 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2912 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2913 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2914 if (context->hslot < LINE_CHANGE_H32) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2915 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2916 } else if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2917 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2918 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2919 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2920 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2921 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2922 if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2923 return (148 - context->hslot + LINE_CHANGE_MODE4 - 233) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2924 } else if (context->hslot < LINE_CHANGE_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2925 return (LINE_CHANGE_MODE4 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2926 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2927 return MCLKS_LINE - (context->hslot - LINE_CHANGE_MODE4) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2928 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2929 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2930 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2931 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2932
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2933 static void get_jump_params(vdp_context *context, uint32_t *jump_start, uint32_t *jump_dst)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2934 {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2935 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2936 if (context->flags2 & FLAG2_REGION_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2937 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2938 *jump_start = 0x10B;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2939 *jump_dst = 0x1D2;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2940 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2941 *jump_start = 0x103;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2942 *jump_dst = 0x1CA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2943 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2944 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2945 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2946 *jump_start = 0x100;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2947 *jump_dst = 0x1FA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2948 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2949 *jump_start = 0xEB;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2950 *jump_dst = 0x1E5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2951 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2952 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2953 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2954 *jump_start = 0xDB;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2955 *jump_dst = 0x1D5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2956 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2957 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2958
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
2959 static uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target)
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2960 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2961 uint32_t jump_start, jump_dst;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2962 get_jump_params(context, &jump_start, &jump_dst);
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2963 uint32_t lines;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2964 if (context->vcounter < target) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2965 if (target < jump_start || context->vcounter > jump_start) {
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2966 lines = target - context->vcounter;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2967 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2968 lines = jump_start - context->vcounter + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2969 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2970 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2971 if (context->vcounter < jump_start) {
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
2972 lines = jump_start - context->vcounter + 512 - jump_dst;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2973 } else {
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
2974 lines = 512 - context->vcounter;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2975 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2976 if (target < jump_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2977 lines += target;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2978 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2979 lines += jump_start + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2980 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2981 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2982 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context);
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2983 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2984
680
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
2985 uint32_t vdp_cycles_to_frame_end(vdp_context * context)
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
2986 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2987 return context->cycles + vdp_cycles_to_line(context, context->inactive_start);
680
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
2988 }
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
2989
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2990 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2991 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
2992 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2993 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2994 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2995 if (context->flags2 & FLAG2_HINT_PENDING) {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
2996 return context->pending_hint_start;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
2997 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
2998 uint32_t hint_line;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2999 if (context->state != ACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3000 hint_line = context->regs[REG_HINT];
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3001 if (hint_line > context->inactive_start) {
724
2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents: 722
diff changeset
3002 return 0xFFFFFFFF;
2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents: 722
diff changeset
3003 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3004 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3005 hint_line = context->vcounter + context->hint_counter + 1;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3006 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3007 if (hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3008 hint_line = context->regs[REG_HINT];
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3009 if (hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3010 return 0xFFFFFFFF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3011 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3012 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3013 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3014 uint32_t jump_start, jump_dst;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3015 get_jump_params(context, &jump_start, &jump_dst);
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3016 if (hint_line >= jump_start && context->vcounter < jump_dst) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3017 hint_line = (hint_line + jump_dst - jump_start) & 0x1FF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3018 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3019 if (hint_line < context->vcounter && hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3020 return 0xFFFFFFFF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3021 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3022 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3023 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3024 return context->cycles + vdp_cycles_to_line(context, hint_line);
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3025 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3026
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3027 static uint32_t vdp_next_vint_real(vdp_context * context)
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3028 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3029 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3030 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3031 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3032 if (context->flags2 & FLAG2_VINT_PENDING) {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3033 return context->pending_vint_start;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3034 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3035
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3036
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3037 return vdp_next_vint_z80(context);
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3038 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3039
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3040 uint32_t vdp_next_vint(vdp_context *context)
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3041 {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3042 uint32_t ret = vdp_next_vint_real(context);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3043 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3044 static uint32_t last = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3045 if (last != ret) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3046 printf("vdp_next_vint is %d at frame %d, line %d, hslot %d\n", ret, context->frame, context->vcounter, context->hslot);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3047 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3048 last = ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3049 #endif
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3050 return ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3051 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3052
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3053 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3054 {
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3055 uint16_t vint_line = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->inactive_start : context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3056 if (context->vcounter == vint_line) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3057 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3058 if (context->regs[REG_MODE_4] & BIT_H40) {
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3059 if (context->hslot >= LINE_CHANGE_H40 || context->hslot <= VINT_SLOT_H40) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3060 uint32_t cycles = context->cycles;
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3061 if (context->hslot >= LINE_CHANGE_H40) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3062 if (context->hslot < 183) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3063 cycles += (183 - context->hslot) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3064 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3065
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3066 if (context->hslot < HSYNC_SLOT_H40) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3067 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3068 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3069 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ )
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3070 {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3071 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3072 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3073 cycles += (256 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3074 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3075
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3076 cycles += (VINT_SLOT_H40 - (context->hslot >= LINE_CHANGE_H40 ? 0 : context->hslot)) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3077 return cycles;
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
3078 }
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3079 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3080 if (context->hslot >= LINE_CHANGE_H32 || context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3081 if (context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3082 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32;
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3083 } else if (context->hslot < 233) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3084 return context->cycles + (VINT_SLOT_H32 + 256 - 233 + 148 - context->hslot) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3085 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3086 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3087 }
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
3088 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3089 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3090 } else {
1177
67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency
Michael Pavone <pavone@retrodev.com>
parents: 1175
diff changeset
3091 if (context->hslot >= LINE_CHANGE_MODE4) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3092 return context->cycles + (VINT_SLOT_MODE4 + 256 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3093 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3094 if (context->hslot <= VINT_SLOT_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3095 return context->cycles + (VINT_SLOT_MODE4 - context->hslot) * MCLKS_SLOT_H32;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3096 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3097 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3098 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3099 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3100 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3101 if (context->regs[REG_MODE_4] & BIT_H40) {
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3102 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3103 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3104 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3105 }
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3106 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3107 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32;
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3108 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3109 return context->cycles + cycles_to_vint;
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3110 }
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3111
953
08346262990b Remove the int number argument to vdp_int_ack since it is no longer used
Michael Pavone <pavone@retrodev.com>
parents: 952
diff changeset
3112 void vdp_int_ack(vdp_context * context)
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3113 {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3114 //CPU interrupt acknowledge is only used in Mode 5
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3115 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3116 //Apparently the VDP interrupt controller is not very smart
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3117 //Instead of paying attention to what interrupt is being acknowledged it just
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3118 //clears the pending flag for whatever interrupt it is currently asserted
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3119 //which may be different from the interrupt it was asserting when the 68k
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3120 //started the interrupt process. The window for this is narrow and depends
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3121 //on the latency between the int enable register write and the interrupt being
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3122 //asserted, but Fatal Rewind depends on this due to some buggy code
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3123 if ((context->flags2 & FLAG2_VINT_PENDING) && (context->regs[REG_MODE_2] & BIT_VINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3124 context->flags2 &= ~FLAG2_VINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3125 } else if((context->flags2 & FLAG2_HINT_PENDING) && (context->regs[REG_MODE_1] & BIT_HINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3126 context->flags2 &= ~FLAG2_HINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3127 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3128 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3129 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3130