repos/blastem: vdp.c annotate

annotate vdp.c @ 1336:baaf05fd64c4

Make internal screenshot functionality completely ignore overscan settings rather than only doing it for the height

author	Michael Pavone <pavone@retrodev.com>
date	Sat, 29 Apr 2017 12:32:50 -0700
parents	26e72126f9d1
children	d092c15246a3

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	2 Copyright 2013 Michael Pavone
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 462 diff changeset	5 */
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include "vdp.h"
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	7 #include "blastem.h"
1103 22e87b739ad6 WIP split of ROM loading/argument parsing from Genesis emulation code. Compiles and doesn't crash, but nothing works. Still a few too many globals as well. Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	8 #include "genesis.h"
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #include <stdlib.h>
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 #include <string.h>
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	11 #include "render.h"
991 f9ee6f746cb4 Properly emulate machine freeze when reading from VDP while configured for writes Michael Pavone <pavone@retrodev.com> parents: 984 diff changeset	12 #include "util.h"
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	13
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	14 #define NTSC_INACTIVE_START 224
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	15 #define PAL_INACTIVE_START 240
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	16 #define MODE4_INACTIVE_START 192
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define BUF_BIT_PRIORITY 0x40
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define MAP_BIT_PRIORITY 0x8000
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define MAP_BIT_H_FLIP 0x800
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define MAP_BIT_V_FLIP 0x1000
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	21
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	22 #define SCROLL_BUFFER_SIZE 32
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	23 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	24 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	25
328 bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	26 #define MCLKS_SLOT_H40 16
bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	27 #define MCLKS_SLOT_H32 20
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	28 #define VINT_SLOT_H40 0 //21 slots before HSYNC, 16 during, 10 after
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	29 #define VINT_SLOT_H32 0 //old value was 23, but recent tests suggest the actual value is close to the H40 one
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	30 #define VINT_SLOT_MODE4 4
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	31 #define HSYNC_SLOT_H40 230
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	32 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17)
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	33 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	34 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	35 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	36 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	37 #define LINE_CHANGE_H40 165
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	38 #define LINE_CHANGE_H32 133
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	39 #define LINE_CHANGE_MODE4 249
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	40 #define VBLANK_START_H40 (LINE_CHANGE_H40+2)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	41 #define VBLANK_START_H32 (LINE_CHANGE_H32+2)
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	42 #define FIFO_LATENCY 3
328 bf7ed23efa40 Fewer magic numbers in the VDP core for the win Mike Pavone <pavone@retrodev.com> parents: 327 diff changeset	43
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	44 #define BORDER_TOP_V24 27
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	45 #define BORDER_TOP_V28 11
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	46 #define BORDER_TOP_V24_PAL 54
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	47 #define BORDER_TOP_V28_PAL 38
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	48 #define BORDER_TOP_V30_PAL 30
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	49
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	50 #define BORDER_BOT_V24 24
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	51 #define BORDER_BOT_V28 8
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	52 #define BORDER_BOT_V24_PAL 48
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	53 #define BORDER_BOT_V28_PAL 32
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	54 #define BORDER_BOT_V30_PAL 24
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	55
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	56 #define INVALID_LINE 0x200
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	57
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	58 enum {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	59 INACTIVE = 0,
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	60 PREPARING, //used for line 0x1FF
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	61 ACTIVE
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	62 };
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	63
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	64 static int32_t color_map[1 << 12];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	65 static uint16_t mode4_address_map[0x4000];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	66 static uint32_t planar_to_chunky[256];
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	67 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	68
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	69 static uint8_t debug_base[][3] = {
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	70 {127, 127, 127}, //BG
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	71 {0, 0, 127}, //A
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	72 {127, 0, 0}, //Window
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	73 {0, 127, 0}, //B
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	74 {127, 0, 127} //Sprites
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	75 };
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	76
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	77 static void update_video_params(vdp_context *context)
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	78 {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	79 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	80 if (context->regs[REG_MODE_2] & BIT_PAL) {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	81 if (context->flags2 & FLAG2_REGION_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	82 context->inactive_start = PAL_INACTIVE_START;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	83 context->border_top = BORDER_TOP_V30_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	84 context->border_bot = BORDER_BOT_V30_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	85 } else {
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	86 //the behavior here is rather weird and needs more investigation
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	87 context->inactive_start = 0xF0;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	88 context->border_top = 1;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	89 context->border_bot = 3;
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	90 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	91 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	92 context->inactive_start = NTSC_INACTIVE_START;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	93 if (context->flags2 & FLAG2_REGION_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	94 context->border_top = BORDER_TOP_V28_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	95 context->border_bot = BORDER_BOT_V28_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	96 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	97 context->border_top = BORDER_TOP_V28;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	98 context->border_bot = BORDER_TOP_V28;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	99 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	100 }
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	101 if (context->regs[REG_MODE_4] & BIT_H40) {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	102 context->max_sprites_frame = MAX_SPRITES_FRAME;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	103 context->max_sprites_line = MAX_SPRITES_LINE;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	104 } else {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	105 context->max_sprites_frame = MAX_SPRITES_FRAME_H32;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	106 context->max_sprites_line = MAX_SPRITES_LINE_H32;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	107 }
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	108 if (context->state == INACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	109 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	110 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	111 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	112 } else if (context->vcounter == 0x1FF) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	113 context->state = PREPARING;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	114 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	115 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	116 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	117 context->inactive_start = MODE4_INACTIVE_START;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	118 if (context->flags2 & FLAG2_REGION_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	119 context->border_top = BORDER_TOP_V24_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	120 context->border_bot = BORDER_BOT_V24_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	121 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	122 context->border_top = BORDER_TOP_V24;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	123 context->border_bot = BORDER_BOT_V24;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	124 }
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	125 if (!(context->regs[REG_MODE_1] & BIT_MODE_4)){
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	126 context->state = INACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	127 } else if (context->state == INACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	128 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	129 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	130 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	131 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	132 /*
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	133 FIXME: uncomment this once mode 4 renderer is updated to handle this
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	134 else if (context->vcounter == 0x1FF) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	135 context->state = PREPARING;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	136 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	137 */
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	138 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	139 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	140 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	141
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	142 static uint8_t color_map_init_done;
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	143
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	144 void init_vdp_context(vdp_context * context, uint8_t region_pal)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	145 {
58 a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs. Mike Pavone <pavone@retrodev.com> parents: 56 diff changeset	146 memset(context, 0, sizeof(*context));
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 context->vdpmem = malloc(VRAM_SIZE);
58 a6a19c45d358 Properly zero-init all VDP buffers. Comment out some debug printfs. Mike Pavone <pavone@retrodev.com> parents: 56 diff changeset	148 memset(context->vdpmem, 0, VRAM_SIZE);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	149 /*
488 32f053ad9b02 Basic OpenGL rendering is working Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	150 */
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	151 if (headless) {
1168 fa73a77ddf92 Fix benchmark mode Michael Pavone <pavone@retrodev.com> parents: 1167 diff changeset	152 context->output = malloc(LINEBUF_SIZE * sizeof(uint32_t));
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	153 context->output_pitch = 0;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	154 } else {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	155 context->fb = render_get_framebuffer(FRAMEBUFFER_ODD, &context->output_pitch);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	156 }
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	157 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	158 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE;
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	160 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE;
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	161 context->sprite_draws = MAX_DRAWS;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	162 context->fifo_write = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	163 context->fifo_read = -1;
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	164 context->regs[REG_HINT] = context->hint_counter = 0xFF;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	165
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	166 if (!color_map_init_done) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	167 uint8_t b,g,r;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	168 for (uint16_t color = 0; color < (1 << 12); color++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	169 if (color & FBUF_SHADOW) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	170 b = levels[(color >> 9) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	171 g = levels[(color >> 5) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	172 r = levels[(color >> 1) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	173 } else if(color & FBUF_HILIGHT) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	174 b = levels[((color >> 9) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	175 g = levels[((color >> 5) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	176 r = levels[((color >> 1) & 0x7) + 7];
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	177 } else if(color & FBUF_MODE4) {
1127 cb4771f4543a Fix Mode 4 color mapping Michael Pavone <pavone@retrodev.com> parents: 1125 diff changeset	178 b = levels[(color >> 4 & 0xC) \| (color >> 6 & 0x2)];
1125 fba485949723 Brighten up Mode 4 colors Michael Pavone <pavone@retrodev.com> parents: 1124 diff changeset	179 g = levels[(color >> 2 & 0x8) \| (color >> 1 & 0x4) \| (color >> 4 & 0x2)];
fba485949723 Brighten up Mode 4 colors Michael Pavone <pavone@retrodev.com> parents: 1124 diff changeset	180 r = levels[(color << 1 & 0xC) \| (color >> 1 & 0x2)];
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	181 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	182 b = levels[(color >> 8) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	183 g = levels[(color >> 4) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	184 r = levels[color & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	185 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	186 color_map[color] = render_map_color(r, g, b);
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	187 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	188 for (uint16_t mode4_addr = 0; mode4_addr < 0x4000; mode4_addr++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	189 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	190 uint16_t mode5_addr = mode4_addr & 0x3DFD;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	191 mode5_addr \|= mode4_addr << 8 & 0x200;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	192 mode5_addr \|= mode4_addr >> 8 & 2;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	193 mode4_address_map[mode4_addr] = mode5_addr;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	194 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	195 for (uint32_t planar = 0; planar < 256; planar++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	196 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	197 uint32_t chunky = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	198 for (int bit = 7; bit >= 0; bit--)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	199 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	200 chunky = chunky << 4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	201 chunky \|= planar >> bit & 1;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	202 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	203 planar_to_chunky[planar] = chunky;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	204 }
426 add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	205 color_map_init_done = 1;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	206 }
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	207 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++)
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	208 {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	209 uint8_t src = color & DBG_SRC_MASK;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	210 if (src > DBG_SRC_S) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	211 context->debugcolors[color] = 0;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	212 } else {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	213 uint8_t r,g,b;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	214 b = debug_base[src][0];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	215 g = debug_base[src][1];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	216 r = debug_base[src][2];
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	217 if (color & DBG_PRIORITY)
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	218 {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	219 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	220 b += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	221 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	222 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	223 g += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	224 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	225 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	226 r += 48;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	227 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	228 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	229 if (color & DBG_SHADOW) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	230 b /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	231 g /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	232 r /=2 ;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	233 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	234 if (color & DBG_HILIGHT) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	235 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	236 b += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	237 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	238 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	239 g += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	240 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	241 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	242 r += 72;
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	243 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	244 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	245 context->debugcolors[color] = render_map_color(r, g, b);
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	246 }
afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	247 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	248 if (region_pal) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	249 context->flags2 \|= FLAG2_REGION_PAL;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	250 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	251 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	252 if (!headless) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	253 context->output = (uint32_t )(((char )context->fb) + context->output_pitch * context->border_top);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	254 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	255 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	256
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	257 void vdp_free(vdp_context *context)
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	258 {
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	259 free(context->vdpmem);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	260 free(context->linebuf);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	261 free(context);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	262 }
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	263
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	264 static int is_refresh(vdp_context * context, uint32_t slot)
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	265 {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	266 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	267 return slot == 250 \|\| slot == 26 \|\| slot == 59 \|\| slot == 90 \|\| slot == 122 \|\| slot == 154;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	268 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	269 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	270 //These numbers are guesses based on H40 numbers
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	271 return slot == 243 \|\| slot == 19 \|\| slot == 51 \|\| slot == 83 \|\| slot == 115;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	272 //The numbers below are the refresh slots during active display
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	273 //return (slot == 29 \|\| slot == 61 \|\| slot == 93 \|\| slot == 125);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	274 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	275 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	276
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	277 static void increment_address(vdp_context *context)
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	278 {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	279 context->address += context->regs[REG_AUTOINC];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	280 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	281 context->address++;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	282 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	283 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	284
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	285 static void render_sprite_cells(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 {
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	287 if (context->cur_slot >= context->sprite_draws) {
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	288 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	289
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	294 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 }
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	299 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	300 context->cur_slot--;
143 e5487ef04619 Fix infinite loop bug in sprite rendering Mike Pavone <pavone@retrodev.com> parents: 142 diff changeset	301 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
1029 4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	302 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	303 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	304 context->linebuf[x] = (context->vdpmem[address] >> 4) \| d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	305 } else if (context->vdpmem[address] >> 4) {
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	306 context->flags2 \|= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	307 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	309 x += dir;
1029 4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	310 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	311 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	312 context->linebuf[x] = (context->vdpmem[address] & 0xF) \| d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense. Michael Pavone <pavone@retrodev.com> parents: 1019 diff changeset	313 } else if (context->vdpmem[address] & 0xF) {
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	314 context->flags2 \|= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	315 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	318 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	319 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	320 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	321
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	322 static void fetch_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	323 {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	324 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	325 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	326 uint32_t address = mode4_address_map[d->address & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	327 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	328 context->fetch_tmp[1] = context->vdpmem[address + 1];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	329 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	330 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	331
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	332 static void render_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	333 {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	334 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	335 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	336 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	337 pixels \|= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	338 uint32_t address = mode4_address_map[(d->address + 2) & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	339 pixels \|= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	340 pixels \|= planar_to_chunky[context->vdpmem[address + 1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	341 int x = d->x_pos & 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	342 for (int i = 28; i >= 0; i -= 4, x++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	343 {
1155 da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	344 if (context->linebuf[x] && (pixels >> i & 0xF)) {
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	345 if (
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	346 ((context->regs[REG_MODE_1] & BIT_SPRITE_8PX) && x > 8)
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	347 \|\| ((!(context->regs[REG_MODE_1] & BIT_SPRITE_8PX)) && x < 256)
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	348 ) {
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	349 context->flags2 \|= FLAG2_SPRITE_COLLIDE;
da6a1f156f24 Fix Mode 4 sprite collision flag Michael Pavone <pavone@retrodev.com> parents: 1154 diff changeset	350 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	351 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	352 context->linebuf[x] = pixels >> i & 0xF;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	353 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	354 }
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	355 context->sprite_index--;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	356 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	357 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	358
1320 df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	359 static uint32_t mode5_sat_address(vdp_context *context)
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	360 {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	361 uint32_t addr = context->regs[REG_SAT] << 9;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	362 if (!(context->regs[REG_MODE_2] & BIT_128K_VRAM)) {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	363 addr &= 0xFFFF;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	364 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	365 if (context->regs[REG_MODE_4] & BIT_H40) {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	366 addr &= 0x1FC00;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	367 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	368 return addr;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	369 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	370
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	371 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	372 {
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	373 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1320 df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	374 uint16_t sat_address = mode5_sat_address(context);
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	375 uint16_t current_index = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	376 uint8_t count = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	377 do {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	378 uint16_t address = current_index * 8 + sat_address;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	379 uint16_t cache_address = current_index * 4;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	380 uint8_t height = ((context->sat_cache[cache_address+2] & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	381 uint8_t width = (((context->sat_cache[cache_address+2] >> 2) & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	382 int16_t y = ((context->sat_cache[cache_address] & 0x3) << 8 \| context->sat_cache[cache_address+1]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	383 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 \| context->vdpmem[address + 7]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	384 uint16_t link = context->sat_cache[cache_address+3] & 0x7F;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	385 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	386 uint8_t pri = context->vdpmem[address + 4] >> 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	387 uint16_t pattern = ((context->vdpmem[address + 4] << 8 \| context->vdpmem[address + 5]) & 0x7FF) << 5;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	388 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	389 current_index = link;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	390 count++;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	391 } while (current_index != 0 && count < 80);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	392 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	393 uint16_t sat_address = (context->regs[REG_SAT] & 0x7E) << 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	394 for (int i = 0; i < 64; i++)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	395 {
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	396 uint8_t y = context->vdpmem[mode4_address_map[sat_address + (i ^ 1)]];
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	397 if (y == 0xD0) {
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	398 break;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	399 }
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	400 uint8_t x = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2 + 1]];
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	401 uint16_t tile_address = context->vdpmem[mode4_address_map[sat_address + 0x80 + i2]] 32
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	402 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	403 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	404 tile_address &= ~32;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	405 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	406 printf("Sprite %d: X=%d, Y=%d, Pat=%X\n", i, x, y, tile_address);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	407 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	408 }
322 8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	409 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview. Mike Pavone <pavone@retrodev.com> parents: 318 diff changeset	410
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	411 #define VRAM_READ 0 //0000
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	412 #define VRAM_WRITE 1 //0001
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	413 //2 would trigger register write 0010
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	414 #define CRAM_WRITE 3 //0011
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	415 #define VSRAM_READ 4 //0100
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	416 #define VSRAM_WRITE 5//0101
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	417 //6 would trigger regsiter write 0110
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	418 //7 is a mystery //0111
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	419 #define CRAM_READ 8 //1000
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	420 //9 is also a mystery //1001
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	421 //A would trigger register write 1010
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	422 //B is a mystery 1011
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	423 #define VRAM_READ8 0xC //1100
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	424 //D is a mystery 1101
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	425 //E would trigger register write 1110
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	426 //F is a mystery 1111
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	427
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	428 //Possible theory on how bits work
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	429 //CD0 = Read/Write flag
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	430 //CD2,(CD1\|CD3) = RAM type
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	431 // 00 = VRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	432 // 01 = CRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	433 // 10 = VSRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	434 // 11 = VRAM8
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	435 //Would result in
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	436 // 7 = VRAM8 write
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	437 // 9 = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	438 // B = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	439 // D = VRAM8 write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	440 // F = VRAM8 write alais
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	441
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	442 #define DMA_START 0x20
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	443
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	444 static const char * cd_name(uint8_t cd)
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	445 {
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	446 switch (cd & 0xF)
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	447 {
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	448 case VRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	449 return "VRAM read";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	450 case VRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	451 return "VRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	452 case CRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	453 return "CRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	454 case VSRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	455 return "VSRAM read";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	456 case VSRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	457 return "VSRAM write";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	458 case VRAM_READ8:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	459 return "VRAM read (undocumented 8-bit mode)";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	460 default:
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	461 return "invalid";
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	462 }
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	463 }
ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	464
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	465 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	466 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	467 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	468 printf("Mode Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	469 "00: %.2X \| H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1331 9bba5ff5beb8 Add 128K VRAM bit to VDP register print in debugger Michael Pavone <pavone@retrodev.com> parents: 1325 diff changeset	470 "01: %.2X \| Display %s, V-ints %s, Height: %d, Mode %d, %dK VRAM\n"
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	471 "0B: %.2X \| E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	472 "0C: %.2X \| Width: %d, Shadow/Highlight: %s\n",
757 483f7e7926a6 More clang warning cleanup Michael Pavone <pavone@retrodev.com> parents: 748 diff changeset	473 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", (context->regs[REG_MODE_1] & BIT_PAL_SEL) != 0,
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	474 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	475 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
1331 9bba5ff5beb8 Add 128K VRAM bit to VDP register print in debugger Michael Pavone <pavone@retrodev.com> parents: 1325 diff changeset	476 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, context->regs[REG_MODE_1] & BIT_128K_VRAM ? 128 : 64,
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	477 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	478 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	479 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	480 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	481 printf("\nTable Group\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	482 "02: %.2X \| Scroll A Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	483 "03: %.2X \| Window Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	484 "04: %.2X \| Scroll B Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	485 "05: %.2X \| Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	486 "0D: %.2X \| HScroll Data Table: $%.4X\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	487 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	488 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	489 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
1320 df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	490 context->regs[REG_SAT], mode5_sat_address(context),
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	491 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	492 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	493 printf("\nTable Group\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	494 "02: %.2X \| Background Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	495 "05: %.2X \| Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	496 "06: %.2X \| Sprite Tile Base: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	497 "08: %.2X \| Background X Scroll: %d\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	498 "09: %.2X \| Background Y Scroll: %d\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	499 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0xE) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	500 context->regs[REG_SAT], (context->regs[REG_SAT] & 0x7E) << 7,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	501 context->regs[REG_STILE_BASE], (context->regs[REG_STILE_BASE] & 2) << 11,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	502 context->regs[REG_X_SCROLL], context->regs[REG_X_SCROLL],
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	503 context->regs[REG_Y_SCROLL], context->regs[REG_Y_SCROLL]);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	504
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	505 }
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	506 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	507 printf("\nMisc Group\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	508 "07: %.2X \| Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	509 "0A: %.2X \| H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	510 "0F: %.2X \| Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	511 "10: %.2X \| Scroll A/B Size: %sx%s\n",
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	512 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR],
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	513 context->regs[REG_HINT], context->regs[REG_HINT],
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	514 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	515 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
621 5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	516 char * src_types[] = {"68K", "68K", "Copy", "Fill"};
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	517 printf("\nDMA Group\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	518 "13: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	519 "14: %.2X \| DMA Length: $%.4X words\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	520 "15: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	521 "16: %.2X \|\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	522 "17: %.2X \| DMA Source Address: $%.6X, Type: %s\n",
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	523 context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	524 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 \| context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	525 context->regs[REG_DMASRC_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	526 context->regs[REG_DMASRC_M],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	527 context->regs[REG_DMASRC_H],
629 9089951a1994 Small fix to display of DMA source address in vr debug command Michael Pavone <pavone@retrodev.com> parents: 624 diff changeset	528 context->regs[REG_DMASRC_H] << 17 \| context->regs[REG_DMASRC_M] << 9 \| context->regs[REG_DMASRC_L] << 1,
621 5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes. Michael Pavone <pavone@retrodev.com> parents: 515 diff changeset	529 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]);
438 b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	530 printf("\nInternal Group\n"
b3cee2fe690b Add address/cd registers to VDP debug message Mike Pavone <pavone@retrodev.com> parents: 437 diff changeset	531 "Address: %X\n"
705 ce4046476abc Add description of cd register value to vr debugger command Michael Pavone <pavone@retrodev.com> parents: 699 diff changeset	532 "CD: %X - %s\n"
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	533 "Pending: %s\n"
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	534 "VCounter: %d\n"
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	535 "HCounter: %d\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	536 "VINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	537 "HINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	538 "Status: %X\n",
1150 322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode Michael Pavone <pavone@retrodev.com> parents: 1149 diff changeset	539 context->address, context->cd, cd_name(context->cd),
322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode Michael Pavone <pavone@retrodev.com> parents: 1149 diff changeset	540 (context->flags & FLAG_PENDING) ? "word" : (context->flags2 & FLAG2_BYTE_PENDING) ? "byte" : "none",
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	541 context->vcounter, context->hslot*2, (context->flags2 & FLAG2_VINT_PENDING) ? "true" : "false",
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	542 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context));
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	543
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	544 //TODO: Window Group, DMA Group
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	545 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	546
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	547 static uint8_t is_active(vdp_context *context)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	548 {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	549 return context->state != INACTIVE && (context->regs[REG_MODE_2] & BIT_DISP_EN) != 0;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	550 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	551
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	552 static void scan_sprite_table(uint32_t line, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	553 {
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	554 if (context->sprite_index && ((uint8_t)context->slot_counter) < context->max_sprites_line) {
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	555 line += 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	556 line &= 0xFF;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	557 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	558 uint8_t height_mult;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	559 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	560 line *= 2;
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	561 if (context->flags2 & FLAG2_EVEN_FIELD) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	562 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	563 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	564 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	565 ymin = 256;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	566 height_mult = 16;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	567 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	568 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	569 ymin = 128;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	570 height_mult = 8;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	571 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	572 context->sprite_index &= 0x7F;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	573 //TODO: Implement squirelly behavior documented by Kabuto
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	574 if (context->sprite_index >= context->max_sprites_frame) {
38 898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	575 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	576 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior Mike Pavone <pavone@retrodev.com> parents: 37 diff changeset	577 }
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	578 uint16_t address = context->sprite_index * 4;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	579 line += ymin;
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	580 uint16_t y = ((context->sat_cache[address] & 0x3) << 8 \| context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	581 uint8_t height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	582 //printf("Sprite %d \| y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	583 if (y <= line && line < (y + height)) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	584 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	585 context->sprite_info_list[context->slot_counter].size = context->sat_cache[address+2];
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	586 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	587 context->sprite_info_list[context->slot_counter++].y = y-ymin;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	588 }
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	589 context->sprite_index = context->sat_cache[address+3] & 0x7F;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	590 if (context->sprite_index && ((uint8_t)context->slot_counter) < context->max_sprites_line)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	591 {
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	592 //TODO: Implement squirelly behavior documented by Kabuto
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	593 if (context->sprite_index >= context->max_sprites_frame) {
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	594 context->sprite_index = 0;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	595 return;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	596 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	597 address = context->sprite_index * 4;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	598 y = ((context->sat_cache[address] & 0x3) << 8 \| context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	599 height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	600 //printf("Sprite %d \| y: %d, height: %d\n", context->sprite_index, y, height);
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	601 if (y <= line && line < (y + height)) {
27 aa1c47fab3f1 Fix sprite transparency for overlapping sprites Mike Pavone <pavone@retrodev.com> parents: 26 diff changeset	602 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	603 context->sprite_info_list[context->slot_counter].size = context->sat_cache[address+2];
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	604 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	605 context->sprite_info_list[context->slot_counter++].y = y-ymin;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	606 }
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	607 context->sprite_index = context->sat_cache[address+3] & 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	608 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	609 }
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	610 //TODO: Seems like the overflow flag should be set here if we run out of sprite info slots without hitting the end of the list
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	611 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	612
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	613 static void scan_sprite_table_mode4(vdp_context * context)
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	614 {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	615 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	616 uint32_t line = context->vcounter;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	617 line &= 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	618
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	619 uint32_t sat_address = mode4_address_map[(context->regs[REG_SAT] << 7 & 0x3F00) + context->sprite_index];
1138 25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping Michael Pavone <pavone@retrodev.com> parents: 1137 diff changeset	620 uint32_t y = context->vdpmem[sat_address+1];
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	621 uint32_t size = (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) ? 16 : 8;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	622
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	623 if (y == 0xd0) {
1122 d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	624 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	625 return;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	626 } else {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	627 if (y <= line && line < (y + size)) {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	628 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	629 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	630 context->flags \|= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	631 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	632 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	633 context->sprite_info_list[--(context->slot_counter)].size = size;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	634 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	635 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	636 context->sprite_index++;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	637 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	638
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	639 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1138 25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping Michael Pavone <pavone@retrodev.com> parents: 1137 diff changeset	640 y = context->vdpmem[sat_address];
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	641 if (y == 0xd0) {
1122 d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	642 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	643 return;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	644 } else {
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	645 if (y <= line && line < (y + size)) {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	646 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	647 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	648 context->flags \|= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	649 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	650 }
1122 d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	651 context->sprite_info_list[--(context->slot_counter)].size = size;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	652 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	653 }
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	654 context->sprite_index++;
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	655 }
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	656 }
d4bef26d0977 Implemented Mode 4 sprite list termination Michael Pavone <pavone@retrodev.com> parents: 1121 diff changeset	657
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	658 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	659 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	660
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	661 static void read_sprite_x(uint32_t line, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	662 {
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	663 if (context->cur_slot == context->max_sprites_line) {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	664 context->cur_slot = 0;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	665 }
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	666 if (context->cur_slot < context->slot_counter) {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	667 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	668 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	669 line &= 0xFF;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	670 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	671 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	672 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	673 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	674 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	675 line *= 2;
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	676 if (context->flags2 & FLAG2_EVEN_FIELD) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	677 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	678 }
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	679 height *= 2;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	680 }
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	681 uint16_t ymask, ymin;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	682 if (context->double_res) {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	683 ymask = 0x3FF;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	684 ymin = 256;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	685 } else {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	686 ymask = 0x1FF;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	687 ymin = 128;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	688 }
1320 df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	689 uint16_t att_addr = mode5_sat_address(context) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	690 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) \| context->vdpmem[att_addr+1];
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	691 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	692 uint8_t row;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	693 uint16_t cache_addr = context->sprite_info_list[context->cur_slot].index * 4;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	694 int16_t y = ((context->sat_cache[cache_addr] << 8 \| context->sat_cache[cache_addr+1]) & ymask) - ymin;
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	695 if (tileinfo & MAP_BIT_V_FLIP) {
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	696 row = (y + height - 1) - line;
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	697 } else {
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	698 row = line-y;
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	699 }
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	700 row &= ymask >> 4;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	701 uint16_t address;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	702 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	703 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	704 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	705 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	706 }
323 8c01b4154480 Properly mask sprite X and Y coordinates Mike Pavone <pavone@retrodev.com> parents: 322 diff changeset	707 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 \| context->vdpmem[att_addr + 3]) & 0x1FF;
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	708 if (x) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	709 context->flags \|= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	710 } else if(context->flags & (FLAG_CAN_MASK \| FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	711 context->flags \|= FLAG_MASKED;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	712 }
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	713
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	714 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	715 int16_t i;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	716 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	717 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	718 --context->sprite_draws;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	719 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	720 }
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	721 } else {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	722 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	723 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	724 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	725 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	726 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	727 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	728 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	729 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	730 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	731 //printf("Sprite %d \| x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35 233c7737c152 Small fix to overflow flag Mike Pavone <pavone@retrodev.com> parents: 34 diff changeset	732 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	733 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	734 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	735 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	736 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	737 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	738 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	739 }
1000 1a797fcbb35f Added TODO for hardware checking Michael Pavone <pavone@retrodev.com> parents: 999 diff changeset	740 //Used to be i < width
1a797fcbb35f Added TODO for hardware checking Michael Pavone <pavone@retrodev.com> parents: 999 diff changeset	741 //TODO: Confirm this is the right condition on hardware
1a797fcbb35f Added TODO for hardware checking Michael Pavone <pavone@retrodev.com> parents: 999 diff changeset	742 if (!context->sprite_draws) {
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	743 context->flags \|= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	744 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	745 } else {
34 0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test Mike Pavone <pavone@retrodev.com> parents: 32 diff changeset	746 context->flags \|= FLAG_DOT_OFLOW;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	747 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	748 }
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	749 context->cur_slot++;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	750 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	751
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	752 static void read_sprite_x_mode4(vdp_context * context)
427 2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	753 {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	754 if (context->cur_slot >= context->slot_counter) {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	755 uint32_t address = (context->regs[REG_SAT] << 7 & 0x3F00) + 0x80 + context->sprite_info_list[context->cur_slot].index * 2;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	756 address = mode4_address_map[address];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	757 --context->sprite_draws;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	758 uint32_t tile_address = context->vdpmem[address] * 32 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	759 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	760 tile_address &= ~32;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	761 }
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	762 tile_address += (context->vcounter - context->sprite_info_list[context->cur_slot].y)* 4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	763 context->sprite_draw_list[context->sprite_draws].x_pos = context->vdpmem[address + 1];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	764 context->sprite_draw_list[context->sprite_draws].address = tile_address;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	765 context->cur_slot--;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	766 }
427 2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	767 }
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process Mike Pavone <pavone@retrodev.com> parents: 426 diff changeset	768
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	769 #define CRAM_BITS 0xEEE
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	770 #define VSRAM_BITS 0x7FF
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	771 #define VSRAM_DIRTY_BITS 0xF800
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	772
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	773 //rough estimate of slot number at which border display starts
1270 687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	774 #define BG_START_SLOT 6
1183 8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	775
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	776 void write_cram(vdp_context * context, uint16_t address, uint16_t value)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	777 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	778 uint16_t addr;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	779 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	780 addr = (address/2) & (CRAM_SIZE-1);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	781 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	782 addr = address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	783 value = (value << 1 & 0xE) \| (value << 2 & 0xE0) \| (value & 0xE00);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	784 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	785 context->cram[addr] = value;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	786 context->colors[addr] = color_map[value & CRAM_BITS];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	787 context->colors[addr + CRAM_SIZE] = color_map[(value & CRAM_BITS) \| FBUF_SHADOW];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	788 context->colors[addr + CRAM_SIZE*2] = color_map[(value & CRAM_BITS) \| FBUF_HILIGHT];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	789 context->colors[addr + CRAM_SIZE*3] = color_map[(value & CRAM_BITS) \| FBUF_MODE4];
1183 8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	790
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	791 if (context->hslot >= BG_START_SLOT && (
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	792 context->vcounter < context->inactive_start + context->border_bot
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	793 \|\| context->vcounter > 0x200 - context->border_top
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	794 )) {
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	795 uint8_t bg_end_slot = BG_START_SLOT + (context->regs[REG_MODE_4] & BIT_H40) ? LINEBUF_SIZE/2 : (256+HORIZ_BORDER)/2;
1183 8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	796 if (context->hslot < bg_end_slot) {
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	797 uint32_t color = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->colors[addr] : context->colors[addr + CRAM_SIZE*3];
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	798 context->output[(context->hslot - BG_START_SLOT)*2 + 1] = color;
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	799 }
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	800 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	801 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	802
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	803 static void vdp_advance_dma(vdp_context * context)
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	804 {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	805 context->regs[REG_DMASRC_L] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	806 if (!context->regs[REG_DMASRC_L]) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	807 context->regs[REG_DMASRC_M] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	808 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	809 context->address += context->regs[REG_AUTOINC];
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	810 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L]) - 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	811 context->regs[REG_DMALEN_H] = dma_len >> 8;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	812 context->regs[REG_DMALEN_L] = dma_len;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	813 if (!dma_len) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	814 context->flags &= ~FLAG_DMA_RUN;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	815 context->cd &= 0xF;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	816 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	817 }
1019 e34334e6c682 Fix GST savestate loading to deal with SAT cache to fix sprite corruption on savestate load. Clear out Z80 native_pc so the Z80 state does not get hosed when loading a savestate while the emulator is already running Michael Pavone <pavone@retrodev.com> parents: 1001 diff changeset	818
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	819 static void vdp_check_update_sat(vdp_context *context, uint32_t address, uint16_t value)
1319 b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	820 {
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	821 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	822 if (!(address & 4)) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	823 uint32_t sat_address = mode5_sat_address(context);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	824 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	825 uint16_t cache_address = address - sat_address;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	826 cache_address = (cache_address & 3) \| (cache_address >> 1 & 0x1FC);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	827 context->sat_cache[cache_address] = value >> 8;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	828 context->sat_cache[cache_address^1] = value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	829 }
1319 b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	830 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	831 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	832 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	833
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	834 void vdp_check_update_sat_byte(vdp_context *context, uint32_t address, uint8_t value)
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	835 {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	836 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	837 if (!(address & 4)) {
1320 df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1319 diff changeset	838 uint32_t sat_address = mode5_sat_address(context);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	839 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	840 uint16_t cache_address = address - sat_address;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	841 cache_address = (cache_address & 3) \| (cache_address >> 1 & 0x1FC);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	842 context->sat_cache[cache_address] = value;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	843 }
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	844 }
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	845 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	846 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	847
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	848 static void write_vram_word(vdp_context *context, uint32_t address, uint16_t value)
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	849 {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	850 address = (address & 0x3FC) \| (address >> 1 & 0xFC01) \| (address >> 9 & 0x2);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	851 address ^= 1;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	852 //TODO: Support an option to actually have 128KB of VRAM
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	853 context->vdpmem[address] = value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	854 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	855
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	856 static void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value)
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	857 {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	858 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1319 b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	859 address &= 0xFFFF;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	860 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	861 address = mode4_address_map[address & 0x3FFF];
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	862 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	863 context->vdpmem[address] = value;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	864 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	865
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	866 static void external_slot(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	867 {
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	868 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && context->fifo_read < 0) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	869 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	870 fifo_entry * cur = context->fifo + context->fifo_read;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	871 cur->cycle = context->cycles;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	872 cur->address = context->address;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	873 cur->partial = 2;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	874 vdp_advance_dma(context);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	875 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	876 fifo_entry * start = context->fifo + context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	877 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	878 switch (start->cd & 0xF)
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	879 {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	880 case VRAM_WRITE:
1319 b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	881 if ((context->regs[REG_MODE_2] & (BIT_128K_VRAM\|BIT_MODE_5)) == (BIT_128K_VRAM\|BIT_MODE_5)) {
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	882 vdp_check_update_sat(context, start->address, start->value);
1319 b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	883 write_vram_word(context, start->address, start->value);
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache Michael Pavone <pavone@retrodev.com> parents: 1318 diff changeset	884 } else if (start->partial) {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	885 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	886 uint8_t byte = start->partial == 2 ? start->value >> 8 : start->value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	887 if (start->partial > 1) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	888 vdp_check_update_sat_byte(context, start->address ^ 1, byte);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	889 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	890 write_vram_byte(context, start->address ^ 1, byte);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	891 } else {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	892 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	893 vdp_check_update_sat(context, start->address, start->value);
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	894 write_vram_byte(context, start->address, start->value >> 8);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	895 start->partial = 1;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	896 //skip auto-increment and removal of entry from fifo
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	897 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	898 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	899 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	900 case CRAM_WRITE: {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	901 //printf("CRAM Write \| %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	902 if (start->partial == 3) {
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	903 uint16_t val;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	904 if ((start->address & 1) && (context->regs[REG_MODE_2] & BIT_MODE_5)) {
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	905 val = (context->cram[start->address >> 1 & (CRAM_SIZE-1)] & 0xFF) \| start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	906 } else {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	907 uint16_t address = (context->regs[REG_MODE_2] & BIT_MODE_5) ? start->address >> 1 & (CRAM_SIZE-1) : start->address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	908 val = (context->cram[address] & 0xFF00) \| start->value;
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	909 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	910 write_cram(context, start->address, val);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	911 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	912 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	913 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	914 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	915 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	916 case VSRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	917 if (((start->address/2) & 63) < VSRAM_SIZE) {
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	918 //printf("VSRAM Write: %X to %X @ vcounter: %d, hslot: %d, cycle: %d\n", start->value, context->address, context->vcounter, context->hslot, context->cycles);
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	919 if (start->partial == 3) {
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	920 if (start->address & 1) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	921 context->vsram[(start->address/2) & 63] &= 0xFF;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	922 context->vsram[(start->address/2) & 63] \|= start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	923 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	924 context->vsram[(start->address/2) & 63] &= 0xFF00;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	925 context->vsram[(start->address/2) & 63] \|= start->value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	926 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	927 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	928 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	929 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	930 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	931
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	932 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	933 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	934 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	935 if (context->fifo_read == context->fifo_write) {
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	936 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	937 context->flags \|= FLAG_DMA_RUN;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	938 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	939 context->fifo_read = -1;
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	940 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	941 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	942 if (context->flags & FLAG_READ_FETCHED) {
998 bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug. Michael Pavone <pavone@retrodev.com> parents: 995 diff changeset	943 write_vram_byte(context, context->address ^ 1, context->prefetch);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	944
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	945 //Update DMA state
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	946 vdp_advance_dma(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	947
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	948 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	949 } else {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	950 context->prefetch = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L] ^ 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	951
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	952 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	953 }
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	954 } else if (!(context->cd & 1) && !(context->flags & (FLAG_READ_FETCHED\|FLAG_PENDING))) {
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	955 switch(context->cd & 0xF)
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	956 {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	957 case VRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	958 if (context->flags2 & FLAG2_READ_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	959 context->prefetch \|= context->vdpmem[context->address \| 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	960 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	961 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	962 //Should this happen after the prefetch or after the read?
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	963 increment_address(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	964 } else {
1318 bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support Michael Pavone <pavone@retrodev.com> parents: 1315 diff changeset	965 //TODO: 128K VRAM Mode
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	966 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	967 context->flags2 \|= FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	968 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	969 break;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	970 case VRAM_READ8: {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	971 uint32_t address = context->address ^ 1;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	972 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	973 address = mode4_address_map[address & 0x3FFF];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	974 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	975 context->prefetch = context->vdpmem[address];
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	976 context->prefetch \|= context->fifo[context->fifo_write].value & 0xFF00;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	977 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	978 //Should this happen after the prefetch or after the read?
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	979 increment_address(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	980 break;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	981 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	982 case CRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	983 context->prefetch = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	984 context->prefetch \|= context->fifo[context->fifo_write].value & ~CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	985 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	986 //Should this happen after the prefetch or after the read?
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	987 increment_address(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	988 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	989 case VSRAM_READ: {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	990 uint16_t address = (context->address /2) & 63;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	991 if (address >= VSRAM_SIZE) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	992 address = 0;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	993 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	994 context->prefetch = context->vsram[address] & VSRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	995 context->prefetch \|= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	996 context->flags \|= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	997 //Should this happen after the prefetch or after the read?
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	998 increment_address(context);
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	999 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	1000 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	1001 }
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1002 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1003 }
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1004
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1005 static void run_dma_src(vdp_context * context, int32_t slot)
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1006 {
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1007 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1008 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	1009 if (context->fifo_write == context->fifo_read) {
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1010 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1011 }
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1012 fifo_entry * cur = NULL;
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	1013 if (!(context->regs[REG_DMASRC_H] & 0x80))
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	1014 {
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	1015 //68K -> VDP
924 1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period Michael Pavone <pavone@retrodev.com> parents: 923 diff changeset	1016 if (slot == -1 \|\| !is_refresh(context, slot-1)) {
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1017 cur = context->fifo + context->fifo_write;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1018 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
478 2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1019 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1020 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) \| (context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1021 cur->cd = context->cd;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1022 cur->partial = 0;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1023 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1024 context->fifo_read = context->fifo_write;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1025 }
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all. Mike Pavone <pavone@retrodev.com> parents: 477 diff changeset	1026 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
984 bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 983 diff changeset	1027 vdp_advance_dma(context);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	1028 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1029 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1030 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1031
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1032 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1033 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1034
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1035 static void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1036 {
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1037 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1038 if (context->double_res) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1039 line *= 2;
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1040 if (context->flags2 & FLAG2_EVEN_FIELD) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1041 line++;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1042 }
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1043 window_line_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1044 v_offset_mask = 0xF;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1045 vscroll_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1046 } else {
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1047 window_line_shift = 3;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1048 v_offset_mask = 0x7;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1049 vscroll_shift = 3;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1050 }
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1051 if (!vsram_off) {
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1052 uint16_t left_col, right_col;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1053 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
920 e64168bb2b25 Fix calculation of window start column when it's on the right side. This removes graphical glitches in Afterburner 2, Fireshark and Dungeons and Dragons: Warriors of the Eternal Sun and probably others Michael Pavone <pavone@retrodev.com> parents: 884 diff changeset	1054 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2 + 2;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1055 right_col = 42;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1056 } else {
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1057 left_col = 0;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1058 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1059 if (right_col) {
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1060 right_col += 2;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1061 }
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1062 }
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1063 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1064 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1065 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1066 bottom_line = context->double_res ? 481 : 241;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1067 } else {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1068 top_line = 0;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1069 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1070 }
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1071 if ((column >= left_col && column < right_col) \|\| (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1072 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1073 uint16_t line_offset, offset, mask;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	1074 if (context->regs[REG_MODE_4] & BIT_H40) {
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1075 address &= 0xF000;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1076 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1077 mask = 0x7F;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	1078
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1079 } else {
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1080 address &= 0xF800;
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1081 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1082 mask = 0x3F;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1083 }
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1084 if (context->double_res) {
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1085 mask <<= 1;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1086 mask \|= 1;
acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1087 }
42 6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane. Mike Pavone <pavone@retrodev.com> parents: 41 diff changeset	1088 offset = address + line_offset + (((column - 2) * 2) & mask);
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1089 context->col_1 = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	1090 //printf("Window \| top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42 6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane. Mike Pavone <pavone@retrodev.com> parents: 41 diff changeset	1091 offset = address + line_offset + (((column - 1) * 2) & mask);
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1092 context->col_2 = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
417 acdd6c5240fe Fix window layer in double res interlace mode Mike Pavone <pavone@retrodev.com> parents: 415 diff changeset	1093 context->v_offset = (line) & v_offset_mask;
41 e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1094 context->flags \|= FLAG_WINDOW;
e591004487bc More correct window support, maybe Mike Pavone <pavone@retrodev.com> parents: 40 diff changeset	1095 return;
40 7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1096 }
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1097 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support Mike Pavone <pavone@retrodev.com> parents: 39 diff changeset	1098 }
1290 aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk Michael Pavone <pavone@retrodev.com> parents: 1289 diff changeset	1099 //TODO: Verify behavior for 0x20 case
aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk Michael Pavone <pavone@retrodev.com> parents: 1289 diff changeset	1100 uint16_t vscroll = 0xFF \| (context->regs[REG_SCROLL] & 0x30) << 4;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1101 if (context->double_res) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1102 vscroll <<= 1;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1103 vscroll \|= 1;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1104 }
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1105 //TODO: Further research on vscroll latch behavior and the "first column bug"
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1106 if (!column) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1107 if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1108 if (context->regs[REG_MODE_4] & BIT_H40) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1109 //Based on observed behavior documented by Eke-Eke, I'm guessing the VDP
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1110 //ends up fetching the last value on the VSRAM bus in the H40 case
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1111 //getting the last latched value should be close enough for now
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1112 if (!vsram_off) {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1113 context->vscroll_latch[0] = context->vscroll_latch[1];
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1114 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1115 } else {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1116 //supposedly it's always forced to 0 in the H32 case
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1117 context->vscroll_latch[0] = context->vscroll_latch[1] = 0;
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1118 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1119 } else {
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1120 context->vscroll_latch[vsram_off] = context->vsram[vsram_off];
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1121 }
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	1122 } else if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
710 4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	1123 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off];
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	1124 }
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it Michael Pavone <pavone@retrodev.com> parents: 708 diff changeset	1125 vscroll &= context->vscroll_latch[vsram_off] + line;
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1126 context->v_offset = vscroll & v_offset_mask;
26 a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should Mike Pavone <pavone@retrodev.com> parents: 25 diff changeset	1127 //printf("%s \| line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414 51ee0f117365 Fix vscroll calculation in double resultion interlace mode Mike Pavone <pavone@retrodev.com> parents: 413 diff changeset	1128 vscroll >>= vscroll_shift;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1129 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1130 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1131 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1132 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1133 case 0:
108 1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1134 hscroll_mask = 0x1F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1135 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1136 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1137 case 0x1:
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	1138 hscroll_mask = 0x3F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1139 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1140 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1141 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1142 //TODO: Verify this behavior
1334 7757d605e365 Adjust how the invalid size is handled for the horizontal dimmension of a plane. Fixes some garbage on the spinning cube scene of Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1333 diff changeset	1143 hscroll_mask = 0x1F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1144 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1145 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1146 case 0x3:
108 1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1147 hscroll_mask = 0x7F;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1148 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1149 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1150 }
28 037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1151 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1152 for (int i = 0; i < 2; i++) {
39 3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	1153 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	1154 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should Mike Pavone <pavone@retrodev.com> parents: 38 diff changeset	1155 //printf("%s \| line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28 037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1156 uint16_t col_val = (context->vdpmem[offset] << 8) \| context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1157 if (i) {
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1158 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1159 } else {
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1160 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1161 }
037963b4c92d Fix BG plane B render bug Mike Pavone <pavone@retrodev.com> parents: 27 diff changeset	1162 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1163 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1164
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1165 static void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1166 {
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	1167 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1168 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1169
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1170 static void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1171 {
25 4d0c20ad815a Fix vertical scroll value for plane B Mike Pavone <pavone@retrodev.com> parents: 24 diff changeset	1172 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1173 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1174
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1175 static void read_map_mode4(uint16_t column, uint32_t line, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1176 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1177 uint32_t address = (context->regs[REG_SCROLL_A] & 0xE) << 10;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1178 //add row
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1179 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1180 if (column < 24 \|\| !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1181 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1182 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1183 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1184 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1185 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1186 address += (vscroll >> 3) * 2 * 32;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1187 //add column
1136 52f25c41abdd Fix horizontal scrolling in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1135 diff changeset	1188 address += ((column - (context->hscroll_a >> 3)) & 31) * 2;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1189 //adjust for weird VRAM mapping in Mode 4
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1190 address = mode4_address_map[address];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1191 context->col_1 = (context->vdpmem[address] << 8) \| context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1192 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1193
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1194 static void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1195 {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1196 uint16_t address;
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1197 uint16_t vflip_base;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1198 if (context->double_res) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1199 address = ((col & 0x3FF) << 6);
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1200 vflip_base = 60;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1201 } else {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1202 address = ((col & 0x7FF) << 5);
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1203 vflip_base = 28;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	1204 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1205 if (col & MAP_BIT_V_FLIP) {
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1206 address += vflip_base - 4 * context->v_offset;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1207 } else {
1032 679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode Michael Pavone <pavone@retrodev.com> parents: 1029 diff changeset	1208 address += 4 * context->v_offset;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1209 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1210 uint16_t pal_priority = (col >> 9) & 0x70;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1211 int32_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1212 if (col & MAP_BIT_H_FLIP) {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1213 offset += 7;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1214 offset &= SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1215 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1216 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1217 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1218 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1219 for (uint32_t i=0; i < 4; i++, address++)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1220 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1221 tmp_buf[offset] = pal_priority \| (context->vdpmem[address] >> 4);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1222 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1223 offset &= SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1224 tmp_buf[offset] = pal_priority \| (context->vdpmem[address] & 0xF);
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1225 offset += dir;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1226 offset &= SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1227 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1228 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1229
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1230 static void render_map_1(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1231 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1232 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1233 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1234
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1235 static void render_map_2(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1236 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1237 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1238 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1239
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1240 static void render_map_3(vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1241 {
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1242 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1243 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1244
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1245 static void fetch_map_mode4(uint16_t col, uint32_t line, vdp_context *context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1246 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1247 //calculate pixel row to fetch
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1248 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1249 if (col < 24 \|\| !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1250 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1251 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1252 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1253 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1254 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1255 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1256 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1257 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1258 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1259
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1260 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1261 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1262 context->fetch_tmp[1] = context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1263 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1264
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1265 static void render_map_output(uint32_t line, int32_t col, vdp_context * context)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1266 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1267 uint32_t *dst;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1268 if (context->state == PREPARING) {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1269 if (!col) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1270 return;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1271 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1272 col -= 2;
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1273 if (col) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1274 dst = context->output + BORDER_LEFT + col * 8;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1275 } else {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1276 dst = context->output;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1277 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1278 for (int i = 0; i < BORDER_LEFT; i++, dst++)
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1279 {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1280 *dst = bg_color;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1281 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1282 }
1170 9170fc4d9835 Don't adjust cycles every frame. Only when we start getting close to UINT_MAX. Don't adjust all the way down to zero when we do adjust. Shouldn't fix anything, but may make debugging current issues easier. Michael Pavone <pavone@retrodev.com> parents: 1169 diff changeset	1283 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1284 for (int i = 0; i < 16; i++)
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1285 {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1286 *(dst++) = color;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1287 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1288 return;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1289 }
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1290 line &= 0xFF;
1180 e2b81a0f8fd8 Undo poorly thought out minor optimization that screwed up rendering Michael Pavone <pavone@retrodev.com> parents: 1179 diff changeset	1291 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1292 uint8_t sprite_buf, plane_a, *plane_b;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1293 int plane_a_off, plane_b_off;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1294 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1295 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1296 col-=2;
1270 687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1297 if (col) {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1298 dst = context->output + BORDER_LEFT + col * 8;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1299 } else {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1300 dst = context->output;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1301 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1302 for (int i = 0; i < BORDER_LEFT; i++, dst++)
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1303 {
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1304 *dst = bg_color;
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1305 }
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13 Michael Pavone <pavone@retrodev.com> parents: 1269 diff changeset	1306 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1307 if (context->debug < 2) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1308 sprite_buf = context->linebuf + col * 8;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1309 uint8_t a_src, src;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1310 if (context->flags & FLAG_WINDOW) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1311 plane_a_off = context->buf_a_off;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1312 a_src = DBG_SRC_W;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1313 } else {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1314 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1315 a_src = DBG_SRC_A;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1316 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1317 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1318 //printf("A \| tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1319 uint8_t output_disabled = (context->test_port & TEST_BIT_DISABLE) != 0;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1320 uint8_t test_layer = context->test_port >> 7 & 3;
450 3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty Mike Pavone <pavone@retrodev.com> parents: 438 diff changeset	1321
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1322 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1323 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1324 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1325 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1326 uint8_t pixel = context->regs[REG_BG_COLOR];
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1327 uint32_t *colors = context->colors;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1328 src = DBG_SRC_BG;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1329 if (*plane_b & 0xF) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1330 pixel = *plane_b;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1331 src = DBG_SRC_B;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1332 }
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1333 uint8_t intensity = *plane_b & BUF_BIT_PRIORITY;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1334 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1335 pixel = *plane_a;
1315 810ae0287d66 Fix minor bug that displayed window plane as if it were plane A In plane debug view Michael Pavone <pavone@retrodev.com> parents: 1299 diff changeset	1336 src = a_src;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1337 }
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1338 intensity \|= *plane_a & BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1339 if (sprite_buf & 0xF && (sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1340 if ((*sprite_buf & 0x3F) == 0x3E) {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1341 intensity += BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1342 } else if ((*sprite_buf & 0x3F) == 0x3F) {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1343 intensity = 0;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1344 } else {
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1345 pixel = *sprite_buf;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1346 src = DBG_SRC_S;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1347 if ((pixel & 0xF) == 0xE) {
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1348 intensity = BUF_BIT_PRIORITY;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1349 } else {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1350 intensity \|= pixel & BUF_BIT_PRIORITY;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1351 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1352 }
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1353 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1354 if (output_disabled) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1355 pixel = 0x3F;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1356 }
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1357 if (!intensity) {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	1358 src \|= DBG_SHADOW;
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1359 colors += CRAM_SIZE;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1360 } else if (intensity == BUF_BIT_PRIORITY*2) {
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1361 src \|= DBG_HILIGHT;
45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1362 colors += CRAM_SIZE*2;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1363 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1364 //TODO: Verify how test register stuff interacts with shadow/highlight
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1365 //TODO: Simulate CRAM corruption from bus fight
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1366 switch (test_layer)
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1367 {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1368 case 1:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1369 pixel &= *sprite_buf;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1370 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1371 src = DBG_SRC_S;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1372 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1373 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1374 case 2:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1375 pixel &= *plane_a;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1376 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1377 src = DBG_SRC_A;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1378 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1379 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1380 case 3:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1381 pixel &= *plane_b;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1382 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1383 src = DBG_SRC_B;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1384 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1385 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1386 }
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	1387
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1388 uint32_t outpixel;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1389 if (context->debug) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1390 outpixel = context->debugcolors[src];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1391 } else {
748 45b62d237b7b Fixed shadow/highlight mode Michael Pavone <pavone@retrodev.com> parents: 724 diff changeset	1392 outpixel = colors[pixel & 0x3F];
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1393 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1394 *(dst++) = outpixel;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1395 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1396 } else {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1397 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1398 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1399 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK);
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1400 uint8_t pixel = context->regs[REG_BG_COLOR];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1401 src = DBG_SRC_BG;
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1402 if (output_disabled) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1403 pixel = 0x3F;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1404 } else {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1405 if (*plane_b & 0xF) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1406 pixel = *plane_b;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1407 src = DBG_SRC_B;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1408 }
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1409 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1410 pixel = *plane_a;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1411 src = a_src;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1412 }
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1413 if (sprite_buf & 0xF && (sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1414 pixel = *sprite_buf;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1415 src = DBG_SRC_S;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1416 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1417 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1418 //TODO: Simulate CRAM corruption from bus fight
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1419 switch (test_layer)
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1420 {
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1421 case 1:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1422 pixel &= *sprite_buf;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1423 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1424 src = DBG_SRC_S;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1425 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1426 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1427 case 2:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1428 pixel &= *plane_a;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1429 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1430 src = DBG_SRC_A;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1431 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1432 break;
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1433 case 3:
b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1434 pixel &= *plane_b;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1435 if (output_disabled && pixel) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1436 src = DBG_SRC_B;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1437 }
1322 b1423d432c0e Initial stab at implementing the output disable/layer selection bits of the VDP test register Michael Pavone <pavone@retrodev.com> parents: 1321 diff changeset	1438 break;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1439 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1440 uint32_t outpixel;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1441 if (context->debug) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1442 outpixel = context->debugcolors[src];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1443 } else {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1444 outpixel = context->colors[pixel & 0x3F];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1445 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1446 *(dst++) = outpixel;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1447 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1448 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1449 } else if (context->debug == 2) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1450 if (col < 32) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1451 (dst++) = context->colors[col 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1452 (dst++) = context->colors[col 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1453 (dst++) = context->colors[col 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1454 (dst++) = context->colors[col 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1455 (dst++) = context->colors[col 2 + 1];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1456 (dst++) = context->colors[col 2 + 1];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1457 (dst++) = context->colors[col 2 + 1];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1458 (dst++) = context->colors[col 2 + 1];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1459 (dst++) = context->colors[col 2 + 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1460 (dst++) = context->colors[col 2 + 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1461 (dst++) = context->colors[col 2 + 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1462 (dst++) = context->colors[col 2 + 2];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1463 (dst++) = context->colors[col 2 + 3];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1464 (dst++) = context->colors[col 2 + 3];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1465 (dst++) = context->colors[col 2 + 3];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1466 (dst++) = context->colors[col 2 + 3];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1467 } else if (col == 32 \|\| line >= 192) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1468 for (int32_t i = 0; i < 16; i ++) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1469 *(dst++) = 0;
437 afbea09d7fb4 Restore one of the VDP debugging modes Mike Pavone <pavone@retrodev.com> parents: 436 diff changeset	1470 }
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1471 } else {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1472 for (int32_t i = 0; i < 16; i ++) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1473 (dst++) = context->colors[line / 3 + (col - 34) 0x20];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1474 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1475 }
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1476 } else {
771 0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3 Michael Pavone <pavone@retrodev.com> parents: 757 diff changeset	1477 uint32_t base = (context->debug - 3) * 0x200;
0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3 Michael Pavone <pavone@retrodev.com> parents: 757 diff changeset	1478 uint32_t cell = base + (line / 8) * (context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32) + col;
0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3 Michael Pavone <pavone@retrodev.com> parents: 757 diff changeset	1479 uint32_t address = (cell * 32 + (line % 8) * 4) & 0xFFFF;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1480 for (int32_t i = 0; i < 4; i ++) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1481 *(dst++) = context->colors[(context->debug_pal << 4) \| (context->vdpmem[address] >> 4)];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1482 *(dst++) = context->colors[(context->debug_pal << 4) \| (context->vdpmem[address] & 0xF)];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1483 address++;
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1484 }
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1485 cell++;
771 0565b2c1a034 Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3 Michael Pavone <pavone@retrodev.com> parents: 757 diff changeset	1486 address = (cell * 32 + (line % 8) * 4) & 0xFFFF;
722 8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1487 for (int32_t i = 0; i < 4; i ++) {
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1488 *(dst++) = context->colors[(context->debug_pal << 4) \| (context->vdpmem[address] >> 4)];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1489 *(dst++) = context->colors[(context->debug_pal << 4) \| (context->vdpmem[address] & 0xF)];
8f5339961903 Restore the other 2 debug display modes Michael Pavone <pavone@retrodev.com> parents: 720 diff changeset	1490 address++;
230 d3266cee02c9 Implemented shadow hilight mode. Mike Pavone <pavone@retrodev.com> parents: 191 diff changeset	1491 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1492 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1493 }
436 e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1494 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy Mike Pavone <pavone@retrodev.com> parents: 427 diff changeset	1495 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1496 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1497
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1498 static void render_map_mode4(uint32_t line, int32_t col, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1499 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1500 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1501 if (col < 24 \|\| !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1502 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1503 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1504 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1505 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1506 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1507 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1508 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1509 //vflip
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1510 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1511 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1512
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1513 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1514 pixels \|= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1515
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1516 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4 + 2];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1517 pixels \|= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1518 pixels \|= planar_to_chunky[context->vdpmem[address+1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1519
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1520 int i, i_inc, i_limit;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1521 if (context->col_1 & 0x200) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1522 //hflip
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1523 i = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1524 i_inc = 4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1525 i_limit = 32;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1526 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1527 i = 28;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1528 i_inc = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1529 i_limit = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1530 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1531 uint8_t pal_priority = (context->col_1 >> 7 & 0x10) \| (context->col_1 >> 6 & 0x40);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1532 for (uint8_t *dst = context->tmp_buf_a + context->buf_a_off; i != i_limit; i += i_inc, dst++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1533 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1534 *dst = (pixels >> i & 0xF) \| pal_priority;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1535 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1536 context->buf_a_off = (context->buf_a_off + 8) & 15;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1537
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1538 uint8_t bgcolor = 0x10 \| (context->regs[REG_BG_COLOR] & 0xF) + CRAM_SIZE*3;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1539 uint32_t dst = context->output + col 8;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1540 if (context->debug < 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1541 if (col \|\| !(context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1542 uint8_t sprite_src = context->linebuf + col 8;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1543 if (context->regs[REG_MODE_1] & BIT_SPRITE_8PX) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1544 sprite_src += 8;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1545 }
1121 1913f9c28003 Less broken Mode 4 implementation Michael Pavone <pavone@retrodev.com> parents: 1120 diff changeset	1546 for (int i = 0; i < 8; i++, sprite_src++)
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1547 {
1121 1913f9c28003 Less broken Mode 4 implementation Michael Pavone <pavone@retrodev.com> parents: 1120 diff changeset	1548 uint8_t bg_src = context->tmp_buf_a + ((8 + i + col 8 - (context->hscroll_a & 0x7)) & 15);
1132 fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1549 if ((bg_src & 0x4F) > 0x40 \|\| !sprite_src) {
fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1550 //background plane has priority and is opaque or sprite layer is transparent
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1551 if (context->debug) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1552 *(dst++) = context->debugcolors[DBG_SRC_A];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1553 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1554 (dst++) = context->colors[(bg_src & 0x1F) + CRAM_SIZE*3];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1555 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1556 } else {
1132 fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1557 //sprite layer is opaque and not covered by high priority BG pixels
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1558 if (context->debug) {
1132 fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1559 *(dst++) = context->debugcolors[DBG_SRC_S];
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1560 } else {
1132 fd3b8ac57aca Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5 Michael Pavone <pavone@retrodev.com> parents: 1127 diff changeset	1561 (dst++) = context->colors[sprite_src \| 0x10 + CRAM_SIZE*3];
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1562 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1563 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1564 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1565 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1566 for (int i = 0; i < 8; i++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1567 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1568 *(dst++) = context->colors[bgcolor];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1569 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1570 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1571 } else if (context->debug == 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1572 for (int i = 0; i < 8; i++)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1573 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1574 (dst++) = context->colors[CRAM_SIZE3 + col];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1575 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1576 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1577 uint32_t cell = (line / 8) * 32 + col;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1578 uint32_t address = cell * 32 + (line % 8) * 4;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1579 uint32_t m4_address = mode4_address_map[address & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1580 uint32_t pixel = planar_to_chunky[context->vdpmem[m4_address]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1581 pixel \|= planar_to_chunky[context->vdpmem[m4_address + 1]];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1582 m4_address = mode4_address_map[(address + 2) & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1583 pixel \|= planar_to_chunky[context->vdpmem[m4_address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1584 pixel \|= planar_to_chunky[context->vdpmem[m4_address + 1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1585 if (context->debug_pal < 2) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1586 for (int i = 28; i >= 0; i -= 4)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1587 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1588 (dst++) = context->colors[CRAM_SIZE3 \| (context->debug_pal << 4) \| (pixel >> i & 0xF)];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1589 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1590 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1591 for (int i = 28; i >= 0; i -= 4)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1592 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1593 uint8_t value = (pixel >> i & 0xF) * 17;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1594 if (context->debug_pal == 3) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1595 value = 255 - value;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1596 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1597 *(dst++) = render_map_color(value, value, value);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1598 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1599 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1600 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1601 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1602
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1603 static uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19};
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1604
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1605 static void vdp_advance_line(vdp_context *context)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1606 {
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1607 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1608 static uint32_t last_line = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1609 if (last_line != 0xFFFFFFFF) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1610 uint32_t diff = context->cycles - last_line;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1611 if (diff != MCLKS_LINE) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1612 printf("Line %d took %d cycles\n", context->vcounter, diff);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1613 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1614 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1615 last_line = context->cycles;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1616 #endif
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1617 context->vcounter++;
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1618
1156 b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1619 uint8_t is_mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1620 if (is_mode_5) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1621 if (context->flags2 & FLAG2_REGION_PAL) {
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1622 if (context->regs[REG_MODE_2] & BIT_PAL) {
1156 b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1623 if (context->vcounter == 0x10B) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1624 context->vcounter = 0x1D2;
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1625 }
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1626 } else if (context->vcounter == 0x103){
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1627 context->vcounter = 0x1CA;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1628 }
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1629 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1630 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1631 if (context->vcounter == 0x100) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1632 context->vcounter = 0x1FA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1633 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1634 } else if (context->vcounter == 0xEB) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1635 context->vcounter = 0x1E5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1636 }
1299 da1ffc4026c4 Fix latching of V32 mode bit Michael Pavone <pavone@retrodev.com> parents: 1290 diff changeset	1637 }
1156 b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1638 } else if (context->vcounter == 0xDB) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	1639 context->vcounter = 0x1D5;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1640 }
1273 6dedaa645843 Fix graphical corruption and sprite flickering introduced into some games by the last change for horizontal border support Michael Pavone <pavone@retrodev.com> parents: 1272 diff changeset	1641 context->vcounter &= 0x1FF;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1642 if (context->state == PREPARING) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1643 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1644 }
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1645
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1646 if (context->state != ACTIVE) {
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1647 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1648 } else if (context->hint_counter) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1649 context->hint_counter--;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1650 } else {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1651 context->flags2 \|= FLAG2_HINT_PENDING;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1652 context->pending_hint_start = context->cycles;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1653 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1654 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1655 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1656
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1657 static void advance_output_line(vdp_context *context)
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1658 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1659 if (headless) {
1168 fa73a77ddf92 Fix benchmark mode Michael Pavone <pavone@retrodev.com> parents: 1167 diff changeset	1660 if (context->vcounter == context->inactive_start) {
fa73a77ddf92 Fix benchmark mode Michael Pavone <pavone@retrodev.com> parents: 1167 diff changeset	1661 context->frame++;
fa73a77ddf92 Fix benchmark mode Michael Pavone <pavone@retrodev.com> parents: 1167 diff changeset	1662 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1663 context->vcounter &= 0x1FF;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1664 } else {
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1665 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1666 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1667 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1668
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1669 if (context->output_lines == lines_max) {
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	1670 render_framebuffer_updated(context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN: FRAMEBUFFER_ODD, context->h40_lines > (context->inactive_start + context->border_top) / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1671 if (context->double_res) {
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1672 context->flags2 ^= FLAG2_EVEN_FIELD;
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1673 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1674 context->fb = render_get_framebuffer(context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN : FRAMEBUFFER_ODD, &context->output_pitch);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1675 context->h40_lines = 0;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1676 context->frame++;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1677 context->output_lines = 0;
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1678 }
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1679 uint32_t output_line;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1680 if (context->vcounter < context->inactive_start + context->border_bot && context->output_lines > 0) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1681 output_line = context->output_lines++;//context->border_top + context->vcounter;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1682 } else if (context->vcounter >= 0x200 - context->border_top) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1683 output_line = context->output_lines++;//context->vcounter - (0x200 - context->border_top);
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1684 } else {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1685 output_line = INVALID_LINE;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1686 }
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1687 context->output = (uint32_t )(((char )context->fb) + context->output_pitch * output_line);
1271 c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1688 #ifdef DEBUG_FB_FILL
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1689 for (int i = 0; i < LINEBUF_SIZE; i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1690 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1691 context->output[i] = 0xFFFF00FF;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1692 }
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1693 #endif
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1694 if (output_line != INVALID_LINE && (context->regs[REG_MODE_4] & BIT_H40)) {
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	1695 context->h40_lines++;
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1696 }
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	1697 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1698 }
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1699
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1700 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; }
924 1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period Michael Pavone <pavone@retrodev.com> parents: 923 diff changeset	1701 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1702
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1703 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1704 case startcyc:\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1705 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1706 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1707 case ((startcyc+1)&0xFF):\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1708 external_slot(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1709 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1710 case ((startcyc+2)&0xFF):\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1711 render_map_1(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1712 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1713 case ((startcyc+3)&0xFF):\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1714 render_map_2(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1715 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1716 case ((startcyc+4)&0xFF):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1717 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1718 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1719 case ((startcyc+5)&0xFF):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1720 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1721 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1722 case ((startcyc+6)&0xFF):\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1723 render_map_3(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1724 CHECK_LIMIT\
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1725 case ((startcyc+7)&0xFF):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1726 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1727 CHECK_LIMIT
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1728
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1729 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1730 case startcyc:\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1731 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1732 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1733 case (startcyc+1):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1734 /* refresh, no don't run dma src */\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1735 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1736 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1737 CHECK_ONLY\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1738 case (startcyc+2):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1739 render_map_1(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1740 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1741 case (startcyc+3):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1742 render_map_2(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1743 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1744 case (startcyc+4):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1745 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1746 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1747 case (startcyc+5):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1748 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1749 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1750 case (startcyc+6):\
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1751 render_map_3(context);\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1752 CHECK_LIMIT\
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1753 case (startcyc+7):\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1754 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1755 CHECK_LIMIT
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1756
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1757 #define COLUMN_RENDER_BLOCK_MODE4(column, startcyc) \
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1758 case startcyc:\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1759 read_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1760 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1761 case ((startcyc+1)&0xFF):\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1762 if (column & 3) {\
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1763 scan_sprite_table_mode4(context);\
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1764 } else {\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1765 external_slot(context);\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1766 }\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1767 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1768 case ((startcyc+2)&0xFF):\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1769 fetch_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1770 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1771 case ((startcyc+3)&0xFF):\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1772 render_map_mode4(context->vcounter, column, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1773 CHECK_LIMIT
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1774
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1775 #define CHECK_LIMIT_HSYNC(slot) \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1776 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1777 if (slot >= HSYNC_SLOT_H40 && slot < HSYNC_END_H40) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1778 context->cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1779 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1780 context->cycles += slot_cycles;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1781 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1782 if (slot == 182) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1783 context->hslot = 229;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1784 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1785 context->hslot++;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1786 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1787 CHECK_ONLY
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	1788
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1789 #define SPRITE_RENDER_H40(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1790 case slot:\
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1791 if ((slot) == BG_START_SLOT + LINEBUF_SIZE/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1792 advance_output_line(context);\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1793 }\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1794 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1795 scan_sprite_table(context->vcounter, context);\
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1796 CHECK_LIMIT_HSYNC(slot)
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 822 diff changeset	1797
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1798 //Note that the line advancement check will fail if BG_START_SLOT is > 6
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1799 //as we're bumping up against the hcounter jump
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1800 #define SPRITE_RENDER_H32(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1801 case slot:\
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1802 if ((slot) == BG_START_SLOT + (256+HORIZ_BORDER)/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1803 advance_output_line(context);\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	1804 }\
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1805 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1806 scan_sprite_table(context->vcounter, context);\
924 1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period Michael Pavone <pavone@retrodev.com> parents: 923 diff changeset	1807 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1808 if (slot == 147) {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1809 context->hslot = 233;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1810 } else {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1811 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1812 }\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1813 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1814 CHECK_ONLY
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1815
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1816 #define MODE4_CHECK_SLOT_LINE(slot) \
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1817 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1818 if ((slot) == 147) {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1819 context->hslot = 233;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1820 } else {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1821 context->hslot++;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1822 }\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1823 context->cycles += slot_cycles;\
1163 b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1824 if ((slot+1) == LINE_CHANGE_MODE4) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1825 vdp_advance_line(context);\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1826 if (context->vcounter == 192) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1827 return;\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1828 }\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases Michael Pavone <pavone@retrodev.com> parents: 1161 diff changeset	1829 }\
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1830 CHECK_ONLY
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1831
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1832 #define CALC_SLOT(slot, increment) ((slot+increment) > 147 && (slot+increment) < 233 ? (slot+increment-148+233): (slot+increment))
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1833
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1834 #define SPRITE_RENDER_H32_MODE4(slot) \
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1835 case slot:\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1836 read_sprite_x_mode4(context);\
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	1837 MODE4_CHECK_SLOT_LINE(slot)\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1838 case CALC_SLOT(slot, 1):\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1839 read_sprite_x_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1840 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot,1))\
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1841 case CALC_SLOT(slot, 2):\
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1842 fetch_sprite_cells_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1843 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 2))\
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1844 case CALC_SLOT(slot, 3):\
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	1845 render_sprite_cells_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1846 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 3))\
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1847 case CALC_SLOT(slot, 4):\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1848 fetch_sprite_cells_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1849 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 4))\
c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1850 case CALC_SLOT(slot, 5):\
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	1851 render_sprite_cells_mode4(context);\
1161 c2210d586950 A bunch of Mode 4 fixes Michael Pavone <pavone@retrodev.com> parents: 1160 diff changeset	1852 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 5))
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1853
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	1854 static void vdp_h40(vdp_context * context, uint32_t target_cycles)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1855 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1856 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1857 uint32_t mask;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1858 uint32_t const slot_cycles = MCLKS_SLOT_H40;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1859 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1860 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1861 for (;;)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1862 {
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1863 case 165:
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1864 if (context->state == PREPARING) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1865 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1866 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1867 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1868 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1869 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1870 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1871 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1872 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1873 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1874 *dst = bg_color;
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1875 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1876 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1877 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1878 }
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1879 CHECK_LIMIT
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1880 case 166:
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1881 if (context->state == PREPARING) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1882 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1883 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1884 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1885 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1886 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1887 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1888 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1889 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1890 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1891 *dst = bg_color;
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1892 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1893 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1894 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1895 }
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1896 CHECK_LIMIT
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1897 //sprite attribute table scan starts
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1898 case 167:
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	1899 if (context->state == PREPARING) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1900 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1901 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1902 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1903 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1904 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1905 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1906 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1907 }
1271 c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1908 for (int i = 0; i < LINEBUF_SIZE - 2 * (context->hslot - BG_START_SLOT); i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1909 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1910 *(dst++) = bg_color;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	1911 }
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	1912 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1913 context->sprite_index = 0x80;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	1914 context->slot_counter = 0;
21 72ce60cb1711 Sprites somewhat less broken Mike Pavone <pavone@retrodev.com> parents: 20 diff changeset	1915 render_sprite_cells( context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1916 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1917 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1918 SPRITE_RENDER_H40(168)
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1919 SPRITE_RENDER_H40(169)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1920 SPRITE_RENDER_H40(170)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1921 SPRITE_RENDER_H40(171)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1922 SPRITE_RENDER_H40(172)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1923 SPRITE_RENDER_H40(173)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1924 SPRITE_RENDER_H40(174)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1925 SPRITE_RENDER_H40(175)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1926 SPRITE_RENDER_H40(176)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1927 SPRITE_RENDER_H40(177)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1928 SPRITE_RENDER_H40(178)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1929 SPRITE_RENDER_H40(179)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1930 SPRITE_RENDER_H40(180)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1931 SPRITE_RENDER_H40(181)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1932 SPRITE_RENDER_H40(182)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1933 SPRITE_RENDER_H40(229)
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1934 //!HSYNC asserted
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1935 SPRITE_RENDER_H40(230)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1936 SPRITE_RENDER_H40(231)
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1937 case 232:
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1938 external_slot(context);
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	1939 CHECK_LIMIT_HSYNC(232)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1940 SPRITE_RENDER_H40(233)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1941 SPRITE_RENDER_H40(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1942 SPRITE_RENDER_H40(235)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1943 SPRITE_RENDER_H40(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1944 SPRITE_RENDER_H40(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1945 SPRITE_RENDER_H40(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1946 SPRITE_RENDER_H40(239)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1947 SPRITE_RENDER_H40(240)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1948 SPRITE_RENDER_H40(241)
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1949 SPRITE_RENDER_H40(242)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1950 SPRITE_RENDER_H40(243)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1951 case 244:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1952 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1953 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1954 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1955 mask \|= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1956 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1957 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1958 mask \|= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1959 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1960 address += (context->vcounter & mask) * 4;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1961 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1962 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1963 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
924 1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period Michael Pavone <pavone@retrodev.com> parents: 923 diff changeset	1964 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1965 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1966 context->cycles += h40_hsync_cycles[14];
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1967 CHECK_ONLY
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1968 //!HSYNC high
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1969 SPRITE_RENDER_H40(245)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1970 SPRITE_RENDER_H40(246)
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1971 SPRITE_RENDER_H40(247)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1972 SPRITE_RENDER_H40(248)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1973 case 249:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1974 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1975 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1976 SPRITE_RENDER_H40(250)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1977 case 251:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1978 render_map_1(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1979 scan_sprite_table(context->vcounter, context);//Just a guess
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	1980 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1981 case 252:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1982 render_map_2(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1983 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1984 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1985 case 253:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1986 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1987 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1988 SPRITE_RENDER_H40(254)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1989 case 255:
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	1990 render_map_3(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1991 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1992 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	1993 case 0:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1994 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	1995 scan_sprite_table(context->vcounter, context);//Just a guess
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	1996 //seems like the sprite table scan fills a shift register
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	1997 //values are FIFO, but unused slots precede used slots
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	1998 //so we set cur_slot to slot_counter and let it wrap around to
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	1999 //the beginning of the list
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	2000 context->cur_slot = context->slot_counter;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2001 context->sprite_draws = MAX_DRAWS;
36 04672c060062 Pass all sprite masking tests Mike Pavone <pavone@retrodev.com> parents: 35 diff changeset	2002 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2003 CHECK_LIMIT
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2004 COLUMN_RENDER_BLOCK(2, 1)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2005 COLUMN_RENDER_BLOCK(4, 9)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2006 COLUMN_RENDER_BLOCK(6, 17)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2007 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2008 COLUMN_RENDER_BLOCK(10, 33)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2009 COLUMN_RENDER_BLOCK(12, 41)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2010 COLUMN_RENDER_BLOCK(14, 49)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2011 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2012 COLUMN_RENDER_BLOCK(18, 65)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2013 COLUMN_RENDER_BLOCK(20, 73)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2014 COLUMN_RENDER_BLOCK(22, 81)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2015 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2016 COLUMN_RENDER_BLOCK(26, 97)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2017 COLUMN_RENDER_BLOCK(28, 105)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2018 COLUMN_RENDER_BLOCK(30, 113)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2019 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2020 COLUMN_RENDER_BLOCK(34, 129)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2021 COLUMN_RENDER_BLOCK(36, 137)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2022 COLUMN_RENDER_BLOCK(38, 145)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2023 COLUMN_RENDER_BLOCK_REFRESH(40, 153)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2024 case 161:
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2025 external_slot(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2026 CHECK_LIMIT
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2027 case 162: {
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2028 external_slot(context);
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2029 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2030 for (int i = LINEBUF_SIZE-BORDER_RIGHT; i < LINEBUF_SIZE; i++)
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2031 {
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2032 context->output[i] = bg_color;
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2033 }
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2034 CHECK_LIMIT
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2035 }
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2036 //sprite render to line buffer starts
1157 d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements Michael Pavone <pavone@retrodev.com> parents: 1156 diff changeset	2037 case 163:
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2038 context->cur_slot = MAX_DRAWS-1;
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2039 memset(context->linebuf, 0, LINEBUF_SIZE);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2040 render_sprite_cells(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2041 CHECK_LIMIT
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2042 case 164:
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2043 render_sprite_cells(context);
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2044 if (context->flags & FLAG_DMA_RUN) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2045 run_dma_src(context, -1);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2046 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2047 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2048 context->cycles += slot_cycles;
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2049 vdp_advance_line(context);
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2050 if (context->vcounter == context->inactive_start) {
922 913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2051 return;
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot Michael Pavone <pavone@retrodev.com> parents: 921 diff changeset	2052 }
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2053 CHECK_ONLY
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2054 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2055 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2056 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2057 context->cycles += slot_cycles;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2058 return;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2059 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2060 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2061
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	2062 static void vdp_h32(vdp_context * context, uint32_t target_cycles)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2063 {
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2064 uint16_t address;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2065 uint32_t mask;
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2066 uint32_t const slot_cycles = MCLKS_SLOT_H32;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2067 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2068 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2069 for (;;)
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2070 {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2071 case 133:
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2072 if (context->state == PREPARING) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2073 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2074 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2075 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2076 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2077 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2078 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2079 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2080 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2081 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2082 *dst = bg_color;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2083 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2084 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2085 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2086 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2087 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2088 case 134:
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2089 if (context->state == PREPARING) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2090 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2091 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2092 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2093 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2094 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2095 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2096 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2097 }
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2098 *(dst++) = bg_color;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2099 *dst = bg_color;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2100 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2101 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2102 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2103 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2104 CHECK_LIMIT
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2105 //sprite attribute table scan starts
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2106 case 135: //FIXME - Here
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2107 if (context->state == PREPARING) {
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2108 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2109 uint32_t *dst;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2110 if (headless) {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2111 dst = context->output;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2112 } else {
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2113 dst = ((uint32_t )(((char )context->fb) + context->output_pitch * (context->border_top - 2)))
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2114 + (context->hslot - BG_START_SLOT) * 2;
9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2115 }
1271 c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	2116 for (int i = 0; i < (256+HORIZ_BORDER) - 2 * (context->hslot - BG_START_SLOT); i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	2117 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	2118 *(dst++) = bg_color;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes Michael Pavone <pavone@retrodev.com> parents: 1270 diff changeset	2119 }
1185 9de9d2c6ebe5 Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished. Michael Pavone <pavone@retrodev.com> parents: 1183 diff changeset	2120 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2121 context->sprite_index = 0x80;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	2122 context->slot_counter = 0;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2123 render_sprite_cells( context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2124 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2125 CHECK_LIMIT
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2126 SPRITE_RENDER_H32(136)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2127 SPRITE_RENDER_H32(137)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2128 SPRITE_RENDER_H32(138)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2129 SPRITE_RENDER_H32(139)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2130 SPRITE_RENDER_H32(140)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2131 SPRITE_RENDER_H32(141)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2132 SPRITE_RENDER_H32(142)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2133 SPRITE_RENDER_H32(143)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2134 SPRITE_RENDER_H32(144)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2135 case 145:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2136 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2137 CHECK_LIMIT
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2138 SPRITE_RENDER_H32(146)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2139 SPRITE_RENDER_H32(147)
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2140 SPRITE_RENDER_H32(233)
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2141 SPRITE_RENDER_H32(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2142 SPRITE_RENDER_H32(235)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2143 //HSYNC start
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2144 SPRITE_RENDER_H32(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2145 SPRITE_RENDER_H32(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2146 SPRITE_RENDER_H32(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2147 SPRITE_RENDER_H32(239)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2148 SPRITE_RENDER_H32(240)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2149 SPRITE_RENDER_H32(241)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2150 SPRITE_RENDER_H32(242)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2151 case 243:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2152 external_slot(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2153 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2154 case 244:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2155 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2156 mask = 0;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2157 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2158 mask \|= 0xF8;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2159 }
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2160 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2161 mask \|= 0x7;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2162 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2163 address += (context->vcounter & mask) * 4;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2164 context->hscroll_a = context->vdpmem[address] << 8 \| context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2165 context->hscroll_b = context->vdpmem[address+2] << 8 \| context->vdpmem[address+3];
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2166 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2167 CHECK_LIMIT
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2168 SPRITE_RENDER_H32(245)
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2169 SPRITE_RENDER_H32(246)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2170 SPRITE_RENDER_H32(247)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2171 SPRITE_RENDER_H32(248)
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2172 //!HSYNC high
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2173 case 249:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2174 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2175 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2176 SPRITE_RENDER_H32(250)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2177 case 251:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2178 render_map_1(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2179 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2180 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2181 case 252:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2182 render_map_2(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2183 scan_sprite_table(context->vcounter, context);//Just a guess
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2184 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2185 case 253:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2186 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2187 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2188 case 254:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2189 render_sprite_cells(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2190 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2191 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2192 case 255:
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2193 render_map_3(context);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2194 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2195 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2196 case 0:
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2197 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2198 scan_sprite_table(context->vcounter, context);//Just a guess
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2199 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2200 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2201 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	2202 context->cur_slot = context->slot_counter;
37 cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2203 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support Mike Pavone <pavone@retrodev.com> parents: 36 diff changeset	2204 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2205 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2206 COLUMN_RENDER_BLOCK(2, 1)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2207 COLUMN_RENDER_BLOCK(4, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2208 COLUMN_RENDER_BLOCK(6, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2209 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2210 COLUMN_RENDER_BLOCK(10, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2211 COLUMN_RENDER_BLOCK(12, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2212 COLUMN_RENDER_BLOCK(14, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2213 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2214 COLUMN_RENDER_BLOCK(18, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2215 COLUMN_RENDER_BLOCK(20, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2216 COLUMN_RENDER_BLOCK(22, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2217 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2218 COLUMN_RENDER_BLOCK(26, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2219 COLUMN_RENDER_BLOCK(28, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2220 COLUMN_RENDER_BLOCK(30, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2221 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2222 case 129:
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2223 external_slot(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2224 CHECK_LIMIT
1269 ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2225 case 130: {
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2226 external_slot(context);
1269 ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2227 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2228 for (int i = 256+BORDER_LEFT; i < 256+HORIZ_BORDER; i++)
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2229 {
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2230 context->output[i] = bg_color;
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2231 }
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2232 CHECK_LIMIT
1269 ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition Michael Pavone <pavone@retrodev.com> parents: 1267 diff changeset	2233 }
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2234 //sprite render to line buffer starts
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2235 case 131:
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2236 context->cur_slot = MAX_DRAWS_H32-1;
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2237 memset(context->linebuf, 0, LINEBUF_SIZE);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2238 render_sprite_cells(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2239 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2240 case 132:
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2241 render_sprite_cells(context);
1173 d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2242 if (context->flags & FLAG_DMA_RUN) {
d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2243 run_dma_src(context, -1);
d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2244 }
d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2245 context->hslot++;
d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2246 context->cycles += slot_cycles;
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2247 vdp_advance_line(context);
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2248 if (context->vcounter == context->inactive_start) {
923 8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2249 return;
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40 Michael Pavone <pavone@retrodev.com> parents: 922 diff changeset	2250 }
1173 d0f67c59b756 Fix H32 inconsistency Michael Pavone <pavone@retrodev.com> parents: 1172 diff changeset	2251 CHECK_ONLY
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2252 }
822 ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2253 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2254 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others Michael Pavone <pavone@retrodev.com> parents: 771 diff changeset	2255 context->cycles += MCLKS_SLOT_H32;
503 eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	2256 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	2257 }
eee6be465c47 Small optimization for H40 mode Mike Pavone <pavone@retrodev.com> parents: 499 diff changeset	2258
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2259 static void vdp_h32_mode4(vdp_context * context, uint32_t target_cycles)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2260 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2261 uint16_t address;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2262 uint32_t mask;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2263 uint32_t const slot_cycles = MCLKS_SLOT_H32;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2264 switch(context->hslot)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2265 {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2266 for (;;)
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2267 {
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2268 //sprite rendering starts
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2269 SPRITE_RENDER_H32_MODE4(137)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2270 SPRITE_RENDER_H32_MODE4(143)
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2271 case 234:
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2272 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2273 CHECK_LIMIT
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2274 case 235:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2275 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2276 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2277 //!HSYNC low
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2278 case 236:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2279 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2280 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2281 case 237:
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2282 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2283 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2284 case 238:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2285 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2286 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2287 SPRITE_RENDER_H32_MODE4(239)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2288 SPRITE_RENDER_H32_MODE4(245)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2289 case 251:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2290 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2291 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2292 case 252:
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2293 external_slot(context);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2294 if (context->regs[REG_MODE_1] & BIT_HSCRL_LOCK && context->vcounter < 16) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2295 context->hscroll_a = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2296 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2297 context->hscroll_a = context->regs[REG_X_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2298 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2299 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2300 case 253:
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2301 context->sprite_index = 0;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2302 context->slot_counter = MAX_DRAWS_H32_MODE4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2303 scan_sprite_table_mode4(context);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2304 CHECK_LIMIT
1135 8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2305 case 254:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2306 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2307 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2308 case 255:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2309 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2310 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2311 case 0:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2312 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2313 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2314 case 1:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures Michael Pavone <pavone@retrodev.com> parents: 1134 diff changeset	2315 scan_sprite_table_mode4(context);
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2316 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2317 case 2:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2318 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2319 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2320 case 3:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2321 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2322 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2323 case 4:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2324 scan_sprite_table_mode4(context);
1121 1913f9c28003 Less broken Mode 4 implementation Michael Pavone <pavone@retrodev.com> parents: 1120 diff changeset	2325 context->buf_a_off = 8;
1913f9c28003 Less broken Mode 4 implementation Michael Pavone <pavone@retrodev.com> parents: 1120 diff changeset	2326 memset(context->tmp_buf_a, 0, 8);
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2327 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2328 COLUMN_RENDER_BLOCK_MODE4(0, 5)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2329 COLUMN_RENDER_BLOCK_MODE4(1, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2330 COLUMN_RENDER_BLOCK_MODE4(2, 13)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2331 COLUMN_RENDER_BLOCK_MODE4(3, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2332 COLUMN_RENDER_BLOCK_MODE4(4, 21)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2333 COLUMN_RENDER_BLOCK_MODE4(5, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2334 COLUMN_RENDER_BLOCK_MODE4(6, 29)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2335 COLUMN_RENDER_BLOCK_MODE4(7, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2336 COLUMN_RENDER_BLOCK_MODE4(8, 37)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2337 COLUMN_RENDER_BLOCK_MODE4(9, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2338 COLUMN_RENDER_BLOCK_MODE4(10, 45)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2339 COLUMN_RENDER_BLOCK_MODE4(11, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2340 COLUMN_RENDER_BLOCK_MODE4(12, 53)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2341 COLUMN_RENDER_BLOCK_MODE4(13, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2342 COLUMN_RENDER_BLOCK_MODE4(14, 61)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2343 COLUMN_RENDER_BLOCK_MODE4(15, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2344 COLUMN_RENDER_BLOCK_MODE4(16, 69)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2345 COLUMN_RENDER_BLOCK_MODE4(17, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2346 COLUMN_RENDER_BLOCK_MODE4(18, 77)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2347 COLUMN_RENDER_BLOCK_MODE4(19, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2348 COLUMN_RENDER_BLOCK_MODE4(20, 85)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2349 COLUMN_RENDER_BLOCK_MODE4(21, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2350 COLUMN_RENDER_BLOCK_MODE4(22, 93)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2351 COLUMN_RENDER_BLOCK_MODE4(23, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2352 COLUMN_RENDER_BLOCK_MODE4(24, 101)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2353 COLUMN_RENDER_BLOCK_MODE4(25, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2354 COLUMN_RENDER_BLOCK_MODE4(26, 109)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2355 COLUMN_RENDER_BLOCK_MODE4(27, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2356 COLUMN_RENDER_BLOCK_MODE4(28, 117)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2357 COLUMN_RENDER_BLOCK_MODE4(29, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2358 COLUMN_RENDER_BLOCK_MODE4(30, 125)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2359 COLUMN_RENDER_BLOCK_MODE4(31, 129)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2360 case 133:
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2361 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2362 CHECK_LIMIT
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2363 case 134:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2364 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2365 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2366 case 135:
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2367 external_slot(context);
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2368 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2369 case 136:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2370 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2371 //set things up for sprite rendering in the next slot
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2372 memset(context->linebuf, 0, LINEBUF_SIZE);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2373 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2374 context->sprite_draws = MAX_DRAWS_H32_MODE4;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2375 CHECK_LIMIT
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2376 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2377 default:
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2378 context->hslot++;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2379 context->cycles += MCLKS_SLOT_H32;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2380 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2381 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2382
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2383 static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2384 {
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2385 uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2386 uint8_t index_reset_value, max_draws, max_sprites;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2387 uint16_t vint_line, active_line;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2388 uint32_t bg_color;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2389
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2390 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2391 if (is_h40) {
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	2392 buf_clear_slot = 163;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	2393 index_reset_slot = 167;
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2394 bg_end_slot = BG_START_SLOT + LINEBUF_SIZE/2;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2395 max_draws = MAX_DRAWS-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2396 max_sprites = MAX_SPRITES_LINE;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2397 index_reset_value = 0x80;
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2398 vint_slot = VINT_SLOT_H40;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2399 line_change = LINE_CHANGE_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2400 jump_start = 182;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2401 jump_dest = 229;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2402 } else {
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2403 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2404 max_draws = MAX_DRAWS_H32-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2405 max_sprites = MAX_SPRITES_LINE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2406 buf_clear_slot = 128;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2407 index_reset_slot = 132;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2408 index_reset_value = 0x80;
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	2409 vint_slot = VINT_SLOT_H32;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2410 line_change = LINE_CHANGE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2411 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2412 jump_dest = 233;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2413 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2414 vint_line = context->inactive_start;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2415 active_line = 0x1FF;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2416 } else {
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2417 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2418 max_draws = MAX_DRAWS_H32_MODE4;
1278 34d3cb05014d Fix VDP buffer overrun that was causing sprite flickering in some games Michael Pavone <pavone@retrodev.com> parents: 1273 diff changeset	2419 max_sprites = 8;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2420 buf_clear_slot = 136;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2421 index_reset_slot = 253;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2422 index_reset_value = 0;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2423 vint_line = context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2424 vint_slot = VINT_SLOT_MODE4;
1177 67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency Michael Pavone <pavone@retrodev.com> parents: 1175 diff changeset	2425 line_change = LINE_CHANGE_MODE4;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2426 bg_color = render_map_color(0, 0, 0);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2427 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2428 jump_dest = 233;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2429 if (context->regs[REG_MODE_1] & BIT_MODE_4) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2430 //FIXME: This is actually 0x1FF like in Mode 5
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2431 active_line = 0;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2432 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2433 //never active unless either mode 4 or mode 5 is turned on
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2434 active_line = 0x200;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2435 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2436 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2437 uint32_t *dst = (
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2438 context->vcounter < context->inactive_start + context->border_bot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2439 \|\| context->vcounter > 0x200 - context->border_top
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2440 ) && context->hslot >= BG_START_SLOT && context->hslot < bg_end_slot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2441 ? context->output + 2 * (context->hslot - BG_START_SLOT)
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2442 : NULL;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2443
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2444 while(context->cycles < target_cycles)
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2445 {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2446 if (context->hslot == BG_START_SLOT && (
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2447 context->vcounter < context->inactive_start + context->border_bot
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2448 \|\| context->vcounter > 0x200 - context->border_top
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2449 )) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2450 dst = context->output + (context->hslot - BG_START_SLOT) * 2;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2451 } else if (context->hslot == bg_end_slot) {
1272 be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame Michael Pavone <pavone@retrodev.com> parents: 1271 diff changeset	2452 advance_output_line(context);
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2453 dst = NULL;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2454 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2455
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2456 if (context->hslot == buf_clear_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2457 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2458 context->cur_slot = max_draws;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2459 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2460 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2461 context->sprite_draws = MAX_DRAWS_H32_MODE4;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2462 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2463 memset(context->linebuf, 0, LINEBUF_SIZE);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2464 } else if (context->hslot == index_reset_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2465 context->sprite_index = index_reset_value;
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	2466 context->slot_counter = mode_5 ? 0 : max_sprites;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2467 } else if (context->vcounter == vint_line && context->hslot == vint_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2468 context->flags2 \|= FLAG2_VINT_PENDING;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2469 context->pending_vint_start = context->cycles;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2470 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2471
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2472 if (dst) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2473 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2474 bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2475 } else if (context->regs[REG_MODE_1] & BIT_MODE_4) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2476 bg_color = context->colors[CRAM_SIZE * 3 + 0x10 + (context->regs[REG_BG_COLOR] & 0xF)];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2477 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2478 *(dst++) = bg_color;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2479 *(dst++) = bg_color;
1267 3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2480 if (context->hslot == (bg_end_slot-1)) {
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2481 *(dst++) = bg_color;
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill Michael Pavone <pavone@retrodev.com> parents: 1191 diff changeset	2482 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2483 }
1183 8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2484
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2485 if (!is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2486 external_slot(context);
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2487 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2488 run_dma_src(context, context->hslot);
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2489 }
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2490 }
8d8c71ebbbce CRAM contention artifact emulation Michael Pavone <pavone@retrodev.com> parents: 1180 diff changeset	2491
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2492 if (is_h40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2493 if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2494 context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2495 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2496 context->cycles += MCLKS_SLOT_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2497 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2498 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2499 context->cycles += MCLKS_SLOT_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2500 }
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2501 if (context->hslot == jump_start) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2502 context->hslot = jump_dest;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2503 } else {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2504 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	2505 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2506 if (context->hslot == line_change) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2507 vdp_advance_line(context);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2508 if (context->vcounter == active_line) {
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2509 context->state = PREPARING;
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2510 return;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2511 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2512 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2513 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2514 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2515
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2516 void vdp_run_context(vdp_context * context, uint32_t target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2517 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2518 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2519 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2520 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2521 {
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2522 if (context->state == ACTIVE && context->vcounter == context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2523 context->state = INACTIVE;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2524 }
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2525
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2526 if (is_active(context)) {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2527 if (mode_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2528 if (is_h40) {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2529 vdp_h40(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2530 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2531 vdp_h32(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2532 }
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	2533 } else {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2534 vdp_h32_mode4(context, target_cycles);
330 57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	2535 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode Mike Pavone <pavone@retrodev.com> parents: 329 diff changeset	2536 } else {
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	2537 vdp_inactive(context, target_cycles, is_h40, mode_5);
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2538 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2539 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2540 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2541
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2542 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2543 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2544 uint32_t old_frame = context->frame;
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2545 while (context->frame == old_frame) {
1179 1271b240b9c2 Fix vdp_run_to_vblank Michael Pavone <pavone@retrodev.com> parents: 1178 diff changeset	2546 vdp_run_context(context, context->cycles + MCLKS_LINE);
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2547 }
20 f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2548 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2549 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer Mike Pavone <pavone@retrodev.com> parents: diff changeset	2550
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2551 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2552 {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2553 for(;;) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2554 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2555 if (!dmalen) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2556 dmalen = 0x10000;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2557 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2558 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20);
1321 0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1320 diff changeset	2559 if (
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1320 diff changeset	2560 (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1320 diff changeset	2561 \|\| (((context->cd & 0xF) == VRAM_WRITE) && !(context->regs[REG_MODE_2] & BIT_128K_VRAM))) {
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2562 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2563 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
1321 0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1320 diff changeset	2564 //unless 128KB mode is enabled
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2565 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2566 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2567 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2568 if (target_cycles < min_dma_complete) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2569 vdp_run_context(context, target_cycles);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2570 return;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2571 } else {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2572 vdp_run_context(context, min_dma_complete);
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2573 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2574 return;
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2575 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2576 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2577 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2578 }
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2579
1154 c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2580 static uint16_t get_ext_vcounter(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2581 {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2582 uint16_t line= context->vcounter & 0xFF;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2583 if (context->double_res) {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2584 line <<= 1;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2585 if (line & 0x100) {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2586 line \|= 1;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2587 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2588 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2589 return line << 8;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2590 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2591
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2592 void vdp_latch_hv(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2593 {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2594 context->hv_latch = context->hslot \| get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2595 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2596
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2597 uint16_t vdp_hv_counter_read(vdp_context * context)
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2598 {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2599 if ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_1] & BIT_HVC_LATCH)) {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2600 return context->hv_latch;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2601 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2602 uint16_t hv;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2603 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2604 hv = context->hslot;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2605 } else {
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2606 hv = context->hv_latch & 0xFF;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2607 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2608 hv \|= get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2609
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2610 return hv;
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2611 }
c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2612
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2613 int vdp_control_port_write(vdp_context * context, uint16_t value)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2614 {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2615 //printf("control port write: %X at %d\n", value, context->cycles);
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2616 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2617 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2618 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2619 if (context->flags & FLAG_PENDING) {
1318 bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support Michael Pavone <pavone@retrodev.com> parents: 1315 diff changeset	2620 context->address = (context->address & 0x3FFF) \| (value << 14 & 0x1C000);
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2621 //It seems like the DMA enable bit doesn't so much enable DMA so much
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2622 //as it enables changing CD5 from control port writes
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2623 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2624 context->cd = (context->cd & preserve) \| ((value >> 2) & ~preserve & 0xFF);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2625 context->flags &= ~FLAG_PENDING;
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2626 //Should these be taken care of here or after the first write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2627 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2628 context->flags2 &= ~FLAG2_READ_PENDING;
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	2629 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2630 if (context->cd & 0x20) {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2631 //
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2632 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2633 //DMA copy or 68K -> VDP, transfer starts immediately
131 8fc8e46be691 Fix bug that was causing DMA fills to lock up under certain circumstances Mike Pavone <pavone@retrodev.com> parents: 109 diff changeset	2634 context->dma_cd = context->cd;
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2635 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) \| context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot);
1191 8dc50e50ced6 Remove accidentally committed debug logging Michael Pavone <pavone@retrodev.com> parents: 1189 diff changeset	2636 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
8dc50e50ced6 Remove accidentally committed debug logging Michael Pavone <pavone@retrodev.com> parents: 1189 diff changeset	2637 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) \| (context->regs[REG_DMASRC_M] << 9) \| (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 \| context->regs[REG_DMALEN_L]);
1289 6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2638 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2639 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2640 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2641 //sticking with 3 slots for now until I can do some more captures
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM Michael Pavone <pavone@retrodev.com> parents: 1285 diff changeset	2642 vdp_run_context(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5));
1285 76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation Michael Pavone <pavone@retrodev.com> parents: 1278 diff changeset	2643 context->flags \|= FLAG_DMA_RUN;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2644 return 1;
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2645 } else {
1285 76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation Michael Pavone <pavone@retrodev.com> parents: 1278 diff changeset	2646 context->flags \|= FLAG_DMA_RUN;
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2647 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) \| context->regs[REG_DMASRC_L]);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2648 }
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	2649 } else {
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	2650 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2651 }
63 a6dd5b7a971b Add FPS counter to console output Mike Pavone <pavone@retrodev.com> parents: 58 diff changeset	2652 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2653 } else {
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2654 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2655 context->address = (context->address &0xC000) \| (value & 0x3FFF);
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2656 context->cd = (context->cd & 0x3C) \| (value >> 14);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2657 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2658 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2659 uint8_t reg = (value >> 8) & 0x1F;
1123 d5412f76accc Fix inactive start line for Mode 4 in vdp_next_hint. Fix an off by one error in the range of registers allowed to be written in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1122 diff changeset	2660 if (reg < (mode_5 ? VDP_REGS : 0xB)) {
453 b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements. Mike Pavone <pavone@retrodev.com> parents: 452 diff changeset	2661 //printf("register %d set to %X\n", reg, value & 0xFF);
480 0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	2662 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) {
1154 c83ec07ddbac Implemented Mode 4 H conter latching Michael Pavone <pavone@retrodev.com> parents: 1153 diff changeset	2663 vdp_latch_hv(context);
480 0737953132ad Implement HV counter latch Mike Pavone <pavone@retrodev.com> parents: 479 diff changeset	2664 }
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	2665 if (reg == REG_BG_COLOR) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	2666 value &= 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 503 diff changeset	2667 }
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	2668 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2669 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame);
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	2670 }*/
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2671 context->regs[reg] = value;
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2672 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2673 context->double_res = (value & (BIT_INTERLACE \| BIT_DOUBLE_RES)) == (BIT_INTERLACE \| BIT_DOUBLE_RES);
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	2674 if (!context->double_res) {
1106 cacbd3f18f03 Fix field flag handling bug introduced with VDP/render interface cleanup Michael Pavone <pavone@retrodev.com> parents: 1103 diff changeset	2675 context->flags2 &= ~FLAG2_EVEN_FIELD;
415 8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode. Mike Pavone <pavone@retrodev.com> parents: 414 diff changeset	2676 }
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2677 }
1335 26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2. Michael Pavone <pavone@retrodev.com> parents: 1334 diff changeset	2678 if (reg == REG_MODE_1 \|\| reg == REG_MODE_2 \|\| reg == REG_MODE_4) {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2679 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	2680 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2681 }
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2682 } else if (mode_5) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2683 context->flags \|= FLAG_PENDING;
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2684 //Should these be taken care of here or after the second write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2685 //context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2686 //context->flags2 &= ~FLAG2_READ_PENDING;
1120 e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2687 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2688 context->flags &= ~FLAG_READ_FETCHED;
e9369d6f0101 Somewhat broken implementation of Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1117 diff changeset	2689 context->flags2 &= ~FLAG2_READ_PENDING;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2690 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2691 }
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2692 return 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2693 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2694
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2695 void vdp_control_port_write_pbc(vdp_context *context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2696 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2697 if (context->flags2 & FLAG2_BYTE_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2698 uint16_t full_val = value << 8 \| context->pending_byte;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2699 context->flags2 &= ~FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2700 //TODO: Deal with fact that Vbus->VDP DMA doesn't do anything in PBC mode
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2701 vdp_control_port_write(context, full_val);
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2702 if (context->cd == VRAM_READ) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2703 context->cd = VRAM_READ8;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2704 }
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2705 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2706 context->pending_byte = value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2707 context->flags2 \|= FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2708 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2709 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2710
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2711 int vdp_data_port_write(vdp_context * context, uint16_t value)
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2712 {
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2713 //printf("data port write: %X at %d\n", value, context->cycles);
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2714 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2715 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2716 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2717 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2718 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2719 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2720 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2721 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2722 }
109 004dd46e0a97 COmment out fifo full debug printf Mike Pavone <pavone@retrodev.com> parents: 108 diff changeset	2723 /*if (context->fifo_cur == context->fifo_end) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2724 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109 004dd46e0a97 COmment out fifo full debug printf Mike Pavone <pavone@retrodev.com> parents: 108 diff changeset	2725 }*/
460 788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2726 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2727 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2728 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2729 while (context->fifo_write == context->fifo_read) {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2730 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2731 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2732 fifo_entry * cur = context->fifo + context->fifo_write;
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2733 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2734 cur->address = context->address;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2735 cur->value = value;
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2736 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2737 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2738 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2739 cur->cd = (context->cd & 2) \| 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2740 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2741 cur->partial = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2742 if (context->fifo_read < 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2743 context->fifo_read = context->fifo_write;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2744 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2745 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2746 increment_address(context);
149 139e5dcd6aa3 Make writes to control and data port block when DMA is in progress Mike Pavone <pavone@retrodev.com> parents: 143 diff changeset	2747 return 0;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2748 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2749
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2750 void vdp_data_port_write_pbc(vdp_context * context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2751 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2752 if (context->flags & FLAG_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2753 context->flags &= ~FLAG_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2754 //Should these be cleared here?
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2755 context->flags &= ~FLAG_READ_FETCHED;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2756 context->flags2 &= ~FLAG2_READ_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2757 }
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2758 context->flags2 &= ~FLAG2_BYTE_PENDING;
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2759 /*if (context->fifo_cur == context->fifo_end) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2760 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2761 }*/
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2762 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2763 context->flags &= ~FLAG_DMA_RUN;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2764 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2765 while (context->fifo_write == context->fifo_read) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2766 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2767 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2768 fifo_entry * cur = context->fifo + context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2769 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2770 cur->address = context->address;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2771 cur->value = value;
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2772 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2773 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2774 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2775 cur->cd = (context->cd & 2) \| 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2776 }
1333 69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2 Michael Pavone <pavone@retrodev.com> parents: 1331 diff changeset	2777 cur->partial = 3;
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2778 if (context->fifo_read < 0) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2779 context->fifo_read = context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2780 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2781 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2782 increment_address(context);
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2783 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2784
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2785 void vdp_test_port_write(vdp_context * context, uint16_t value)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2786 {
1318 bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support Michael Pavone <pavone@retrodev.com> parents: 1315 diff changeset	2787 context->test_port = value;
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2788 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2789
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2790 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2791 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2792 context->flags &= ~FLAG_PENDING;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2793 context->flags2 &= ~FLAG2_BYTE_PENDING;
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2794 //Bits 15-10 are not fixed like Charles MacDonald's doc suggests, but instead open bus values that reflect 68K prefetch
1117 928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful. Michael Pavone <pavone@retrodev.com> parents: 1106 diff changeset	2795 uint16_t value = context->system->get_open_bus_value(context->system) & 0xFC00;
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2796 if (context->fifo_read < 0) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2797 value \|= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2798 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2799 if (context->fifo_read == context->fifo_write) {
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2800 value \|= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2801 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2802 if (context->flags2 & FLAG2_VINT_PENDING) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2803 value \|= 0x80;
36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2804 }
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2805 if (context->flags & FLAG_DOT_OFLOW) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2806 value \|= 0x40;
1156 b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4 Michael Pavone <pavone@retrodev.com> parents: 1155 diff changeset	2807 context->flags &= ~FLAG_DOT_OFLOW;
494 8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2808 }
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2809 if (context->flags2 & FLAG2_SPRITE_COLLIDE) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2810 value \|= 0x20;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2811 context->flags2 &= ~FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags Mike Pavone <pavone@retrodev.com> parents: 481 diff changeset	2812 }
1077 1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode. Michael Pavone <pavone@retrodev.com> parents: 1076 diff changeset	2813 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && !(context->flags2 & FLAG2_EVEN_FIELD)) {
413 36fbbced25c2 Initial work on interlace Mike Pavone <pavone@retrodev.com> parents: 337 diff changeset	2814 value \|= 0x10;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2815 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2816 uint32_t slot = context->hslot;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2817 if (!is_active(context)) {
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	2818 value \|= 0x8;
789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	2819 }
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2820 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2821 if (slot < HBLANK_END_H40 \|\| slot > HBLANK_START_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2822 value \|= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2823 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2824 } else {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2825 if (slot < HBLANK_END_H32 \|\| slot > HBLANK_START_H32) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2826 value \|= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2827 }
318 789f2f5f2277 Implement hblank flag in status register Mike Pavone <pavone@retrodev.com> parents: 317 diff changeset	2828 }
983 14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	2829 if (context->cd & 0x20) {
141 576f55711d8d Fix DMA in progress flag in VDP status register Mike Pavone <pavone@retrodev.com> parents: 138 diff changeset	2830 value \|= 0x2;
75 108e587165c0 Implement DMA (untested) Mike Pavone <pavone@retrodev.com> parents: 65 diff changeset	2831 }
714 e29bc2918f69 Fix VDP status register PAL bit based on observations of the Titan Overdrive demo Michael Pavone <pavone@retrodev.com> parents: 711 diff changeset	2832 if (context->flags2 & FLAG2_REGION_PAL) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2833 value \|= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	2834 }
459 c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test Mike Pavone <pavone@retrodev.com> parents: 454 diff changeset	2835 //printf("status read at cycle %d returned %X\n", context->cycles, value);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2836 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2837 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2838
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2839 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2840 {
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2841 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2842 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2843 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2844 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2845 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2846 }
138 aa3e1bb338c9 Fix VDP reads Mike Pavone <pavone@retrodev.com> parents: 137 diff changeset	2847 if (context->cd & 1) {
991 f9ee6f746cb4 Properly emulate machine freeze when reading from VDP while configured for writes Michael Pavone <pavone@retrodev.com> parents: 984 diff changeset	2848 warning("Read from VDP data port while writes are configured, CPU is now frozen. VDP Address: %X, CD: %X\n", context->address, context->cd);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2849 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2850 while (!(context->flags & FLAG_READ_FETCHED)) {
622 b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though Michael Pavone <pavone@retrodev.com> parents: 621 diff changeset	2851 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2852 }
980 928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2853 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM Michael Pavone <pavone@retrodev.com> parents: 953 diff changeset	2854 return context->prefetch;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2855 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 43 diff changeset	2856
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2857 uint8_t vdp_data_port_read_pbc(vdp_context * context)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2858 {
1153 2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2859 context->flags &= ~(FLAG_PENDING \| FLAG_READ_FETCHED);
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1152 diff changeset	2860 context->flags2 &= ~FLAG2_BYTE_PENDING;
1151 681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode Michael Pavone <pavone@retrodev.com> parents: 1150 diff changeset	2861
1152 ddbb61be6119 Fix to pass a couple more tests in VDPTEST.sms Michael Pavone <pavone@retrodev.com> parents: 1151 diff changeset	2862 context->cd = VRAM_READ8;
1149 6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2863 return context->prefetch;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2864 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions Michael Pavone <pavone@retrodev.com> parents: 1138 diff changeset	2865
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2866 uint16_t vdp_test_port_read(vdp_context * context)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2867 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2868 //TODO: Find out what actually gets returned here
1318 bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support Michael Pavone <pavone@retrodev.com> parents: 1315 diff changeset	2869 return context->test_port;
470 541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2870 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM. Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	2871
65 aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2872 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2873 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2874 context->cycles -= deduction;
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2875 if (context->pending_vint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2876 context->pending_vint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2877 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2878 context->pending_vint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2879 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2880 if (context->pending_hint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2881 context->pending_hint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2882 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2883 context->pending_hint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2884 }
471 f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2885 if (context->fifo_read >= 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2886 int32_t idx = context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2887 do {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2888 if (context->fifo[idx].cycle >= deduction) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2889 context->fifo[idx].cycle -= deduction;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2890 } else {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2891 context->fifo[idx].cycle = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2892 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2893 idx = (idx+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly Mike Pavone <pavone@retrodev.com> parents: 470 diff changeset	2894 } while(idx != context->fifo_write);
65 aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2895 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2896 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame. Mike Pavone <pavone@retrodev.com> parents: 63 diff changeset	2897
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	2898 static uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context)
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2899 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2900 if (context->hslot < 183) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2901 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2902 } else if (context->hslot < HSYNC_END_H40) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2903 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2904 uint32_t hsync = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2905 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2906 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2907 hsync += h40_hsync_cycles[i];
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2908 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2909 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2910 return before_hsync + hsync + after_hsync;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2911 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2912 return (256-context->hslot) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2913 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2914 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2915
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	2916 static uint32_t vdp_cycles_next_line(vdp_context * context)
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2917 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2918 if (context->regs[REG_MODE_4] & BIT_H40) {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2919 //TODO: Handle "illegal" Mode 4/H40 combo
647 5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events Michael Pavone <pavone@retrodev.com> parents: 629 diff changeset	2920 if (context->hslot < LINE_CHANGE_H40) {
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 680 diff changeset	2921 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2922 } else {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	2923 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2924 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2925 } else {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2926 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2927 if (context->hslot < LINE_CHANGE_H32) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2928 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2929 } else if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2930 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2931 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2932 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2933 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2934 } else {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2935 if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2936 return (148 - context->hslot + LINE_CHANGE_MODE4 - 233) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2937 } else if (context->hslot < LINE_CHANGE_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2938 return (LINE_CHANGE_MODE4 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2939 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2940 return MCLKS_LINE - (context->hslot - LINE_CHANGE_MODE4) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	2941 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2942 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2943 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2944 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2945
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2946 static void get_jump_params(vdp_context context, uint32_t jump_start, uint32_t *jump_dst)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2947 {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2948 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2949 if (context->flags2 & FLAG2_REGION_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2950 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2951 *jump_start = 0x10B;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2952 *jump_dst = 0x1D2;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2953 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2954 *jump_start = 0x103;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2955 *jump_dst = 0x1CA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2956 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2957 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2958 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2959 *jump_start = 0x100;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2960 *jump_dst = 0x1FA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2961 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2962 *jump_start = 0xEB;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2963 *jump_dst = 0x1E5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2964 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2965 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2966 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2967 *jump_start = 0xDB;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2968 *jump_dst = 0x1D5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2969 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2970 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2971
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1077 diff changeset	2972 static uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target)
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2973 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2974 uint32_t jump_start, jump_dst;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2975 get_jump_params(context, &jump_start, &jump_dst);
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2976 uint32_t lines;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2977 if (context->vcounter < target) {
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	2978 if (target < jump_start \|\| context->vcounter > jump_start) {
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2979 lines = target - context->vcounter;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2980 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2981 lines = jump_start - context->vcounter + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2982 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2983 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2984 if (context->vcounter < jump_start) {
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	2985 lines = jump_start - context->vcounter + 512 - jump_dst;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2986 } else {
718 eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse. Michael Pavone <pavone@retrodev.com> parents: 717 diff changeset	2987 lines = 512 - context->vcounter;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2988 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2989 if (target < jump_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2990 lines += target;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2991 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2992 lines += jump_start + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2993 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2994 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2995 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context);
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2996 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	2997
680 4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	2998 uint32_t vdp_cycles_to_frame_end(vdp_context * context)
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	2999 {
1167 e758ddbf0624 Initial work on emulating top and bottom border area Michael Pavone <pavone@retrodev.com> parents: 1163 diff changeset	3000 return context->cycles + vdp_cycles_to_line(context, context->inactive_start);
680 4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	3001 }
4996369f1463 Some small synchronization improvements that do not seem to fix anything Michael Pavone <pavone@retrodev.com> parents: 678 diff changeset	3002
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3003 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3004 {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	3005 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3006 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3007 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3008 if (context->flags2 & FLAG2_HINT_PENDING) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	3009 return context->pending_hint_start;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3010 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3011 uint32_t hint_line;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3012 if (context->state != ACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3013 hint_line = context->regs[REG_HINT];
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3014 if (hint_line > context->inactive_start) {
724 2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display Michael Pavone <pavone@retrodev.com> parents: 722 diff changeset	3015 return 0xFFFFFFFF;
2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display Michael Pavone <pavone@retrodev.com> parents: 722 diff changeset	3016 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3017 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3018 hint_line = context->vcounter + context->hint_counter + 1;
1325 58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3019 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3020 if (hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3021 hint_line = context->regs[REG_HINT];
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3022 if (hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3023 return 0xFFFFFFFF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3024 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3025 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3026 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3027 uint32_t jump_start, jump_dst;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3028 get_jump_params(context, &jump_start, &jump_dst);
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3029 if (hint_line >= jump_start && context->vcounter < jump_dst) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3030 hint_line = (hint_line + jump_dst - jump_start) & 0x1FF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3031 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3032 if (hint_line < context->vcounter && hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3033 return 0xFFFFFFFF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3034 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right Michael Pavone <pavone@retrodev.com> parents: 1322 diff changeset	3035 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3036 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3037 return context->cycles + vdp_cycles_to_line(context, hint_line);
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3038 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3039
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3040 static uint32_t vdp_next_vint_real(vdp_context * context)
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3041 {
327 1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug Mike Pavone <pavone@retrodev.com> parents: 323 diff changeset	3042 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3043 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3044 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3045 if (context->flags2 & FLAG2_VINT_PENDING) {
717 22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation. Michael Pavone <pavone@retrodev.com> parents: 714 diff changeset	3046 return context->pending_vint_start;
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3047 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3048
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3049
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3050 return vdp_next_vint_z80(context);
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3051 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3052
1171 43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3053 uint32_t vdp_next_vint(vdp_context *context)
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3054 {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3055 uint32_t ret = vdp_next_vint_real(context);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3056 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3057 static uint32_t last = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3058 if (last != ret) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3059 printf("vdp_next_vint is %d at frame %d, line %d, hslot %d\n", ret, context->frame, context->vcounter, context->hslot);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3060 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3061 last = ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3062 #endif
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3063 return ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3064 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code. Michael Pavone <pavone@retrodev.com> parents: 1170 diff changeset	3065
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	3066 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	3067 {
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	3068 uint16_t vint_line = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->inactive_start : context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	3069 if (context->vcounter == vint_line) {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3070 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3071 if (context->regs[REG_MODE_4] & BIT_H40) {
1175 0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3072 if (context->hslot >= LINE_CHANGE_H40 \|\| context->hslot <= VINT_SLOT_H40) {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3073 uint32_t cycles = context->cycles;
1175 0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3074 if (context->hslot >= LINE_CHANGE_H40) {
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3075 if (context->hslot < 183) {
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3076 cycles += (183 - context->hslot) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3077 }
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3078
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3079 if (context->hslot < HSYNC_SLOT_H40) {
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3080 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3081 }
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3082 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ )
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3083 {
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3084 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3085 }
0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3086 cycles += (256 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3087 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3088
1175 0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3089 cycles += (VINT_SLOT_H40 - (context->hslot >= LINE_CHANGE_H40 ? 0 : context->hslot)) * MCLKS_SLOT_H40;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3090 return cycles;
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	3091 }
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3092 } else {
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	3093 if (context->hslot >= LINE_CHANGE_H32 \|\| context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	3094 if (context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	3095 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32;
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	3096 } else if (context->hslot < 233) {
500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	3097 return context->cycles + (VINT_SLOT_H32 + 256 - 233 + 148 - context->hslot) * MCLKS_SLOT_H32;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3098 } else {
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	3099 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3100 }
995 2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see. Michael Pavone <pavone@retrodev.com> parents: 991 diff changeset	3101 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3102 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3103 } else {
1177 67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency Michael Pavone <pavone@retrodev.com> parents: 1175 diff changeset	3104 if (context->hslot >= LINE_CHANGE_MODE4) {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3105 return context->cycles + (VINT_SLOT_MODE4 + 256 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3106 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3107 if (context->hslot <= VINT_SLOT_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3108 return context->cycles + (VINT_SLOT_MODE4 - context->hslot) * MCLKS_SLOT_H32;
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3109 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3110 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3111 }
1169 82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182 Michael Pavone <pavone@retrodev.com> parents: 1168 diff changeset	3112 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line);
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3113 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3114 if (context->regs[REG_MODE_4] & BIT_H40) {
1175 0e0386fa795c Fix H40 VInt inconsistency Michael Pavone <pavone@retrodev.com> parents: 1174 diff changeset	3115 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3116 } else {
1174 500d8deea802 Fix H32 VInt timing inconsistency Michael Pavone <pavone@retrodev.com> parents: 1173 diff changeset	3117 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3118 }
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	3119 } else {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3120 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32;
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	3121 }
623 66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes Michael Pavone <pavone@retrodev.com> parents: 622 diff changeset	3122 return context->cycles + cycles_to_vint;
333 f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	3123 }
f16136a3835d Update Z80 vint timing Mike Pavone <pavone@retrodev.com> parents: 332 diff changeset	3124
953 08346262990b Remove the int number argument to vdp_int_ack since it is no longer used Michael Pavone <pavone@retrodev.com> parents: 952 diff changeset	3125 void vdp_int_ack(vdp_context * context)
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3126 {
1160 5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3127 //CPU interrupt acknowledge is only used in Mode 5
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3128 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3129 //Apparently the VDP interrupt controller is not very smart
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3130 //Instead of paying attention to what interrupt is being acknowledged it just
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3131 //clears the pending flag for whatever interrupt it is currently asserted
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3132 //which may be different from the interrupt it was asserting when the 68k
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3133 //started the interrupt process. The window for this is narrow and depends
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3134 //on the latency between the int enable register write and the interrupt being
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3135 //asserted, but Fatal Rewind depends on this due to some buggy code
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3136 if ((context->flags2 & FLAG2_VINT_PENDING) && (context->regs[REG_MODE_2] & BIT_VINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3137 context->flags2 &= ~FLAG2_VINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3138 } else if((context->flags2 & FLAG2_HINT_PENDING) && (context->regs[REG_MODE_1] & BIT_HINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3139 context->flags2 &= ~FLAG2_HINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests Michael Pavone <pavone@retrodev.com> parents: 1157 diff changeset	3140 }
317 e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3141 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3142 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port. Mike Pavone <pavone@retrodev.com> parents: 291 diff changeset	3143

Mercurial > repos > blastem

annotate vdp.c @ 1336:baaf05fd64c4