Mercurial > repos > blastem
annotate vdp.c @ 1338:3706b683cd48
Fix sprite rendering for negative line. Fixes remaining visual glitch in the Titancade scene of Overdrive 2
author | Michael Pavone <pavone@retrodev.com> |
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date | Mon, 01 May 2017 20:33:59 -0700 |
parents | d092c15246a3 |
children | 35e6a93b4586 |
rev | line source |
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467
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1 /* |
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2 Copyright 2013 Michael Pavone |
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Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
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3 This file is part of BlastEm. |
467
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "vdp.h" |
75 | 7 #include "blastem.h" |
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8 #include "genesis.h" |
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9 #include <stdlib.h> |
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10 #include <string.h> |
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11 #include "render.h" |
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12 #include "util.h" |
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13 |
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Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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14 #define NTSC_INACTIVE_START 224 |
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15 #define PAL_INACTIVE_START 240 |
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16 #define MODE4_INACTIVE_START 192 |
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17 #define BUF_BIT_PRIORITY 0x40 |
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18 #define MAP_BIT_PRIORITY 0x8000 |
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19 #define MAP_BIT_H_FLIP 0x800 |
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20 #define MAP_BIT_V_FLIP 0x1000 |
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21 |
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Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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22 #define SCROLL_BUFFER_SIZE 32 |
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23 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1) |
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24 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2) |
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25 |
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26 #define MCLKS_SLOT_H40 16 |
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27 #define MCLKS_SLOT_H32 20 |
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28 #define VINT_SLOT_H40 0 //21 slots before HSYNC, 16 during, 10 after |
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29 #define VINT_SLOT_H32 0 //old value was 23, but recent tests suggest the actual value is close to the H40 one |
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30 #define VINT_SLOT_MODE4 4 |
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31 #define HSYNC_SLOT_H40 230 |
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32 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17) |
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33 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results |
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34 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results |
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35 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result |
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36 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results |
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37 #define LINE_CHANGE_H40 165 |
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38 #define LINE_CHANGE_H32 133 |
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39 #define LINE_CHANGE_MODE4 249 |
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40 #define VBLANK_START_H40 (LINE_CHANGE_H40+2) |
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41 #define VBLANK_START_H32 (LINE_CHANGE_H32+2) |
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42 #define FIFO_LATENCY 3 |
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43 |
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44 #define BORDER_TOP_V24 27 |
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45 #define BORDER_TOP_V28 11 |
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46 #define BORDER_TOP_V24_PAL 54 |
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47 #define BORDER_TOP_V28_PAL 38 |
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48 #define BORDER_TOP_V30_PAL 30 |
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49 |
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50 #define BORDER_BOT_V24 24 |
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51 #define BORDER_BOT_V28 8 |
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52 #define BORDER_BOT_V24_PAL 48 |
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53 #define BORDER_BOT_V28_PAL 32 |
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54 #define BORDER_BOT_V30_PAL 24 |
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55 |
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56 #define INVALID_LINE 0x200 |
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57 |
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58 enum { |
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59 INACTIVE = 0, |
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60 PREPARING, //used for line 0x1FF |
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61 ACTIVE |
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62 }; |
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63 |
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64 static int32_t color_map[1 << 12]; |
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65 static uint16_t mode4_address_map[0x4000]; |
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66 static uint32_t planar_to_chunky[256]; |
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67 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; |
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68 |
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69 static uint8_t debug_base[][3] = { |
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70 {127, 127, 127}, //BG |
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71 {0, 0, 127}, //A |
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72 {127, 0, 0}, //Window |
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73 {0, 127, 0}, //B |
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74 {127, 0, 127} //Sprites |
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75 }; |
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76 |
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77 static void update_video_params(vdp_context *context) |
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78 { |
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79 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
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80 if (context->regs[REG_MODE_2] & BIT_PAL) { |
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81 if (context->flags2 & FLAG2_REGION_PAL) { |
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82 context->inactive_start = PAL_INACTIVE_START; |
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83 context->border_top = BORDER_TOP_V30_PAL; |
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84 context->border_bot = BORDER_BOT_V30_PAL; |
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85 } else { |
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86 //the behavior here is rather weird and needs more investigation |
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87 context->inactive_start = 0xF0; |
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88 context->border_top = 1; |
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89 context->border_bot = 3; |
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90 } |
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91 } else { |
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92 context->inactive_start = NTSC_INACTIVE_START; |
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93 if (context->flags2 & FLAG2_REGION_PAL) { |
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94 context->border_top = BORDER_TOP_V28_PAL; |
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95 context->border_bot = BORDER_BOT_V28_PAL; |
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96 } else { |
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97 context->border_top = BORDER_TOP_V28; |
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98 context->border_bot = BORDER_TOP_V28; |
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99 } |
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100 } |
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101 if (context->regs[REG_MODE_4] & BIT_H40) { |
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102 context->max_sprites_frame = MAX_SPRITES_FRAME; |
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103 context->max_sprites_line = MAX_SPRITES_LINE; |
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Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
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104 } else { |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
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105 context->max_sprites_frame = MAX_SPRITES_FRAME_H32; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
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106 context->max_sprites_line = MAX_SPRITES_LINE_H32; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
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107 } |
1325
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Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
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108 if (context->state == INACTIVE) { |
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109 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active |
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110 if (context->vcounter < context->inactive_start) { |
58bfbed6cdb5
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111 context->state = ACTIVE; |
58bfbed6cdb5
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112 } else if (context->vcounter == 0x1FF) { |
58bfbed6cdb5
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113 context->state = PREPARING; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
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114 } |
58bfbed6cdb5
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115 } |
1167
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116 } else { |
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117 context->inactive_start = MODE4_INACTIVE_START; |
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118 if (context->flags2 & FLAG2_REGION_PAL) { |
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119 context->border_top = BORDER_TOP_V24_PAL; |
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120 context->border_bot = BORDER_BOT_V24_PAL; |
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121 } else { |
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122 context->border_top = BORDER_TOP_V24; |
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123 context->border_bot = BORDER_BOT_V24; |
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124 } |
1325
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125 if (!(context->regs[REG_MODE_1] & BIT_MODE_4)){ |
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126 context->state = INACTIVE; |
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127 } else if (context->state == INACTIVE) { |
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128 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active |
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129 if (context->vcounter < context->inactive_start) { |
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130 context->state = ACTIVE; |
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131 } |
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132 /* |
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133 FIXME: uncomment this once mode 4 renderer is updated to handle this |
58bfbed6cdb5
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134 else if (context->vcounter == 0x1FF) { |
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135 context->state = PREPARING; |
58bfbed6cdb5
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136 } |
58bfbed6cdb5
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137 */ |
58bfbed6cdb5
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138 } |
1167
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139 } |
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140 } |
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141 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
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142 static uint8_t color_map_init_done; |
426
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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143 |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
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144 void init_vdp_context(vdp_context * context, uint8_t region_pal) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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145 { |
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
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diff
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146 memset(context, 0, sizeof(*context)); |
20
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147 context->vdpmem = malloc(VRAM_SIZE); |
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
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148 memset(context->vdpmem, 0, VRAM_SIZE); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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149 /* |
488
32f053ad9b02
Basic OpenGL rendering is working
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481
diff
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150 */ |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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151 if (headless) { |
1168 | 152 context->output = malloc(LINEBUF_SIZE * sizeof(uint32_t)); |
1077
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
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153 context->output_pitch = 0; |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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154 } else { |
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155 context->fb = render_get_framebuffer(FRAMEBUFFER_ODD, &context->output_pitch); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
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156 } |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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38
diff
changeset
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157 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
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158 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
20
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Mostly broken VDP core and savestate viewer
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159 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
160 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
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161 context->sprite_draws = MAX_DRAWS; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
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470
diff
changeset
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162 context->fifo_write = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
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parents:
470
diff
changeset
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163 context->fifo_read = -1; |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
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164 context->regs[REG_HINT] = context->hint_counter = 0xFF; |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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165 |
426
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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166 if (!color_map_init_done) { |
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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167 uint8_t b,g,r; |
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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168 for (uint16_t color = 0; color < (1 << 12); color++) { |
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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169 if (color & FBUF_SHADOW) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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170 b = levels[(color >> 9) & 0x7]; |
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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171 g = levels[(color >> 5) & 0x7]; |
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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172 r = levels[(color >> 1) & 0x7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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173 } else if(color & FBUF_HILIGHT) { |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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174 b = levels[((color >> 9) & 0x7) + 7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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175 g = levels[((color >> 5) & 0x7) + 7]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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176 r = levels[((color >> 1) & 0x7) + 7]; |
1120
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Somewhat broken implementation of Mode 4
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177 } else if(color & FBUF_MODE4) { |
1127
cb4771f4543a
Fix Mode 4 color mapping
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parents:
1125
diff
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178 b = levels[(color >> 4 & 0xC) | (color >> 6 & 0x2)]; |
1125
fba485949723
Brighten up Mode 4 colors
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179 g = levels[(color >> 2 & 0x8) | (color >> 1 & 0x4) | (color >> 4 & 0x2)]; |
fba485949723
Brighten up Mode 4 colors
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parents:
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180 r = levels[(color << 1 & 0xC) | (color >> 1 & 0x2)]; |
426
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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181 } else { |
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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182 b = levels[(color >> 8) & 0xE]; |
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183 g = levels[(color >> 4) & 0xE]; |
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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184 r = levels[color & 0xE]; |
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185 } |
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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186 color_map[color] = render_map_color(r, g, b); |
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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187 } |
1120
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Somewhat broken implementation of Mode 4
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188 for (uint16_t mode4_addr = 0; mode4_addr < 0x4000; mode4_addr++) |
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Somewhat broken implementation of Mode 4
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189 { |
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Somewhat broken implementation of Mode 4
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190 uint16_t mode5_addr = mode4_addr & 0x3DFD; |
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Somewhat broken implementation of Mode 4
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191 mode5_addr |= mode4_addr << 8 & 0x200; |
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Somewhat broken implementation of Mode 4
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192 mode5_addr |= mode4_addr >> 8 & 2; |
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Somewhat broken implementation of Mode 4
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193 mode4_address_map[mode4_addr] = mode5_addr; |
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Somewhat broken implementation of Mode 4
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194 } |
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Somewhat broken implementation of Mode 4
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195 for (uint32_t planar = 0; planar < 256; planar++) |
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Somewhat broken implementation of Mode 4
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196 { |
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197 uint32_t chunky = 0; |
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198 for (int bit = 7; bit >= 0; bit--) |
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199 { |
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200 chunky = chunky << 4; |
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201 chunky |= planar >> bit & 1; |
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202 } |
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203 planar_to_chunky[planar] = chunky; |
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204 } |
426
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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205 color_map_init_done = 1; |
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206 } |
437
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207 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++) |
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208 { |
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209 uint8_t src = color & DBG_SRC_MASK; |
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210 if (src > DBG_SRC_S) { |
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211 context->debugcolors[color] = 0; |
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212 } else { |
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213 uint8_t r,g,b; |
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214 b = debug_base[src][0]; |
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215 g = debug_base[src][1]; |
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216 r = debug_base[src][2]; |
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217 if (color & DBG_PRIORITY) |
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218 { |
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219 if (b) { |
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220 b += 48; |
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221 } |
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222 if (g) { |
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223 g += 48; |
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224 } |
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225 if (r) { |
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226 r += 48; |
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227 } |
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228 } |
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229 if (color & DBG_SHADOW) { |
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230 b /= 2; |
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231 g /= 2; |
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232 r /=2 ; |
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233 } |
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234 if (color & DBG_HILIGHT) { |
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235 if (b) { |
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236 b += 72; |
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237 } |
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238 if (g) { |
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239 g += 72; |
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240 } |
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241 if (r) { |
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242 r += 72; |
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243 } |
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244 } |
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245 context->debugcolors[color] = render_map_color(r, g, b); |
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246 } |
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247 } |
623
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248 if (region_pal) { |
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249 context->flags2 |= FLAG2_REGION_PAL; |
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250 } |
1167
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251 update_video_params(context); |
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252 if (!headless) { |
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253 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * context->border_top); |
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254 } |
20
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255 } |
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256 |
884
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257 void vdp_free(vdp_context *context) |
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258 { |
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259 free(context->vdpmem); |
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260 free(context->linebuf); |
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261 free(context); |
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262 } |
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|
263 |
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264 static int is_refresh(vdp_context * context, uint32_t slot) |
460
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265 { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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266 if (context->regs[REG_MODE_4] & BIT_H40) { |
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267 return slot == 250 || slot == 26 || slot == 59 || slot == 90 || slot == 122 || slot == 154; |
460
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268 } else { |
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269 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
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270 //These numbers are guesses based on H40 numbers |
622
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Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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|
271 return slot == 243 || slot == 19 || slot == 51 || slot == 83 || slot == 115; |
460
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|
272 //The numbers below are the refresh slots during active display |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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|
273 //return (slot == 29 || slot == 61 || slot == 93 || slot == 125); |
460
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274 } |
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|
275 } |
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|
276 |
1151
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Fix some issues with VDP interface in Mode 4/PBC mode
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|
277 static void increment_address(vdp_context *context) |
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|
278 { |
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279 context->address += context->regs[REG_AUTOINC]; |
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280 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) { |
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|
281 context->address++; |
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|
282 } |
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diff
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|
283 } |
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diff
changeset
|
284 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
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1077
diff
changeset
|
285 static void render_sprite_cells(vdp_context * context) |
20
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parents:
diff
changeset
|
286 { |
21
72ce60cb1711
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20
diff
changeset
|
287 if (context->cur_slot >= context->sprite_draws) { |
72ce60cb1711
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20
diff
changeset
|
288 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
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438
diff
changeset
|
289 |
20
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parents:
diff
changeset
|
290 uint16_t dir; |
f664eeb55cb4
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parents:
diff
changeset
|
291 int16_t x; |
f664eeb55cb4
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parents:
diff
changeset
|
292 if (d->h_flip) { |
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diff
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|
293 x = d->x_pos + 7; |
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diff
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|
294 dir = -1; |
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diff
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|
295 } else { |
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diff
changeset
|
296 x = d->x_pos; |
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diff
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|
297 dir = 1; |
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diff
changeset
|
298 } |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
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26
diff
changeset
|
299 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
300 context->cur_slot--; |
143
e5487ef04619
Fix infinite loop bug in sprite rendering
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parents:
142
diff
changeset
|
301 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
1029
4263dc9cf86d
Fix implementation of sprite collision flag. Old implementation did not make sense.
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1019
diff
changeset
|
302 if (x >= 0 && x < 320) { |
4263dc9cf86d
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1019
diff
changeset
|
303 if (!(context->linebuf[x] & 0xF)) { |
4263dc9cf86d
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1019
diff
changeset
|
304 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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1019
diff
changeset
|
305 } else if (context->vdpmem[address] >> 4) { |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
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481
diff
changeset
|
306 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
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481
diff
changeset
|
307 } |
20
f664eeb55cb4
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parents:
diff
changeset
|
308 } |
f664eeb55cb4
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diff
changeset
|
309 x += dir; |
1029
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1019
diff
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|
310 if (x >= 0 && x < 320) { |
4263dc9cf86d
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1019
diff
changeset
|
311 if (!(context->linebuf[x] & 0xF)) { |
4263dc9cf86d
Fix implementation of sprite collision flag. Old implementation did not make sense.
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1019
diff
changeset
|
312 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
4263dc9cf86d
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1019
diff
changeset
|
313 } else if (context->vdpmem[address] & 0xF) { |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
314 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
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Initial implementation of sprite overflow and sprite collision status register flags
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315 } |
20
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Mostly broken VDP core and savestate viewer
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316 } |
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|
317 x += dir; |
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|
318 } |
1337
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Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
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319 } else { |
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320 context->cur_slot--; |
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321 } |
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322 } |
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|
323 |
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324 static void fetch_sprite_cells_mode4(vdp_context * context) |
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325 { |
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326 if (context->sprite_index >= context->sprite_draws) { |
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327 sprite_draw * d = context->sprite_draw_list + context->sprite_index; |
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328 uint32_t address = mode4_address_map[d->address & 0x3FFF]; |
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329 context->fetch_tmp[0] = context->vdpmem[address]; |
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330 context->fetch_tmp[1] = context->vdpmem[address + 1]; |
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331 } |
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332 } |
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333 |
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334 static void render_sprite_cells_mode4(vdp_context * context) |
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335 { |
1135
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336 if (context->sprite_index >= context->sprite_draws) { |
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337 sprite_draw * d = context->sprite_draw_list + context->sprite_index; |
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338 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1; |
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339 pixels |= planar_to_chunky[context->fetch_tmp[1]]; |
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340 uint32_t address = mode4_address_map[(d->address + 2) & 0x3FFF]; |
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341 pixels |= planar_to_chunky[context->vdpmem[address]] << 3; |
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342 pixels |= planar_to_chunky[context->vdpmem[address + 1]] << 2; |
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343 int x = d->x_pos & 0xFF; |
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344 for (int i = 28; i >= 0; i -= 4, x++) |
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345 { |
1155
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346 if (context->linebuf[x] && (pixels >> i & 0xF)) { |
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347 if ( |
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348 ((context->regs[REG_MODE_1] & BIT_SPRITE_8PX) && x > 8) |
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349 || ((!(context->regs[REG_MODE_1] & BIT_SPRITE_8PX)) && x < 256) |
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|
350 ) { |
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|
351 context->flags2 |= FLAG2_SPRITE_COLLIDE; |
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352 } |
1120
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353 } else { |
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354 context->linebuf[x] = pixels >> i & 0xF; |
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355 } |
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356 } |
1135
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357 context->sprite_index--; |
1120
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358 } |
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|
359 } |
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360 |
1320
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SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
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|
361 static uint32_t mode5_sat_address(vdp_context *context) |
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362 { |
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363 uint32_t addr = context->regs[REG_SAT] << 9; |
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364 if (!(context->regs[REG_MODE_2] & BIT_128K_VRAM)) { |
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|
365 addr &= 0xFFFF; |
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366 } |
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SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
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367 if (context->regs[REG_MODE_4] & BIT_H40) { |
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|
368 addr &= 0x1FC00; |
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|
369 } |
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|
370 return addr; |
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SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
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|
371 } |
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SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
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|
372 |
322
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
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318
diff
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|
373 void vdp_print_sprite_table(vdp_context * context) |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
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|
374 { |
1149
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|
375 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
1320
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SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
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changeset
|
376 uint16_t sat_address = mode5_sat_address(context); |
1149
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Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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|
377 uint16_t current_index = 0; |
6b0da6021544
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|
378 uint8_t count = 0; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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|
379 do { |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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|
380 uint16_t address = current_index * 8 + sat_address; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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|
381 uint16_t cache_address = current_index * 4; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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|
382 uint8_t height = ((context->sat_cache[cache_address+2] & 0x3) + 1) * 8; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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changeset
|
383 uint8_t width = (((context->sat_cache[cache_address+2] >> 2) & 0x3) + 1) * 8; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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changeset
|
384 int16_t y = ((context->sat_cache[cache_address] & 0x3) << 8 | context->sat_cache[cache_address+1]) & 0x1FF; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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|
385 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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changeset
|
386 uint16_t link = context->sat_cache[cache_address+3] & 0x7F; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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diff
changeset
|
387 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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1138
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changeset
|
388 uint8_t pri = context->vdpmem[address + 4] >> 7; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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changeset
|
389 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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parents:
1138
diff
changeset
|
390 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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1138
diff
changeset
|
391 current_index = link; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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changeset
|
392 count++; |
6b0da6021544
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|
393 } while (current_index != 0 && count < 80); |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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|
394 } else { |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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changeset
|
395 uint16_t sat_address = (context->regs[REG_SAT] & 0x7E) << 7; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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|
396 for (int i = 0; i < 64; i++) |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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1138
diff
changeset
|
397 { |
1161
c2210d586950
A bunch of Mode 4 fixes
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1160
diff
changeset
|
398 uint8_t y = context->vdpmem[mode4_address_map[sat_address + (i ^ 1)]]; |
c2210d586950
A bunch of Mode 4 fixes
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1160
diff
changeset
|
399 if (y == 0xD0) { |
1149
6b0da6021544
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diff
changeset
|
400 break; |
6b0da6021544
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Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
401 } |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
402 uint8_t x = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2 + 1]]; |
c2210d586950
A bunch of Mode 4 fixes
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1160
diff
changeset
|
403 uint16_t tile_address = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2]] * 32 |
1149
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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1138
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changeset
|
404 + (context->regs[REG_STILE_BASE] << 11 & 0x2000); |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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1138
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changeset
|
405 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) { |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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changeset
|
406 tile_address &= ~32; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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1138
diff
changeset
|
407 } |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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1138
diff
changeset
|
408 printf("Sprite %d: X=%d, Y=%d, Pat=%X\n", i, x, y, tile_address); |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
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1138
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changeset
|
409 } |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
410 } |
322
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
411 } |
8e2fa485c0f2
Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents:
318
diff
changeset
|
412 |
705
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
413 #define VRAM_READ 0 //0000 |
ce4046476abc
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parents:
699
diff
changeset
|
414 #define VRAM_WRITE 1 //0001 |
ce4046476abc
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parents:
699
diff
changeset
|
415 //2 would trigger register write 0010 |
ce4046476abc
Add description of cd register value to vr debugger command
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parents:
699
diff
changeset
|
416 #define CRAM_WRITE 3 //0011 |
ce4046476abc
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parents:
699
diff
changeset
|
417 #define VSRAM_READ 4 //0100 |
ce4046476abc
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parents:
699
diff
changeset
|
418 #define VSRAM_WRITE 5//0101 |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
419 //6 would trigger regsiter write 0110 |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
420 //7 is a mystery //0111 |
705
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
421 #define CRAM_READ 8 //1000 |
ce4046476abc
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parents:
699
diff
changeset
|
422 //9 is also a mystery //1001 |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
423 //A would trigger register write 1010 |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
424 //B is a mystery 1011 |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
425 #define VRAM_READ8 0xC //1100 |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
426 //D is a mystery 1101 |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
427 //E would trigger register write 1110 |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
428 //F is a mystery 1111 |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
429 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
430 //Possible theory on how bits work |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
431 //CD0 = Read/Write flag |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
432 //CD2,(CD1|CD3) = RAM type |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
433 // 00 = VRAM |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
434 // 01 = CRAM |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
435 // 10 = VSRAM |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
436 // 11 = VRAM8 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
437 //Would result in |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
438 // 7 = VRAM8 write |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
439 // 9 = CRAM write alias |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
440 // B = CRAM write alias |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
441 // D = VRAM8 write alias |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
442 // F = VRAM8 write alais |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
443 |
705
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
444 #define DMA_START 0x20 |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
445 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
446 static const char * cd_name(uint8_t cd) |
705
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
447 { |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
448 switch (cd & 0xF) |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
449 { |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
450 case VRAM_READ: |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
451 return "VRAM read"; |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
452 case VRAM_WRITE: |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
453 return "VRAM write"; |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
454 case CRAM_WRITE: |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
455 return "CRAM write"; |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
456 case VSRAM_READ: |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
457 return "VSRAM read"; |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
458 case VSRAM_WRITE: |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
459 return "VSRAM write"; |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
460 case VRAM_READ8: |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
461 return "VRAM read (undocumented 8-bit mode)"; |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
462 default: |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
463 return "invalid"; |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
464 } |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
465 } |
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
466 |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
467 void vdp_print_reg_explain(vdp_context * context) |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
468 { |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
469 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
470 printf("**Mode Group**\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
471 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
1331
9bba5ff5beb8
Add 128K VRAM bit to VDP register print in debugger
Michael Pavone <pavone@retrodev.com>
parents:
1325
diff
changeset
|
472 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d, %dK VRAM\n" |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
473 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
474 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
757
483f7e7926a6
More clang warning cleanup
Michael Pavone <pavone@retrodev.com>
parents:
748
diff
changeset
|
475 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", (context->regs[REG_MODE_1] & BIT_PAL_SEL) != 0, |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
476 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
477 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
1331
9bba5ff5beb8
Add 128K VRAM bit to VDP register print in debugger
Michael Pavone <pavone@retrodev.com>
parents:
1325
diff
changeset
|
478 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, context->regs[REG_MODE_1] & BIT_128K_VRAM ? 128 : 64, |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
479 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
480 hscroll[context->regs[REG_MODE_3] & 0x3], |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
481 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
1149
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
482 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
483 printf("\n**Table Group**\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
484 "02: %.2X | Scroll A Name Table: $%.4X\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
485 "03: %.2X | Window Name Table: $%.4X\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
486 "04: %.2X | Scroll B Name Table: $%.4X\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
487 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
488 "0D: %.2X | HScroll Data Table: $%.4X\n", |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
489 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
490 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
491 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
1320
df3d690cb2c3
SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1319
diff
changeset
|
492 context->regs[REG_SAT], mode5_sat_address(context), |
1149
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
493 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10); |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
494 } else { |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
495 printf("\n**Table Group**\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
496 "02: %.2X | Background Name Table: $%.4X\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
497 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
498 "06: %.2X | Sprite Tile Base: $%.4X\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
499 "08: %.2X | Background X Scroll: %d\n" |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
500 "09: %.2X | Background Y Scroll: %d\n", |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
501 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0xE) << 10, |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
502 context->regs[REG_SAT], (context->regs[REG_SAT] & 0x7E) << 7, |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
503 context->regs[REG_STILE_BASE], (context->regs[REG_STILE_BASE] & 2) << 11, |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
504 context->regs[REG_X_SCROLL], context->regs[REG_X_SCROLL], |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
505 context->regs[REG_Y_SCROLL], context->regs[REG_Y_SCROLL]); |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
506 |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
507 } |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
508 char * sizes[] = {"32", "64", "invalid", "128"}; |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
509 printf("\n**Misc Group**\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
510 "07: %.2X | Backdrop Color: $%X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
511 "0A: %.2X | H-Int Counter: %u\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
512 "0F: %.2X | Auto-increment: $%X\n" |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
513 "10: %.2X | Scroll A/B Size: %sx%s\n", |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
514 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR], |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
515 context->regs[REG_HINT], context->regs[REG_HINT], |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
516 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
517 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
621
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
518 char * src_types[] = {"68K", "68K", "Copy", "Fill"}; |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
519 printf("\n**DMA Group**\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
520 "13: %.2X |\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
521 "14: %.2X | DMA Length: $%.4X words\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
522 "15: %.2X |\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
523 "16: %.2X |\n" |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
524 "17: %.2X | DMA Source Address: $%.6X, Type: %s\n", |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
525 context->regs[REG_DMALEN_L], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
526 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
527 context->regs[REG_DMASRC_L], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
528 context->regs[REG_DMASRC_M], |
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
529 context->regs[REG_DMASRC_H], |
629
9089951a1994
Small fix to display of DMA source address in vr debug command
Michael Pavone <pavone@retrodev.com>
parents:
624
diff
changeset
|
530 context->regs[REG_DMASRC_H] << 17 | context->regs[REG_DMASRC_M] << 9 | context->regs[REG_DMASRC_L] << 1, |
621
5196333b37a6
Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents:
515
diff
changeset
|
531 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]); |
438
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
532 printf("\n**Internal Group**\n" |
b3cee2fe690b
Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents:
437
diff
changeset
|
533 "Address: %X\n" |
705
ce4046476abc
Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents:
699
diff
changeset
|
534 "CD: %X - %s\n" |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
535 "Pending: %s\n" |
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
536 "VCounter: %d\n" |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
537 "HCounter: %d\n" |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
538 "VINT Pending: %s\n" |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
539 "HINT Pending: %s\n" |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
540 "Status: %X\n", |
1150
322d28e6f13c
Display both byte and word pending values to better reflect VDP pending state in PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1149
diff
changeset
|
541 context->address, context->cd, cd_name(context->cd), |
322d28e6f13c
Display both byte and word pending values to better reflect VDP pending state in PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1149
diff
changeset
|
542 (context->flags & FLAG_PENDING) ? "word" : (context->flags2 & FLAG2_BYTE_PENDING) ? "byte" : "none", |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
543 context->vcounter, context->hslot*2, (context->flags2 & FLAG2_VINT_PENDING) ? "true" : "false", |
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
544 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context)); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
545 |
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
546 //TODO: Window Group, DMA Group |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
547 } |
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
548 |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
549 static uint8_t is_active(vdp_context *context) |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
550 { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
551 return context->state != INACTIVE && (context->regs[REG_MODE_2] & BIT_DISP_EN) != 0; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
552 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
553 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
554 static void scan_sprite_table(uint32_t line, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
555 { |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
556 if (context->sprite_index && ((uint8_t)context->slot_counter) < context->max_sprites_line) { |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
557 line += 1; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
558 uint16_t ymask, ymin; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
559 uint8_t height_mult; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
560 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
561 line *= 2; |
1077
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
562 if (context->flags2 & FLAG2_EVEN_FIELD) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
563 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
564 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
565 ymask = 0x3FF; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
566 ymin = 256; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
567 height_mult = 16; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
568 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
569 ymask = 0x1FF; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
570 ymin = 128; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
571 height_mult = 8; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
572 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
573 context->sprite_index &= 0x7F; |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
574 //TODO: Implement squirelly behavior documented by Kabuto |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
575 if (context->sprite_index >= context->max_sprites_frame) { |
38
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
576 context->sprite_index = 0; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
577 return; |
898e3d035f42
Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents:
37
diff
changeset
|
578 } |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
579 uint16_t address = context->sprite_index * 4; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
580 line += ymin; |
1338
3706b683cd48
Fix sprite rendering for negative line. Fixes remaining visual glitch in the Titancade scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1337
diff
changeset
|
581 line &= 0x1FF; |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
582 uint16_t y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
583 uint8_t height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult; |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
584 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
585 if (y <= line && line < (y + height)) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
586 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
587 context->sprite_info_list[context->slot_counter].size = context->sat_cache[address+2]; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
588 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
589 context->sprite_info_list[context->slot_counter++].y = y-ymin; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
590 } |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
591 context->sprite_index = context->sat_cache[address+3] & 0x7F; |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
592 if (context->sprite_index && ((uint8_t)context->slot_counter) < context->max_sprites_line) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
593 { |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
594 //TODO: Implement squirelly behavior documented by Kabuto |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
595 if (context->sprite_index >= context->max_sprites_frame) { |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
596 context->sprite_index = 0; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
597 return; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
598 } |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
599 address = context->sprite_index * 4; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
600 y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
601 height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult; |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
602 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
603 if (y <= line && line < (y + height)) { |
27
aa1c47fab3f1
Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents:
26
diff
changeset
|
604 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
605 context->sprite_info_list[context->slot_counter].size = context->sat_cache[address+2]; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
606 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
607 context->sprite_info_list[context->slot_counter++].y = y-ymin; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
608 } |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
609 context->sprite_index = context->sat_cache[address+3] & 0x7F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
610 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
611 } |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
612 //TODO: Seems like the overflow flag should be set here if we run out of sprite info slots without hitting the end of the list |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
613 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
614 |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
615 static void scan_sprite_table_mode4(vdp_context * context) |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
616 { |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
617 if (context->sprite_index < MAX_SPRITES_FRAME_H32) { |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
618 uint32_t line = context->vcounter; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
619 line &= 0xFF; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
620 |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
621 uint32_t sat_address = mode4_address_map[(context->regs[REG_SAT] << 7 & 0x3F00) + context->sprite_index]; |
1138
25268334a24c
Fix Mode 4 sprite table Y scan to account for VRAM byte swapping
Michael Pavone <pavone@retrodev.com>
parents:
1137
diff
changeset
|
622 uint32_t y = context->vdpmem[sat_address+1]; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
623 uint32_t size = (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) ? 16 : 8; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
624 |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
625 if (y == 0xd0) { |
1122
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
626 context->sprite_index = MAX_SPRITES_FRAME_H32; |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
627 return; |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
628 } else { |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
629 if (y <= line && line < (y + size)) { |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
630 if (!context->slot_counter) { |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
631 context->sprite_index = MAX_SPRITES_FRAME_H32; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
632 context->flags |= FLAG_DOT_OFLOW; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
633 return; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
634 } |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
635 context->sprite_info_list[--(context->slot_counter)].size = size; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
636 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
637 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
638 context->sprite_index++; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
639 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
640 |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
641 if (context->sprite_index < MAX_SPRITES_FRAME_H32) { |
1138
25268334a24c
Fix Mode 4 sprite table Y scan to account for VRAM byte swapping
Michael Pavone <pavone@retrodev.com>
parents:
1137
diff
changeset
|
642 y = context->vdpmem[sat_address]; |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
643 if (y == 0xd0) { |
1122
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
644 context->sprite_index = MAX_SPRITES_FRAME_H32; |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
645 return; |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
646 } else { |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
647 if (y <= line && line < (y + size)) { |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
648 if (!context->slot_counter) { |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
649 context->sprite_index = MAX_SPRITES_FRAME_H32; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
650 context->flags |= FLAG_DOT_OFLOW; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
651 return; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
652 } |
1122
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
653 context->sprite_info_list[--(context->slot_counter)].size = size; |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
654 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
655 } |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
656 context->sprite_index++; |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
657 } |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
658 } |
d4bef26d0977
Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents:
1121
diff
changeset
|
659 |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
660 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
661 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
662 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
663 static void read_sprite_x(uint32_t line, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
664 { |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
665 if (context->cur_slot == context->max_sprites_line) { |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
666 context->cur_slot = 0; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
667 } |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
668 if (context->cur_slot < context->slot_counter) { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
669 if (context->sprite_draws) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
670 line += 1; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
671 //in tiles |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
672 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
673 //in pixels |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
674 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
675 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
676 line *= 2; |
1077
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
677 if (context->flags2 & FLAG2_EVEN_FIELD) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
678 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
679 } |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
680 height *= 2; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
681 } |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
682 uint16_t ymask, ymin; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
683 if (context->double_res) { |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
684 ymask = 0x3FF; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
685 ymin = 256; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
686 } else { |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
687 ymask = 0x1FF; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
688 ymin = 128; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
689 } |
1320
df3d690cb2c3
SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1319
diff
changeset
|
690 uint16_t att_addr = mode5_sat_address(context) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
691 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
692 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
693 uint8_t row; |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
694 uint16_t cache_addr = context->sprite_info_list[context->cur_slot].index * 4; |
1338
3706b683cd48
Fix sprite rendering for negative line. Fixes remaining visual glitch in the Titancade scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1337
diff
changeset
|
695 line = (line + ymin) & 0x1FF; |
3706b683cd48
Fix sprite rendering for negative line. Fixes remaining visual glitch in the Titancade scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1337
diff
changeset
|
696 int16_t y = ((context->sat_cache[cache_addr] << 8 | context->sat_cache[cache_addr+1]) & ymask)/* - ymin*/; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
697 if (tileinfo & MAP_BIT_V_FLIP) { |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
698 row = (y + height - 1) - line; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
699 } else { |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
700 row = line-y; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
701 } |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
702 row &= ymask >> 4; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
703 uint16_t address; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
704 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
705 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
706 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
707 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
708 } |
323
8c01b4154480
Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents:
322
diff
changeset
|
709 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
710 if (x) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
711 context->flags |= FLAG_CAN_MASK; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
712 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
713 context->flags |= FLAG_MASKED; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
714 } |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
715 |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
716 context->flags &= ~FLAG_DOT_OFLOW; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
717 int16_t i; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
718 if (context->flags & FLAG_MASKED) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
719 for (i=0; i < width && context->sprite_draws; i++) { |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
720 --context->sprite_draws; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
721 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
722 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
723 } |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
724 } else { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
725 x -= 128; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
726 int16_t base_x = x; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
727 int16_t dir; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
728 if (tileinfo & MAP_BIT_H_FLIP) { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
729 x += (width-1) * 8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
730 dir = -8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
731 } else { |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
732 dir = 8; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
733 } |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
734 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
35
233c7737c152
Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents:
34
diff
changeset
|
735 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
736 --context->sprite_draws; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
737 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
738 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
739 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
740 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
741 } |
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
742 } |
1000
1a797fcbb35f
Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents:
999
diff
changeset
|
743 //Used to be i < width |
1a797fcbb35f
Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents:
999
diff
changeset
|
744 //TODO: Confirm this is the right condition on hardware |
1a797fcbb35f
Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents:
999
diff
changeset
|
745 if (!context->sprite_draws) { |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
746 context->flags |= FLAG_DOT_OFLOW; |
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
747 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 } else { |
34
0e7df84158b1
Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents:
32
diff
changeset
|
749 context->flags |= FLAG_DOT_OFLOW; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 } |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
752 context->cur_slot++; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
755 static void read_sprite_x_mode4(vdp_context * context) |
427
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
756 { |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
757 if (context->cur_slot >= context->slot_counter) { |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
758 uint32_t address = (context->regs[REG_SAT] << 7 & 0x3F00) + 0x80 + context->sprite_info_list[context->cur_slot].index * 2; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
759 address = mode4_address_map[address]; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
760 --context->sprite_draws; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
761 uint32_t tile_address = context->vdpmem[address] * 32 + (context->regs[REG_STILE_BASE] << 11 & 0x2000); |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
762 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) { |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
763 tile_address &= ~32; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
764 } |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
765 tile_address += (context->vcounter - context->sprite_info_list[context->cur_slot].y)* 4; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
766 context->sprite_draw_list[context->sprite_draws].x_pos = context->vdpmem[address + 1]; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
767 context->sprite_draw_list[context->sprite_draws].address = tile_address; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
768 context->cur_slot--; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
769 } |
427
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
770 } |
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
changeset
|
771 |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
772 #define CRAM_BITS 0xEEE |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
773 #define VSRAM_BITS 0x7FF |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
774 #define VSRAM_DIRTY_BITS 0xF800 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
775 |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
776 //rough estimate of slot number at which border display starts |
1270
687d3969416b
Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents:
1269
diff
changeset
|
777 #define BG_START_SLOT 6 |
1183
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
778 |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
779 void write_cram(vdp_context * context, uint16_t address, uint16_t value) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
780 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
781 uint16_t addr; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
782 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
783 addr = (address/2) & (CRAM_SIZE-1); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
784 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
785 addr = address & 0x1F; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
786 value = (value << 1 & 0xE) | (value << 2 & 0xE0) | (value & 0xE00); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
787 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
788 context->cram[addr] = value; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
789 context->colors[addr] = color_map[value & CRAM_BITS]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
790 context->colors[addr + CRAM_SIZE] = color_map[(value & CRAM_BITS) | FBUF_SHADOW]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
791 context->colors[addr + CRAM_SIZE*2] = color_map[(value & CRAM_BITS) | FBUF_HILIGHT]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
792 context->colors[addr + CRAM_SIZE*3] = color_map[(value & CRAM_BITS) | FBUF_MODE4]; |
1183
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
793 |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
794 if (context->hslot >= BG_START_SLOT && ( |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
795 context->vcounter < context->inactive_start + context->border_bot |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
796 || context->vcounter > 0x200 - context->border_top |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
797 )) { |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
798 uint8_t bg_end_slot = BG_START_SLOT + (context->regs[REG_MODE_4] & BIT_H40) ? LINEBUF_SIZE/2 : (256+HORIZ_BORDER)/2; |
1183
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
799 if (context->hslot < bg_end_slot) { |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
800 uint32_t color = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->colors[addr] : context->colors[addr + CRAM_SIZE*3]; |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
801 context->output[(context->hslot - BG_START_SLOT)*2 + 1] = color; |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
802 } |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
803 } |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
804 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
805 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
806 static void vdp_advance_dma(vdp_context * context) |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
807 { |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
808 context->regs[REG_DMASRC_L] += 1; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
809 if (!context->regs[REG_DMASRC_L]) { |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
810 context->regs[REG_DMASRC_M] += 1; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
811 } |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
812 context->address += context->regs[REG_AUTOINC]; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
813 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
814 context->regs[REG_DMALEN_H] = dma_len >> 8; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
815 context->regs[REG_DMALEN_L] = dma_len; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
816 if (!dma_len) { |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
817 context->flags &= ~FLAG_DMA_RUN; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
818 context->cd &= 0xF; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
819 } |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
820 } |
1019
e34334e6c682
Fix GST savestate loading to deal with SAT cache to fix sprite corruption on savestate load. Clear out Z80 native_pc so the Z80 state does not get hosed when loading a savestate while the emulator is already running
Michael Pavone <pavone@retrodev.com>
parents:
1001
diff
changeset
|
821 |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
822 static void vdp_check_update_sat(vdp_context *context, uint32_t address, uint16_t value) |
1319
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
823 { |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
824 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
825 if (!(address & 4)) { |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
826 uint32_t sat_address = mode5_sat_address(context); |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
827 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) { |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
828 uint16_t cache_address = address - sat_address; |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
829 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC); |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
830 context->sat_cache[cache_address] = value >> 8; |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
831 context->sat_cache[cache_address^1] = value; |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
832 } |
1319
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
833 } |
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
834 } |
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
835 } |
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
836 |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
837 void vdp_check_update_sat_byte(vdp_context *context, uint32_t address, uint8_t value) |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
838 { |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
839 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
840 if (!(address & 4)) { |
1320
df3d690cb2c3
SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1319
diff
changeset
|
841 uint32_t sat_address = mode5_sat_address(context); |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
842 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
843 uint16_t cache_address = address - sat_address; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
844 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
845 context->sat_cache[cache_address] = value; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
846 } |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
847 } |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
848 } |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
849 } |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
850 |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
851 static void write_vram_word(vdp_context *context, uint32_t address, uint16_t value) |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
852 { |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
853 address = (address & 0x3FC) | (address >> 1 & 0xFC01) | (address >> 9 & 0x2); |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
854 address ^= 1; |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
855 //TODO: Support an option to actually have 128KB of VRAM |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
856 context->vdpmem[address] = value; |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
857 } |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
858 |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
859 static void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value) |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
860 { |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
861 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
1319
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
862 address &= 0xFFFF; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
863 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
864 address = mode4_address_map[address & 0x3FFF]; |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
865 } |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
866 context->vdpmem[address] = value; |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
867 } |
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
868 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
869 static void external_slot(vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 { |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
871 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80 && context->fifo_read < 0) { |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
872 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1); |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
873 fifo_entry * cur = context->fifo + context->fifo_read; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
874 cur->cycle = context->cycles; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
875 cur->address = context->address; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
876 cur->partial = 2; |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
877 vdp_advance_dma(context); |
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
878 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
879 fifo_entry * start = context->fifo + context->fifo_read; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
880 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
881 switch (start->cd & 0xF) |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
882 { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
883 case VRAM_WRITE: |
1319
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
884 if ((context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) == (BIT_128K_VRAM|BIT_MODE_5)) { |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
885 vdp_check_update_sat(context, start->address, start->value); |
1319
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
886 write_vram_word(context, start->address, start->value); |
b6796d63977f
Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents:
1318
diff
changeset
|
887 } else if (start->partial) { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
888 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
889 uint8_t byte = start->partial == 2 ? start->value >> 8 : start->value; |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
890 if (start->partial > 1) { |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
891 vdp_check_update_sat_byte(context, start->address ^ 1, byte); |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
892 } |
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
893 write_vram_byte(context, start->address ^ 1, byte); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
894 } else { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
895 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
896 vdp_check_update_sat(context, start->address, start->value); |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
897 write_vram_byte(context, start->address, start->value >> 8); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
898 start->partial = 1; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
899 //skip auto-increment and removal of entry from fifo |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
900 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
901 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
902 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
903 case CRAM_WRITE: { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
904 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
905 if (start->partial == 3) { |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
906 uint16_t val; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
907 if ((start->address & 1) && (context->regs[REG_MODE_2] & BIT_MODE_5)) { |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
908 val = (context->cram[start->address >> 1 & (CRAM_SIZE-1)] & 0xFF) | start->value << 8; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
909 } else { |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
910 uint16_t address = (context->regs[REG_MODE_2] & BIT_MODE_5) ? start->address >> 1 & (CRAM_SIZE-1) : start->address & 0x1F; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
911 val = (context->cram[address] & 0xFF00) | start->value; |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
912 } |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
913 write_cram(context, start->address, val); |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
914 } else { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
915 write_cram(context, start->address, start->partial == 2 ? context->fifo[context->fifo_write].value : start->value); |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
916 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
917 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
918 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
919 case VSRAM_WRITE: |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
920 if (((start->address/2) & 63) < VSRAM_SIZE) { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
921 //printf("VSRAM Write: %X to %X @ vcounter: %d, hslot: %d, cycle: %d\n", start->value, context->address, context->vcounter, context->hslot, context->cycles); |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
922 if (start->partial == 3) { |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
923 if (start->address & 1) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
924 context->vsram[(start->address/2) & 63] &= 0xFF; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
925 context->vsram[(start->address/2) & 63] |= start->value << 8; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
926 } else { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
927 context->vsram[(start->address/2) & 63] &= 0xFF00; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
928 context->vsram[(start->address/2) & 63] |= start->value; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
929 } |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
930 } else { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
931 context->vsram[(start->address/2) & 63] = start->partial == 2 ? context->fifo[context->fifo_write].value : start->value; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
932 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
933 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
934 |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
935 break; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
936 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
937 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
938 if (context->fifo_read == context->fifo_write) { |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
939 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
940 context->flags |= FLAG_DMA_RUN; |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
941 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
942 context->fifo_read = -1; |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
943 } |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
944 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
945 if (context->flags & FLAG_READ_FETCHED) { |
998
bf63cbf1d7bb
Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents:
995
diff
changeset
|
946 write_vram_byte(context, context->address ^ 1, context->prefetch); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
947 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
948 //Update DMA state |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
949 vdp_advance_dma(context); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
950 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
951 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
952 } else { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
953 context->prefetch = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
954 |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
955 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
956 } |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
957 } else if (!(context->cd & 1) && !(context->flags & (FLAG_READ_FETCHED|FLAG_PENDING))) { |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
958 switch(context->cd & 0xF) |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
959 { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
960 case VRAM_READ: |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
961 if (context->flags2 & FLAG2_READ_PENDING) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
962 context->prefetch |= context->vdpmem[context->address | 1]; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
963 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
964 context->flags2 &= ~FLAG2_READ_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
965 //Should this happen after the prefetch or after the read? |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
966 increment_address(context); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
967 } else { |
1318
bfdd450e7dea
Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents:
1315
diff
changeset
|
968 //TODO: 128K VRAM Mode |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
969 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
970 context->flags2 |= FLAG2_READ_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
971 } |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
972 break; |
1151
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
973 case VRAM_READ8: { |
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
974 uint32_t address = context->address ^ 1; |
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
975 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) { |
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
976 address = mode4_address_map[address & 0x3FFF]; |
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
977 } |
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
978 context->prefetch = context->vdpmem[address]; |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
979 context->prefetch |= context->fifo[context->fifo_write].value & 0xFF00; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
980 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
981 //Should this happen after the prefetch or after the read? |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
982 increment_address(context); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
983 break; |
1151
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
984 } |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
985 case CRAM_READ: |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
986 context->prefetch = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
987 context->prefetch |= context->fifo[context->fifo_write].value & ~CRAM_BITS; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
988 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
989 //Should this happen after the prefetch or after the read? |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
990 increment_address(context); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
991 break; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
992 case VSRAM_READ: { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
993 uint16_t address = (context->address /2) & 63; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
994 if (address >= VSRAM_SIZE) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
995 address = 0; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
996 } |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
997 context->prefetch = context->vsram[address] & VSRAM_BITS; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
998 context->prefetch |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
999 context->flags |= FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1000 //Should this happen after the prefetch or after the read? |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
1001 increment_address(context); |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1002 break; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1003 } |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
1004 } |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1005 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1006 } |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1007 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1008 static void run_dma_src(vdp_context * context, int32_t slot) |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1009 { |
75 | 1010 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
1011 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
1012 if (context->fifo_write == context->fifo_read) { |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1013 return; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1014 } |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1015 fifo_entry * cur = NULL; |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
1016 if (!(context->regs[REG_DMASRC_H] & 0x80)) |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1017 { |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
1018 //68K -> VDP |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
1019 if (slot == -1 || !is_refresh(context, slot-1)) { |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1020 cur = context->fifo + context->fifo_write; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1021 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
478
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1022 cur->address = context->address; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1023 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1024 cur->cd = context->cd; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1025 cur->partial = 0; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1026 if (context->fifo_read < 0) { |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1027 context->fifo_read = context->fifo_write; |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1028 } |
2e4a4188cfb0
Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents:
477
diff
changeset
|
1029 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
984
bd4d698d995b
FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
983
diff
changeset
|
1030 vdp_advance_dma(context); |
75 | 1031 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1032 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 |
40 | 1035 #define WINDOW_RIGHT 0x80 |
1036 #define WINDOW_DOWN 0x80 | |
1037 | |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1038 static void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1040 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
1041 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1042 line *= 2; |
1077
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
1043 if (context->flags2 & FLAG2_EVEN_FIELD) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1044 line++; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1045 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1046 window_line_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1047 v_offset_mask = 0xF; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1048 vscroll_shift = 4; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1049 } else { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1050 window_line_shift = 3; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1051 v_offset_mask = 0x7; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1052 vscroll_shift = 3; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
1053 } |
40 | 1054 if (!vsram_off) { |
1055 uint16_t left_col, right_col; | |
1056 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
920
e64168bb2b25
Fix calculation of window start column when it's on the right side. This removes graphical glitches in Afterburner 2, Fireshark and Dungeons and Dragons: Warriors of the Eternal Sun and probably others
Michael Pavone <pavone@retrodev.com>
parents:
884
diff
changeset
|
1057 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2 + 2; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1058 right_col = 42; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1059 } else { |
40 | 1060 left_col = 0; |
1061 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
1062 if (right_col) { | |
1063 right_col += 2; | |
1064 } | |
1065 } | |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1066 uint16_t top_line, bottom_line; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1067 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1068 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1069 bottom_line = context->double_res ? 481 : 241; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1070 } else { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1071 top_line = 0; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1072 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1073 } |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1074 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1075 uint16_t address = context->regs[REG_WINDOW] << 10; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1076 uint16_t line_offset, offset, mask; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
1077 if (context->regs[REG_MODE_4] & BIT_H40) { |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1078 address &= 0xF000; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1079 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1080 mask = 0x7F; |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1081 |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1082 } else { |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1083 address &= 0xF800; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1084 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1085 mask = 0x3F; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1086 } |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1087 if (context->double_res) { |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1088 mask <<= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1089 mask |= 1; |
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1090 } |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
1091 offset = address + line_offset + (((column - 2) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1092 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1093 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
1094 offset = address + line_offset + (((column - 1) * 2) & mask); |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1095 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
1096 context->v_offset = (line) & v_offset_mask; |
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1097 context->flags |= FLAG_WINDOW; |
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
1098 return; |
40 | 1099 } |
1100 context->flags &= ~FLAG_WINDOW; | |
1101 } | |
1290
aa1a8eb5bb2b
Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk
Michael Pavone <pavone@retrodev.com>
parents:
1289
diff
changeset
|
1102 //TODO: Verify behavior for 0x20 case |
aa1a8eb5bb2b
Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk
Michael Pavone <pavone@retrodev.com>
parents:
1289
diff
changeset
|
1103 uint16_t vscroll = 0xFF | (context->regs[REG_SCROLL] & 0x30) << 4; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
1104 if (context->double_res) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1105 vscroll <<= 1; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1106 vscroll |= 1; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
1107 } |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1108 //TODO: Further research on vscroll latch behavior and the "first column bug" |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1109 if (!column) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1110 if (context->regs[REG_MODE_3] & BIT_VSCROLL) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1111 if (context->regs[REG_MODE_4] & BIT_H40) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1112 //Based on observed behavior documented by Eke-Eke, I'm guessing the VDP |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1113 //ends up fetching the last value on the VSRAM bus in the H40 case |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1114 //getting the last latched value should be close enough for now |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1115 if (!vsram_off) { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1116 context->vscroll_latch[0] = context->vscroll_latch[1]; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1117 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1118 } else { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1119 //supposedly it's always forced to 0 in the H32 case |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1120 context->vscroll_latch[0] = context->vscroll_latch[1] = 0; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1121 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1122 } else { |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1123 context->vscroll_latch[vsram_off] = context->vsram[vsram_off]; |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1124 } |
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
1125 } else if (context->regs[REG_MODE_3] & BIT_VSCROLL) { |
710
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
1126 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off]; |
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
1127 } |
4cd8823f79e3
First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents:
708
diff
changeset
|
1128 vscroll &= context->vscroll_latch[vsram_off] + line; |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
1129 context->v_offset = vscroll & v_offset_mask; |
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
1130 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
1131 vscroll >>= vscroll_shift; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1132 uint16_t hscroll_mask; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1133 uint16_t v_mul; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1134 switch(context->regs[REG_SCROLL] & 0x3) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1135 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1136 case 0: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1137 hscroll_mask = 0x1F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1138 v_mul = 64; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1140 case 0x1: |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
1141 hscroll_mask = 0x3F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1142 v_mul = 128; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1143 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1144 case 0x2: |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1145 //TODO: Verify this behavior |
1334
7757d605e365
Adjust how the invalid size is handled for the horizontal dimmension of a plane. Fixes some garbage on the spinning cube scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1333
diff
changeset
|
1146 hscroll_mask = 0x1F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1147 v_mul = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1149 case 0x3: |
108
1a551a85cb06
Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents:
87
diff
changeset
|
1150 hscroll_mask = 0x7F; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1151 v_mul = 256; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1152 break; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1153 } |
28 | 1154 uint16_t hscroll, offset; |
1155 for (int i = 0; i < 2; i++) { | |
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
1156 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
1157 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
1158 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
28 | 1159 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
1160 if (i) { | |
1161 context->col_2 = col_val; | |
1162 } else { | |
1163 context->col_1 = col_val; | |
1164 } | |
1165 } | |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1166 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1167 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1168 static void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1169 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
1170 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1171 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1172 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1173 static void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1174 { |
25
4d0c20ad815a
Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents:
24
diff
changeset
|
1175 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1176 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1177 |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1178 static void read_map_mode4(uint16_t column, uint32_t line, vdp_context * context) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1179 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1180 uint32_t address = (context->regs[REG_SCROLL_A] & 0xE) << 10; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1181 //add row |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1182 uint32_t vscroll = line; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1183 if (column < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1184 vscroll += context->regs[REG_Y_SCROLL]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1185 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1186 if (vscroll > 223) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1187 vscroll -= 224; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1188 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1189 address += (vscroll >> 3) * 2 * 32; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1190 //add column |
1136
52f25c41abdd
Fix horizontal scrolling in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1135
diff
changeset
|
1191 address += ((column - (context->hscroll_a >> 3)) & 31) * 2; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1192 //adjust for weird VRAM mapping in Mode 4 |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1193 address = mode4_address_map[address]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1194 context->col_1 = (context->vdpmem[address] << 8) | context->vdpmem[address+1]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1195 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1196 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1197 static void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1198 { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1199 uint16_t address; |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
1200 uint16_t vflip_base; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1201 if (context->double_res) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1202 address = ((col & 0x3FF) << 6); |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
1203 vflip_base = 60; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1204 } else { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1205 address = ((col & 0x7FF) << 5); |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
1206 vflip_base = 28; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1207 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1208 if (col & MAP_BIT_V_FLIP) { |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
1209 address += vflip_base - 4 * context->v_offset; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1210 } else { |
1032
679137a0e78e
Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents:
1029
diff
changeset
|
1211 address += 4 * context->v_offset; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1212 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1213 uint16_t pal_priority = (col >> 9) & 0x70; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1214 int32_t dir; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1215 if (col & MAP_BIT_H_FLIP) { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1216 offset += 7; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1217 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1218 dir = -1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1219 } else { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1220 dir = 1; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1221 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1222 for (uint32_t i=0; i < 4; i++, address++) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1223 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1224 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1225 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1226 offset &= SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1227 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF); |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1228 offset += dir; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1229 offset &= SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1230 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1231 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1232 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1233 static void render_map_1(vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1234 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1235 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1236 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1237 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1238 static void render_map_2(vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1239 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1240 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1241 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1242 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1243 static void render_map_3(vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1244 { |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1245 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context); |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1246 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1247 |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1248 static void fetch_map_mode4(uint16_t col, uint32_t line, vdp_context *context) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1249 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1250 //calculate pixel row to fetch |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1251 uint32_t vscroll = line; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1252 if (col < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1253 vscroll += context->regs[REG_Y_SCROLL]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1254 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1255 if (vscroll > 223) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1256 vscroll -= 224; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1257 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1258 vscroll &= 7; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1259 if (context->col_1 & 0x400) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1260 vscroll = 7 - vscroll; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1261 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1262 |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1263 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1264 context->fetch_tmp[0] = context->vdpmem[address]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1265 context->fetch_tmp[1] = context->vdpmem[address+1]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1266 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1267 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1268 static void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1269 { |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1270 uint32_t *dst; |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1271 uint8_t output_disabled = (context->test_port & TEST_BIT_DISABLE) != 0; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1272 uint8_t test_layer = context->test_port >> 7 & 3; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1273 if (context->state == PREPARING) { |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1274 if (col) { |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1275 col -= 2; |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1276 dst = context->output + BORDER_LEFT + col * 8; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1277 } else { |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1278 dst = context->output; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1279 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1280 for (int i = 0; i < BORDER_LEFT; i++, dst++) |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1281 { |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1282 *dst = bg_color; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1283 } |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1284 return; |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1285 } |
1170
9170fc4d9835
Don't adjust cycles every frame. Only when we start getting close to UINT_MAX. Don't adjust all the way down to zero when we do adjust. Shouldn't fix anything, but may make debugging current issues easier.
Michael Pavone <pavone@retrodev.com>
parents:
1169
diff
changeset
|
1286 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1287 for (int i = 0; i < 16; i++) |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1288 { |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1289 *(dst++) = color; |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1290 } |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1291 return; |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1292 } |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1293 line &= 0xFF; |
1180
e2b81a0f8fd8
Undo poorly thought out minor optimization that screwed up rendering
Michael Pavone <pavone@retrodev.com>
parents:
1179
diff
changeset
|
1294 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context); |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1295 uint8_t *sprite_buf, *plane_a, *plane_b; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1296 int plane_a_off, plane_b_off; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1297 if (col) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1298 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1299 col-=2; |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1300 dst = context->output + BORDER_LEFT + col * 8; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1301 if (context->debug < 2) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1302 sprite_buf = context->linebuf + col * 8; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1303 uint8_t a_src, src; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1304 if (context->flags & FLAG_WINDOW) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1305 plane_a_off = context->buf_a_off; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1306 a_src = DBG_SRC_W; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1307 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1308 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1309 a_src = DBG_SRC_A; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1310 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1311 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1312 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1313 |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1314 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1315 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1316 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1317 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1318 uint8_t pixel = context->regs[REG_BG_COLOR]; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1319 uint32_t *colors = context->colors; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1320 src = DBG_SRC_BG; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1321 if (*plane_b & 0xF) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1322 pixel = *plane_b; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1323 src = DBG_SRC_B; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1324 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1325 uint8_t intensity = *plane_b & BUF_BIT_PRIORITY; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1326 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1327 pixel = *plane_a; |
1315
810ae0287d66
Fix minor bug that displayed window plane as if it were plane A In plane debug view
Michael Pavone <pavone@retrodev.com>
parents:
1299
diff
changeset
|
1328 src = a_src; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1329 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1330 intensity |= *plane_a & BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1331 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1332 if ((*sprite_buf & 0x3F) == 0x3E) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1333 intensity += BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1334 } else if ((*sprite_buf & 0x3F) == 0x3F) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1335 intensity = 0; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1336 } else { |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1337 pixel = *sprite_buf; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1338 src = DBG_SRC_S; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1339 if ((pixel & 0xF) == 0xE) { |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1340 intensity = BUF_BIT_PRIORITY; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1341 } else { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1342 intensity |= pixel & BUF_BIT_PRIORITY; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1343 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1344 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1345 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1346 if (output_disabled) { |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1347 pixel = 0x3F; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1348 } |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1349 if (!intensity) { |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
1350 src |= DBG_SHADOW; |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1351 colors += CRAM_SIZE; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1352 } else if (intensity == BUF_BIT_PRIORITY*2) { |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1353 src |= DBG_HILIGHT; |
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1354 colors += CRAM_SIZE*2; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1355 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1356 //TODO: Verify how test register stuff interacts with shadow/highlight |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1357 //TODO: Simulate CRAM corruption from bus fight |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1358 switch (test_layer) |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1359 { |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1360 case 1: |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1361 pixel &= *sprite_buf; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1362 if (output_disabled && pixel) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1363 src = DBG_SRC_S; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1364 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1365 break; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1366 case 2: |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1367 pixel &= *plane_a; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1368 if (output_disabled && pixel) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1369 src = DBG_SRC_A; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1370 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1371 break; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1372 case 3: |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1373 pixel &= *plane_b; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1374 if (output_disabled && pixel) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1375 src = DBG_SRC_B; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1376 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1377 break; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1378 } |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1379 |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1380 uint32_t outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1381 if (context->debug) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1382 outpixel = context->debugcolors[src]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1383 } else { |
748
45b62d237b7b
Fixed shadow/highlight mode
Michael Pavone <pavone@retrodev.com>
parents:
724
diff
changeset
|
1384 outpixel = colors[pixel & 0x3F]; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1385 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1386 *(dst++) = outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1387 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1388 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1389 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1390 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1391 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1392 uint8_t pixel = context->regs[REG_BG_COLOR]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1393 src = DBG_SRC_BG; |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1394 if (output_disabled) { |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1395 pixel = 0x3F; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1396 } else { |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1397 if (*plane_b & 0xF) { |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1398 pixel = *plane_b; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1399 src = DBG_SRC_B; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1400 } |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1401 if (*plane_a & 0xF && (*plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1402 pixel = *plane_a; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1403 src = a_src; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1404 } |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1405 if (*sprite_buf & 0xF && (*sprite_buf & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) { |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1406 pixel = *sprite_buf; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1407 src = DBG_SRC_S; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1408 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1409 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1410 //TODO: Simulate CRAM corruption from bus fight |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1411 switch (test_layer) |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1412 { |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1413 case 1: |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1414 pixel &= *sprite_buf; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1415 if (output_disabled && pixel) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1416 src = DBG_SRC_S; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1417 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1418 break; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1419 case 2: |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1420 pixel &= *plane_a; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1421 if (output_disabled && pixel) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1422 src = DBG_SRC_A; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1423 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1424 break; |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1425 case 3: |
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1426 pixel &= *plane_b; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1427 if (output_disabled && pixel) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1428 src = DBG_SRC_B; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1429 } |
1322
b1423d432c0e
Initial stab at implementing the output disable/layer selection bits of the VDP test register
Michael Pavone <pavone@retrodev.com>
parents:
1321
diff
changeset
|
1430 break; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
1431 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1432 uint32_t outpixel; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1433 if (context->debug) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1434 outpixel = context->debugcolors[src]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1435 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1436 outpixel = context->colors[pixel & 0x3F]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1437 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1438 *(dst++) = outpixel; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
1439 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1440 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1441 } else if (context->debug == 2) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1442 if (col < 32) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1443 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1444 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1445 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1446 *(dst++) = context->colors[col * 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1447 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1448 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1449 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1450 *(dst++) = context->colors[col * 2 + 1]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1451 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1452 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1453 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1454 *(dst++) = context->colors[col * 2 + 2]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1455 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1456 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1457 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1458 *(dst++) = context->colors[col * 2 + 3]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1459 } else if (col == 32 || line >= 192) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1460 for (int32_t i = 0; i < 16; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1461 *(dst++) = 0; |
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
1462 } |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1463 } else { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1464 for (int32_t i = 0; i < 16; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1465 *(dst++) = context->colors[line / 3 + (col - 34) * 0x20]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1466 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1467 } |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
1468 } else { |
771
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1469 uint32_t base = (context->debug - 3) * 0x200; |
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1470 uint32_t cell = base + (line / 8) * (context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32) + col; |
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1471 uint32_t address = (cell * 32 + (line % 8) * 4) & 0xFFFF; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1472 for (int32_t i = 0; i < 4; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1473 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] >> 4)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1474 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] & 0xF)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1475 address++; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1476 } |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1477 cell++; |
771
0565b2c1a034
Add ability to change start address for VRAM viewer. Fix handling of DMA enable flag when it comes to DMA fills. This fixes a bug in James Pond 3
Michael Pavone <pavone@retrodev.com>
parents:
757
diff
changeset
|
1478 address = (cell * 32 + (line % 8) * 4) & 0xFFFF; |
722
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1479 for (int32_t i = 0; i < 4; i ++) { |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1480 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] >> 4)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1481 *(dst++) = context->colors[(context->debug_pal << 4) | (context->vdpmem[address] & 0xF)]; |
8f5339961903
Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents:
720
diff
changeset
|
1482 address++; |
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
1483 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1484 } |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1485 } else { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1486 dst = context->output; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1487 uint8_t pixel = context->regs[REG_BG_COLOR] & 0x3F; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1488 if (output_disabled) { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1489 pixel = 0x3F; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1490 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1491 uint32_t bg_color = context->colors[pixel]; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1492 if (test_layer) { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1493 switch(test_layer) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1494 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1495 case 1: |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1496 //TODO: Display garbage from bus? |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1497 for (int i = 0; i < BORDER_LEFT; i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1498 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1499 *dst = bg_color; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1500 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1501 break; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1502 case 2: { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1503 //plane A |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1504 //TODO: Deal with Window layer |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1505 int i; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1506 /*for (i = 0; i < (context->hscroll_a & 0xF) - (16 - BORDER_LEFT); i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1507 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1508 *dst = bg_color; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1509 }*/ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1510 i = 0; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1511 uint8_t buf_off = context->buf_a_off - (context->hscroll_a & 0xF) + (16 - BORDER_LEFT); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1512 //uint8_t *src = context->tmp_buf_a + ((context->buf_a_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_a & 0xF))) & SCROLL_BUFFER_MASK); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1513 for (; i < BORDER_LEFT; buf_off++, i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1514 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1515 *dst = context->colors[context->tmp_buf_a[buf_off & SCROLL_BUFFER_MASK]]; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1516 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1517 break; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1518 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1519 case 3: { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1520 //plane B |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1521 int i; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1522 /*for (i = 0; i < (context->hscroll_b & 0xF) - (16 - BORDER_LEFT); i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1523 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1524 *dst = bg_color; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1525 }*/ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1526 i = 0; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1527 uint8_t buf_off = context->buf_b_off - (context->hscroll_b & 0xF) + (16 - BORDER_LEFT); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1528 //uint8_t *src = context->tmp_buf_b + ((context->buf_b_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_b & 0xF))) & SCROLL_BUFFER_MASK); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1529 for (; i < BORDER_LEFT; buf_off++, i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1530 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1531 *dst = context->colors[context->tmp_buf_b[buf_off & SCROLL_BUFFER_MASK]]; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1532 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1533 break; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1534 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1535 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1536 } else { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1537 for (int i = 0; i < BORDER_LEFT; i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1538 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1539 *dst = bg_color; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1540 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1541 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1542 } |
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1543 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
1544 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1545 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1546 |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1547 static void render_map_mode4(uint32_t line, int32_t col, vdp_context * context) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1548 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1549 uint32_t vscroll = line; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1550 if (col < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1551 vscroll += context->regs[REG_Y_SCROLL]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1552 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1553 if (vscroll > 223) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1554 vscroll -= 224; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1555 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1556 vscroll &= 7; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1557 if (context->col_1 & 0x400) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1558 //vflip |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1559 vscroll = 7 - vscroll; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1560 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1561 |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1562 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1563 pixels |= planar_to_chunky[context->fetch_tmp[1]]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1564 |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1565 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4 + 2]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1566 pixels |= planar_to_chunky[context->vdpmem[address]] << 3; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1567 pixels |= planar_to_chunky[context->vdpmem[address+1]] << 2; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1568 |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1569 int i, i_inc, i_limit; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1570 if (context->col_1 & 0x200) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1571 //hflip |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1572 i = 0; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1573 i_inc = 4; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1574 i_limit = 32; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1575 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1576 i = 28; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1577 i_inc = -4; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1578 i_limit = -4; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1579 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1580 uint8_t pal_priority = (context->col_1 >> 7 & 0x10) | (context->col_1 >> 6 & 0x40); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1581 for (uint8_t *dst = context->tmp_buf_a + context->buf_a_off; i != i_limit; i += i_inc, dst++) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1582 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1583 *dst = (pixels >> i & 0xF) | pal_priority; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1584 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1585 context->buf_a_off = (context->buf_a_off + 8) & 15; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1586 |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1587 uint8_t bgcolor = 0x10 | (context->regs[REG_BG_COLOR] & 0xF) + CRAM_SIZE*3; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1588 uint32_t *dst = context->output + col * 8; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1589 if (context->debug < 2) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1590 if (col || !(context->regs[REG_MODE_1] & BIT_COL0_MASK)) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1591 uint8_t *sprite_src = context->linebuf + col * 8; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1592 if (context->regs[REG_MODE_1] & BIT_SPRITE_8PX) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1593 sprite_src += 8; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1594 } |
1121
1913f9c28003
Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents:
1120
diff
changeset
|
1595 for (int i = 0; i < 8; i++, sprite_src++) |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1596 { |
1121
1913f9c28003
Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents:
1120
diff
changeset
|
1597 uint8_t *bg_src = context->tmp_buf_a + ((8 + i + col * 8 - (context->hscroll_a & 0x7)) & 15); |
1132
fd3b8ac57aca
Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents:
1127
diff
changeset
|
1598 if ((*bg_src & 0x4F) > 0x40 || !*sprite_src) { |
fd3b8ac57aca
Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents:
1127
diff
changeset
|
1599 //background plane has priority and is opaque or sprite layer is transparent |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1600 if (context->debug) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1601 *(dst++) = context->debugcolors[DBG_SRC_A]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1602 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1603 *(dst++) = context->colors[(*bg_src & 0x1F) + CRAM_SIZE*3]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1604 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1605 } else { |
1132
fd3b8ac57aca
Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents:
1127
diff
changeset
|
1606 //sprite layer is opaque and not covered by high priority BG pixels |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1607 if (context->debug) { |
1132
fd3b8ac57aca
Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents:
1127
diff
changeset
|
1608 *(dst++) = context->debugcolors[DBG_SRC_S]; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1609 } else { |
1132
fd3b8ac57aca
Fix rendering of BG color index 0 in Mode 4. Only transparent with respect to sprites and not the backdrop like in Mode 5
Michael Pavone <pavone@retrodev.com>
parents:
1127
diff
changeset
|
1610 *(dst++) = context->colors[*sprite_src | 0x10 + CRAM_SIZE*3]; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1611 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1612 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1613 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1614 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1615 for (int i = 0; i < 8; i++) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1616 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1617 *(dst++) = context->colors[bgcolor]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1618 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1619 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1620 } else if (context->debug == 2) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1621 for (int i = 0; i < 8; i++) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1622 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1623 *(dst++) = context->colors[CRAM_SIZE*3 + col]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1624 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1625 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1626 uint32_t cell = (line / 8) * 32 + col; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1627 uint32_t address = cell * 32 + (line % 8) * 4; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1628 uint32_t m4_address = mode4_address_map[address & 0x3FFF]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1629 uint32_t pixel = planar_to_chunky[context->vdpmem[m4_address]] << 1; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1630 pixel |= planar_to_chunky[context->vdpmem[m4_address + 1]]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1631 m4_address = mode4_address_map[(address + 2) & 0x3FFF]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1632 pixel |= planar_to_chunky[context->vdpmem[m4_address]] << 3; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1633 pixel |= planar_to_chunky[context->vdpmem[m4_address + 1]] << 2; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1634 if (context->debug_pal < 2) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1635 for (int i = 28; i >= 0; i -= 4) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1636 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1637 *(dst++) = context->colors[CRAM_SIZE*3 | (context->debug_pal << 4) | (pixel >> i & 0xF)]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1638 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1639 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1640 for (int i = 28; i >= 0; i -= 4) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1641 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1642 uint8_t value = (pixel >> i & 0xF) * 17; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1643 if (context->debug_pal == 3) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1644 value = 255 - value; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1645 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1646 *(dst++) = render_map_color(value, value, value); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1647 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1648 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1649 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1650 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1651 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1652 static uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19}; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1653 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
1654 static void vdp_advance_line(vdp_context *context) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1655 { |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1656 #ifdef TIMING_DEBUG |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1657 static uint32_t last_line = 0xFFFFFFFF; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1658 if (last_line != 0xFFFFFFFF) { |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1659 uint32_t diff = context->cycles - last_line; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1660 if (diff != MCLKS_LINE) { |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1661 printf("Line %d took %d cycles\n", context->vcounter, diff); |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1662 } |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1663 } |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1664 last_line = context->cycles; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1665 #endif |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1666 context->vcounter++; |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1667 |
1156
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1668 uint8_t is_mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5; |
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1669 if (is_mode_5) { |
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1670 if (context->flags2 & FLAG2_REGION_PAL) { |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1671 if (context->regs[REG_MODE_2] & BIT_PAL) { |
1156
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1672 if (context->vcounter == 0x10B) { |
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1673 context->vcounter = 0x1D2; |
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1674 } |
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1675 } else if (context->vcounter == 0x103){ |
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1676 context->vcounter = 0x1CA; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1677 } |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1678 } else { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1679 if (context->regs[REG_MODE_2] & BIT_PAL) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1680 if (context->vcounter == 0x100) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1681 context->vcounter = 0x1FA; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1682 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1683 } else if (context->vcounter == 0xEB) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1684 context->vcounter = 0x1E5; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1685 } |
1299
da1ffc4026c4
Fix latching of V32 mode bit
Michael Pavone <pavone@retrodev.com>
parents:
1290
diff
changeset
|
1686 } |
1156
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1687 } else if (context->vcounter == 0xDB) { |
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
1688 context->vcounter = 0x1D5; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1689 } |
1273
6dedaa645843
Fix graphical corruption and sprite flickering introduced into some games by the last change for horizontal border support
Michael Pavone <pavone@retrodev.com>
parents:
1272
diff
changeset
|
1690 context->vcounter &= 0x1FF; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1691 if (context->state == PREPARING) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1692 context->state = ACTIVE; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1693 } |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1694 |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1695 if (context->state != ACTIVE) { |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1696 context->hint_counter = context->regs[REG_HINT]; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1697 } else if (context->hint_counter) { |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1698 context->hint_counter--; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1699 } else { |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1700 context->flags2 |= FLAG2_HINT_PENDING; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1701 context->pending_hint_start = context->cycles; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1702 context->hint_counter = context->regs[REG_HINT]; |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1703 } |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1704 } |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1705 |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1706 static void advance_output_line(vdp_context *context) |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1707 { |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1708 if (headless) { |
1168 | 1709 if (context->vcounter == context->inactive_start) { |
1710 context->frame++; | |
1711 } | |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1712 context->vcounter &= 0x1FF; |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1713 } else { |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1714 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL) |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1715 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1716 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1717 |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1718 if (context->output_lines == lines_max) { |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
1719 render_framebuffer_updated(context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN: FRAMEBUFFER_ODD, context->h40_lines > (context->inactive_start + context->border_top) / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER)); |
1077
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
1720 if (context->double_res) { |
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
1721 context->flags2 ^= FLAG2_EVEN_FIELD; |
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
1722 } |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1723 context->fb = render_get_framebuffer(context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN : FRAMEBUFFER_ODD, &context->output_pitch); |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1724 context->h40_lines = 0; |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1725 context->frame++; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1726 context->output_lines = 0; |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1727 } |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1728 uint32_t output_line; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1729 if (context->vcounter < context->inactive_start + context->border_bot && context->output_lines > 0) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1730 output_line = context->output_lines++;//context->border_top + context->vcounter; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1731 } else if (context->vcounter >= 0x200 - context->border_top) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1732 output_line = context->output_lines++;//context->vcounter - (0x200 - context->border_top); |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1733 } else { |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1734 output_line = INVALID_LINE; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
1735 } |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1736 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * output_line); |
1271
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
1737 #ifdef DEBUG_FB_FILL |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
1738 for (int i = 0; i < LINEBUF_SIZE; i++) |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
1739 { |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
1740 context->output[i] = 0xFFFF00FF; |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
1741 } |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1742 #endif |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1743 if (output_line != INVALID_LINE && (context->regs[REG_MODE_4] & BIT_H40)) { |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
1744 context->h40_lines++; |
1077
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
1745 } |
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
1746 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1747 } |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1748 |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1749 static void render_border_garbage(vdp_context *context, uint32_t address, uint8_t *buf, uint8_t buf_off, uint16_t col) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1750 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1751 uint8_t base = col >> 9 & 0x30; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1752 for (int i = 0; i < 4; i++, address++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1753 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1754 uint8_t byte = context->vdpmem[address & 0xFFFF]; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1755 buf[(buf_off++) & SCROLL_BUFFER_MASK] = base | byte >> 4; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1756 buf[(buf_off++) & SCROLL_BUFFER_MASK] = base | byte & 0xF; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1757 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1758 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1759 |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1760 static void draw_right_border(vdp_context *context) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1761 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1762 uint32_t *dst = context->output + BORDER_LEFT + ((context->regs[REG_MODE_4] & BIT_H40) ? 320 : 256); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1763 uint8_t pixel = context->regs[REG_BG_COLOR] & 0x3F; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1764 if ((context->test_port & TEST_BIT_DISABLE) != 0) { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1765 pixel = 0x3F; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1766 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1767 uint32_t bg_color = context->colors[pixel]; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1768 uint8_t test_layer = context->test_port >> 7 & 3; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1769 if (test_layer) { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1770 switch(test_layer) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1771 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1772 case 1: |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1773 //TODO: Display garbage from bus? |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1774 for (int i = 0; i < BORDER_RIGHT; i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1775 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1776 *dst = bg_color; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1777 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1778 break; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1779 case 2: { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1780 //plane A |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1781 //TODO: Deal with Window layer |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1782 int i; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1783 /*for (i = 0; i < (context->hscroll_a & 0xF) - (16 - BORDER_LEFT); i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1784 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1785 *dst = bg_color; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1786 }*/ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1787 i = 0; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1788 uint8_t buf_off = context->buf_a_off - (context->hscroll_a & 0xF); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1789 //uint8_t *src = context->tmp_buf_a + ((context->buf_a_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_a & 0xF))) & SCROLL_BUFFER_MASK); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1790 for (; i < BORDER_RIGHT; buf_off++, i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1791 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1792 *dst = context->colors[context->tmp_buf_a[buf_off & SCROLL_BUFFER_MASK] & 0x3F]; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1793 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1794 break; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1795 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1796 case 3: { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1797 //plane B |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1798 int i; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1799 /*for (i = 0; i < (context->hscroll_b & 0xF) - (16 - BORDER_LEFT); i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1800 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1801 *dst = bg_color; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1802 }*/ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1803 i = 0; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1804 uint8_t buf_off = context->buf_b_off - (context->hscroll_b & 0xF); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1805 //uint8_t *src = context->tmp_buf_b + ((context->buf_b_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_b & 0xF))) & SCROLL_BUFFER_MASK); |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1806 for (; i < BORDER_RIGHT; buf_off++, i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1807 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1808 *dst = context->colors[context->tmp_buf_b[buf_off & SCROLL_BUFFER_MASK] & 0x3F]; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1809 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1810 break; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1811 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1812 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1813 } else { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1814 for (int i = 0; i < BORDER_RIGHT; i++, dst++) |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1815 { |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1816 *dst = bg_color; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1817 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1818 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1819 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1820 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1821 } |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1822 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1823 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; } |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
1824 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1825 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1826 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1827 case startcyc:\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1828 read_map_scroll_a(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1829 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1830 case ((startcyc+1)&0xFF):\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1831 external_slot(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1832 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1833 case ((startcyc+2)&0xFF):\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1834 render_map_1(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1835 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1836 case ((startcyc+3)&0xFF):\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1837 render_map_2(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1838 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1839 case ((startcyc+4)&0xFF):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1840 read_map_scroll_b(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1841 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1842 case ((startcyc+5)&0xFF):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1843 read_sprite_x(context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1844 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1845 case ((startcyc+6)&0xFF):\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1846 render_map_3(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1847 CHECK_LIMIT\ |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
1848 case ((startcyc+7)&0xFF):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1849 render_map_output(context->vcounter, column, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1850 CHECK_LIMIT |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1851 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1852 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1853 case startcyc:\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1854 read_map_scroll_a(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1855 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1856 case (startcyc+1):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1857 /* refresh, no don't run dma src */\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1858 context->hslot++;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1859 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1860 CHECK_ONLY\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1861 case (startcyc+2):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1862 render_map_1(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1863 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1864 case (startcyc+3):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1865 render_map_2(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1866 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1867 case (startcyc+4):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1868 read_map_scroll_b(column, context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1869 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1870 case (startcyc+5):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1871 read_sprite_x(context->vcounter, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1872 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1873 case (startcyc+6):\ |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1874 render_map_3(context);\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1875 CHECK_LIMIT\ |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1876 case (startcyc+7):\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1877 render_map_output(context->vcounter, column, context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1878 CHECK_LIMIT |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1879 |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1880 #define COLUMN_RENDER_BLOCK_MODE4(column, startcyc) \ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1881 case startcyc:\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1882 read_map_mode4(column, context->vcounter, context);\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1883 CHECK_LIMIT\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1884 case ((startcyc+1)&0xFF):\ |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
1885 if (column & 3) {\ |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
1886 scan_sprite_table_mode4(context);\ |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1887 } else {\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1888 external_slot(context);\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1889 }\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1890 CHECK_LIMIT\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1891 case ((startcyc+2)&0xFF):\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1892 fetch_map_mode4(column, context->vcounter, context);\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1893 CHECK_LIMIT\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1894 case ((startcyc+3)&0xFF):\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1895 render_map_mode4(context->vcounter, column, context);\ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1896 CHECK_LIMIT |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1897 |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1898 #define CHECK_LIMIT_HSYNC(slot) \ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1899 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1900 if (slot >= HSYNC_SLOT_H40 && slot < HSYNC_END_H40) {\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1901 context->cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1902 } else {\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1903 context->cycles += slot_cycles;\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1904 }\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1905 if (slot == 182) {\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1906 context->hslot = 229;\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1907 } else {\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1908 context->hslot++;\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1909 }\ |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1910 CHECK_ONLY |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1911 |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1912 #define SPRITE_RENDER_H40(slot) \ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1913 case slot:\ |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1914 if ((slot) == BG_START_SLOT + LINEBUF_SIZE/2) {\ |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1915 advance_output_line(context);\ |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1916 }\ |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1917 if (slot == 168 || slot == 247 || slot == 248) {\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1918 render_border_garbage(\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1919 context,\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1920 context->sprite_draw_list[context->cur_slot].address,\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1921 context->tmp_buf_b,\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1922 context->buf_b_off + (slot == 247 ? 0 : 8),\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1923 slot == 247 ? context->col_1 : context->col_2\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1924 );\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1925 if (slot == 248) {\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1926 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1927 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1928 }\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1929 } else if (slot == 243) {\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1930 render_border_garbage(\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1931 context,\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1932 context->sprite_draw_list[context->cur_slot].address,\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1933 context->tmp_buf_a,\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1934 context->buf_a_off,\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1935 context->col_1\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1936 );\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1937 } else if (slot == 169) {\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1938 draw_right_border(context);\ |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
1939 }\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1940 render_sprite_cells( context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1941 scan_sprite_table(context->vcounter, context);\ |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
1942 CHECK_LIMIT_HSYNC(slot) |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
822
diff
changeset
|
1943 |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1944 //Note that the line advancement check will fail if BG_START_SLOT is > 6 |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1945 //as we're bumping up against the hcounter jump |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1946 #define SPRITE_RENDER_H32(slot) \ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1947 case slot:\ |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1948 if ((slot) == BG_START_SLOT + (256+HORIZ_BORDER)/2) {\ |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1949 advance_output_line(context);\ |
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
1950 }\ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1951 render_sprite_cells( context);\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1952 scan_sprite_table(context->vcounter, context);\ |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
1953 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \ |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1954 if (slot == 147) {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1955 context->hslot = 233;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1956 } else {\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1957 context->hslot++;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1958 }\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1959 context->cycles += slot_cycles;\ |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
1960 CHECK_ONLY |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1961 |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1962 #define MODE4_CHECK_SLOT_LINE(slot) \ |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1963 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \ |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1964 if ((slot) == 147) {\ |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1965 context->hslot = 233;\ |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1966 } else {\ |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1967 context->hslot++;\ |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1968 }\ |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1969 context->cycles += slot_cycles;\ |
1163
b251899f2b97
Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents:
1161
diff
changeset
|
1970 if ((slot+1) == LINE_CHANGE_MODE4) {\ |
b251899f2b97
Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents:
1161
diff
changeset
|
1971 vdp_advance_line(context);\ |
b251899f2b97
Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents:
1161
diff
changeset
|
1972 if (context->vcounter == 192) {\ |
b251899f2b97
Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents:
1161
diff
changeset
|
1973 return;\ |
b251899f2b97
Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents:
1161
diff
changeset
|
1974 }\ |
b251899f2b97
Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents:
1161
diff
changeset
|
1975 }\ |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1976 CHECK_ONLY |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1977 |
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1978 #define CALC_SLOT(slot, increment) ((slot+increment) > 147 && (slot+increment) < 233 ? (slot+increment-148+233): (slot+increment)) |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1979 |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1980 #define SPRITE_RENDER_H32_MODE4(slot) \ |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1981 case slot:\ |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
1982 read_sprite_x_mode4(context);\ |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
1983 MODE4_CHECK_SLOT_LINE(slot)\ |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1984 case CALC_SLOT(slot, 1):\ |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
1985 read_sprite_x_mode4(context);\ |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1986 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot,1))\ |
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1987 case CALC_SLOT(slot, 2):\ |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1988 fetch_sprite_cells_mode4(context);\ |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1989 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 2))\ |
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1990 case CALC_SLOT(slot, 3):\ |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
1991 render_sprite_cells_mode4(context);\ |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1992 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 3))\ |
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1993 case CALC_SLOT(slot, 4):\ |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
1994 fetch_sprite_cells_mode4(context);\ |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1995 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 4))\ |
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1996 case CALC_SLOT(slot, 5):\ |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
1997 render_sprite_cells_mode4(context);\ |
1161
c2210d586950
A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents:
1160
diff
changeset
|
1998 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 5)) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1999 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
2000 static void vdp_h40(vdp_context * context, uint32_t target_cycles) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2001 { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2002 uint16_t address; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2003 uint32_t mask; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2004 uint32_t const slot_cycles = MCLKS_SLOT_H40; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2005 switch(context->hslot) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2006 { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2007 for (;;) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2008 { |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2009 case 165: |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2010 if (context->state == PREPARING) { |
1185
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2011 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2012 uint32_t *dst; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2013 if (headless) { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2014 dst = context->output; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2015 } else { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2016 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2))) |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2017 + (context->hslot - BG_START_SLOT) * 2; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2018 } |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2019 *(dst++) = bg_color; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2020 *dst = bg_color; |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2021 external_slot(context); |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2022 } else { |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2023 render_sprite_cells(context); |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2024 } |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2025 CHECK_LIMIT |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2026 case 166: |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2027 if (context->state == PREPARING) { |
1185
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2028 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2029 uint32_t *dst; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2030 if (headless) { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2031 dst = context->output; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2032 } else { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2033 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2))) |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2034 + (context->hslot - BG_START_SLOT) * 2; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2035 } |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2036 *(dst++) = bg_color; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2037 *dst = bg_color; |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2038 external_slot(context); |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2039 } else { |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2040 render_sprite_cells(context); |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2041 } |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2042 CHECK_LIMIT |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2043 //sprite attribute table scan starts |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2044 case 167: |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2045 if (context->state == PREPARING) { |
1185
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2046 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2047 uint32_t *dst; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2048 if (headless) { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2049 dst = context->output; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2050 } else { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2051 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2))) |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2052 + (context->hslot - BG_START_SLOT) * 2; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2053 } |
1271
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
2054 for (int i = 0; i < LINEBUF_SIZE - 2 * (context->hslot - BG_START_SLOT); i++) |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
2055 { |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
2056 *(dst++) = bg_color; |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
2057 } |
1185
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2058 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2059 context->sprite_index = 0x80; |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2060 context->slot_counter = 0; |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2061 render_border_garbage( |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2062 context, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2063 context->sprite_draw_list[context->cur_slot].address, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2064 context->tmp_buf_b, context->buf_b_off, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2065 context->col_1 |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2066 ); |
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
2067 render_sprite_cells( context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2068 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2069 CHECK_LIMIT |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2070 SPRITE_RENDER_H40(168) |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2071 SPRITE_RENDER_H40(169) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2072 SPRITE_RENDER_H40(170) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2073 SPRITE_RENDER_H40(171) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2074 SPRITE_RENDER_H40(172) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2075 SPRITE_RENDER_H40(173) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2076 SPRITE_RENDER_H40(174) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2077 SPRITE_RENDER_H40(175) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2078 SPRITE_RENDER_H40(176) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2079 SPRITE_RENDER_H40(177) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2080 SPRITE_RENDER_H40(178) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2081 SPRITE_RENDER_H40(179) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2082 SPRITE_RENDER_H40(180) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2083 SPRITE_RENDER_H40(181) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2084 SPRITE_RENDER_H40(182) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2085 SPRITE_RENDER_H40(229) |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2086 //!HSYNC asserted |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2087 SPRITE_RENDER_H40(230) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2088 SPRITE_RENDER_H40(231) |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2089 case 232: |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2090 external_slot(context); |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2091 CHECK_LIMIT_HSYNC(232) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2092 SPRITE_RENDER_H40(233) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2093 SPRITE_RENDER_H40(234) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2094 SPRITE_RENDER_H40(235) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2095 SPRITE_RENDER_H40(236) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2096 SPRITE_RENDER_H40(237) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2097 SPRITE_RENDER_H40(238) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2098 SPRITE_RENDER_H40(239) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2099 SPRITE_RENDER_H40(240) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2100 SPRITE_RENDER_H40(241) |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2101 SPRITE_RENDER_H40(242) |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2102 SPRITE_RENDER_H40(243) //provides "garbage" for border when plane A selected |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2103 case 244: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2104 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2105 mask = 0; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2106 if (context->regs[REG_MODE_3] & 0x2) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2107 mask |= 0xF8; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2108 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2109 if (context->regs[REG_MODE_3] & 0x1) { |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2110 mask |= 0x7; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2111 } |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2112 render_border_garbage(context, address, context->tmp_buf_a, context->buf_a_off+8, context->col_2); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2113 address += (context->vcounter & mask) * 4; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2114 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2115 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2116 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b); |
924
1b86268a4cb3
Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents:
923
diff
changeset
|
2117 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2118 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2119 context->cycles += h40_hsync_cycles[14]; |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2120 CHECK_ONLY //provides "garbage" for border when plane A selected |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2121 //!HSYNC high |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2122 SPRITE_RENDER_H40(245) |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2123 SPRITE_RENDER_H40(246) |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2124 SPRITE_RENDER_H40(247) //provides "garbage" for border when plane B selected |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2125 SPRITE_RENDER_H40(248) //provides "garbage" for border when plane B selected |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2126 case 249: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2127 read_map_scroll_a(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2128 CHECK_LIMIT |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2129 SPRITE_RENDER_H40(250) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2130 case 251: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2131 render_map_1(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2132 scan_sprite_table(context->vcounter, context);//Just a guess |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2133 CHECK_LIMIT |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2134 case 252: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2135 render_map_2(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2136 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2137 CHECK_LIMIT |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2138 case 253: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2139 read_map_scroll_b(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2140 CHECK_LIMIT |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2141 SPRITE_RENDER_H40(254) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2142 case 255: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2143 render_map_3(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2144 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2145 CHECK_LIMIT |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2146 case 0: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2147 render_map_output(context->vcounter, 0, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2148 scan_sprite_table(context->vcounter, context);//Just a guess |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2149 //seems like the sprite table scan fills a shift register |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2150 //values are FIFO, but unused slots precede used slots |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2151 //so we set cur_slot to slot_counter and let it wrap around to |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2152 //the beginning of the list |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2153 context->cur_slot = context->slot_counter; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2154 context->sprite_draws = MAX_DRAWS; |
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
2155 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2156 CHECK_LIMIT |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2157 COLUMN_RENDER_BLOCK(2, 1) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2158 COLUMN_RENDER_BLOCK(4, 9) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2159 COLUMN_RENDER_BLOCK(6, 17) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2160 COLUMN_RENDER_BLOCK_REFRESH(8, 25) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2161 COLUMN_RENDER_BLOCK(10, 33) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2162 COLUMN_RENDER_BLOCK(12, 41) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2163 COLUMN_RENDER_BLOCK(14, 49) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2164 COLUMN_RENDER_BLOCK_REFRESH(16, 57) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2165 COLUMN_RENDER_BLOCK(18, 65) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2166 COLUMN_RENDER_BLOCK(20, 73) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2167 COLUMN_RENDER_BLOCK(22, 81) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2168 COLUMN_RENDER_BLOCK_REFRESH(24, 89) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2169 COLUMN_RENDER_BLOCK(26, 97) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2170 COLUMN_RENDER_BLOCK(28, 105) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2171 COLUMN_RENDER_BLOCK(30, 113) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2172 COLUMN_RENDER_BLOCK_REFRESH(32, 121) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2173 COLUMN_RENDER_BLOCK(34, 129) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2174 COLUMN_RENDER_BLOCK(36, 137) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2175 COLUMN_RENDER_BLOCK(38, 145) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2176 COLUMN_RENDER_BLOCK_REFRESH(40, 153) |
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2177 case 161: |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2178 external_slot(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2179 CHECK_LIMIT |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2180 case 162: { |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2181 external_slot(context); |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2182 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2183 for (int i = LINEBUF_SIZE-BORDER_RIGHT; i < LINEBUF_SIZE; i++) |
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2184 { |
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2185 context->output[i] = bg_color; |
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2186 } |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2187 CHECK_LIMIT |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2188 } |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2189 //sprite render to line buffer starts |
1157
d5dda22ae6b4
Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents:
1156
diff
changeset
|
2190 case 163: |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2191 context->cur_slot = MAX_DRAWS-1; |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2192 memset(context->linebuf, 0, LINEBUF_SIZE); |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2193 render_border_garbage( |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2194 context, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2195 context->sprite_draw_list[context->cur_slot].address, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2196 context->tmp_buf_a, context->buf_a_off, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2197 context->col_1 |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2198 ); |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2199 render_sprite_cells(context); |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2200 CHECK_LIMIT |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2201 case 164: |
1337
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2202 render_border_garbage( |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2203 context, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2204 context->sprite_draw_list[context->cur_slot].address, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2205 context->tmp_buf_a, context->buf_a_off + 8, |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2206 context->col_2 |
d092c15246a3
Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents:
1335
diff
changeset
|
2207 ); |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2208 render_sprite_cells(context); |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2209 if (context->flags & FLAG_DMA_RUN) { |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2210 run_dma_src(context, -1); |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2211 } |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2212 context->hslot++; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2213 context->cycles += slot_cycles; |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2214 vdp_advance_line(context); |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2215 if (context->vcounter == context->inactive_start) { |
922
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2216 return; |
913a6336ce20
Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents:
921
diff
changeset
|
2217 } |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2218 CHECK_ONLY |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2219 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2220 default: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2221 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2222 context->cycles += slot_cycles; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2223 return; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2224 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2225 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2226 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
2227 static void vdp_h32(vdp_context * context, uint32_t target_cycles) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2228 { |
37 | 2229 uint16_t address; |
2230 uint32_t mask; | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2231 uint32_t const slot_cycles = MCLKS_SLOT_H32; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2232 switch(context->hslot) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2233 { |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2234 for (;;) |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2235 { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2236 case 133: |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2237 if (context->state == PREPARING) { |
1185
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2238 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2239 uint32_t *dst; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2240 if (headless) { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2241 dst = context->output; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2242 } else { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2243 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2))) |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2244 + (context->hslot - BG_START_SLOT) * 2; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2245 } |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2246 *(dst++) = bg_color; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2247 *dst = bg_color; |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2248 external_slot(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2249 } else { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2250 render_sprite_cells(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2251 } |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2252 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2253 case 134: |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2254 if (context->state == PREPARING) { |
1185
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2255 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2256 uint32_t *dst; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2257 if (headless) { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2258 dst = context->output; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2259 } else { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2260 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2))) |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2261 + (context->hslot - BG_START_SLOT) * 2; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2262 } |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2263 *(dst++) = bg_color; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2264 *dst = bg_color; |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2265 external_slot(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2266 } else { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2267 render_sprite_cells(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2268 } |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2269 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2270 //sprite attribute table scan starts |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2271 case 135: //FIXME - Here |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2272 if (context->state == PREPARING) { |
1185
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2273 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2274 uint32_t *dst; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2275 if (headless) { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2276 dst = context->output; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2277 } else { |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2278 dst = ((uint32_t *)(((char *)context->fb) + context->output_pitch * (context->border_top - 2))) |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2279 + (context->hslot - BG_START_SLOT) * 2; |
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2280 } |
1271
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
2281 for (int i = 0; i < (256+HORIZ_BORDER) - 2 * (context->hslot - BG_START_SLOT); i++) |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
2282 { |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
2283 *(dst++) = bg_color; |
c865ee5478bc
Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents:
1270
diff
changeset
|
2284 } |
1185
9de9d2c6ebe5
Fix border rendering at end of line 1FE. vdp_inactive will probably need a small fixup for the edge case when we start between when the vcounter is incremented and the line is truly finished.
Michael Pavone <pavone@retrodev.com>
parents:
1183
diff
changeset
|
2285 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2286 context->sprite_index = 0x80; |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2287 context->slot_counter = 0; |
37 | 2288 render_sprite_cells( context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2289 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2290 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2291 SPRITE_RENDER_H32(136) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2292 SPRITE_RENDER_H32(137) |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2293 SPRITE_RENDER_H32(138) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2294 SPRITE_RENDER_H32(139) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2295 SPRITE_RENDER_H32(140) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2296 SPRITE_RENDER_H32(141) |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2297 SPRITE_RENDER_H32(142) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2298 SPRITE_RENDER_H32(143) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2299 SPRITE_RENDER_H32(144) |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2300 case 145: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2301 external_slot(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2302 CHECK_LIMIT |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2303 SPRITE_RENDER_H32(146) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2304 SPRITE_RENDER_H32(147) |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2305 SPRITE_RENDER_H32(233) |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2306 SPRITE_RENDER_H32(234) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2307 SPRITE_RENDER_H32(235) |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2308 //HSYNC start |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2309 SPRITE_RENDER_H32(236) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2310 SPRITE_RENDER_H32(237) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2311 SPRITE_RENDER_H32(238) |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2312 SPRITE_RENDER_H32(239) |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2313 SPRITE_RENDER_H32(240) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2314 SPRITE_RENDER_H32(241) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2315 SPRITE_RENDER_H32(242) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2316 case 243: |
37 | 2317 external_slot(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2318 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2319 case 244: |
37 | 2320 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
2321 mask = 0; | |
2322 if (context->regs[REG_MODE_3] & 0x2) { | |
2323 mask |= 0xF8; | |
2324 } | |
2325 if (context->regs[REG_MODE_3] & 0x1) { | |
2326 mask |= 0x7; | |
2327 } | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2328 address += (context->vcounter & mask) * 4; |
37 | 2329 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
2330 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2331 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2332 CHECK_LIMIT |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2333 SPRITE_RENDER_H32(245) |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2334 SPRITE_RENDER_H32(246) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2335 SPRITE_RENDER_H32(247) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2336 SPRITE_RENDER_H32(248) |
37 | 2337 //!HSYNC high |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2338 case 249: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2339 read_map_scroll_a(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2340 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2341 SPRITE_RENDER_H32(250) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2342 case 251: |
37 | 2343 render_map_1(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2344 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2345 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2346 case 252: |
37 | 2347 render_map_2(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2348 scan_sprite_table(context->vcounter, context);//Just a guess |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2349 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2350 case 253: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2351 read_map_scroll_b(0, context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2352 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2353 case 254: |
37 | 2354 render_sprite_cells(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2355 scan_sprite_table(context->vcounter, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2356 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2357 case 255: |
37 | 2358 render_map_3(context); |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2359 scan_sprite_table(context->vcounter, context);//Just a guess |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2360 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2361 case 0: |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2362 render_map_output(context->vcounter, 0, context); |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2363 scan_sprite_table(context->vcounter, context);//Just a guess |
37 | 2364 //reverse context slot counter so it counts the number of sprite slots |
2365 //filled rather than the number of available slots | |
2366 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2367 context->cur_slot = context->slot_counter; |
37 | 2368 context->sprite_draws = MAX_DRAWS_H32; |
2369 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2370 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2371 COLUMN_RENDER_BLOCK(2, 1) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2372 COLUMN_RENDER_BLOCK(4, 9) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2373 COLUMN_RENDER_BLOCK(6, 17) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2374 COLUMN_RENDER_BLOCK_REFRESH(8, 25) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2375 COLUMN_RENDER_BLOCK(10, 33) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2376 COLUMN_RENDER_BLOCK(12, 41) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2377 COLUMN_RENDER_BLOCK(14, 49) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2378 COLUMN_RENDER_BLOCK_REFRESH(16, 57) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2379 COLUMN_RENDER_BLOCK(18, 65) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2380 COLUMN_RENDER_BLOCK(20, 73) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2381 COLUMN_RENDER_BLOCK(22, 81) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2382 COLUMN_RENDER_BLOCK_REFRESH(24, 89) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2383 COLUMN_RENDER_BLOCK(26, 97) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2384 COLUMN_RENDER_BLOCK(28, 105) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2385 COLUMN_RENDER_BLOCK(30, 113) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2386 COLUMN_RENDER_BLOCK_REFRESH(32, 121) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2387 case 129: |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2388 external_slot(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2389 CHECK_LIMIT |
1269
ff8e29eeb1ec
Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents:
1267
diff
changeset
|
2390 case 130: { |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2391 external_slot(context); |
1269
ff8e29eeb1ec
Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents:
1267
diff
changeset
|
2392 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
ff8e29eeb1ec
Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents:
1267
diff
changeset
|
2393 for (int i = 256+BORDER_LEFT; i < 256+HORIZ_BORDER; i++) |
ff8e29eeb1ec
Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents:
1267
diff
changeset
|
2394 { |
ff8e29eeb1ec
Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents:
1267
diff
changeset
|
2395 context->output[i] = bg_color; |
ff8e29eeb1ec
Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents:
1267
diff
changeset
|
2396 } |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2397 CHECK_LIMIT |
1269
ff8e29eeb1ec
Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents:
1267
diff
changeset
|
2398 } |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2399 //sprite render to line buffer starts |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2400 case 131: |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2401 context->cur_slot = MAX_DRAWS_H32-1; |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2402 memset(context->linebuf, 0, LINEBUF_SIZE); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2403 render_sprite_cells(context); |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2404 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2405 case 132: |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2406 render_sprite_cells(context); |
1173
d0f67c59b756
Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1172
diff
changeset
|
2407 if (context->flags & FLAG_DMA_RUN) { |
d0f67c59b756
Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1172
diff
changeset
|
2408 run_dma_src(context, -1); |
d0f67c59b756
Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1172
diff
changeset
|
2409 } |
d0f67c59b756
Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1172
diff
changeset
|
2410 context->hslot++; |
d0f67c59b756
Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1172
diff
changeset
|
2411 context->cycles += slot_cycles; |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2412 vdp_advance_line(context); |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2413 if (context->vcounter == context->inactive_start) { |
923
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2414 return; |
8e012ece95c1
Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents:
922
diff
changeset
|
2415 } |
1173
d0f67c59b756
Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1172
diff
changeset
|
2416 CHECK_ONLY |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2417 } |
822
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2418 default: |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2419 context->hslot++; |
ac65086c031e
Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents:
771
diff
changeset
|
2420 context->cycles += MCLKS_SLOT_H32; |
503
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
2421 } |
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
2422 } |
eee6be465c47
Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
499
diff
changeset
|
2423 |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2424 static void vdp_h32_mode4(vdp_context * context, uint32_t target_cycles) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2425 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2426 uint16_t address; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2427 uint32_t mask; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2428 uint32_t const slot_cycles = MCLKS_SLOT_H32; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2429 switch(context->hslot) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2430 { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2431 for (;;) |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2432 { |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2433 //sprite rendering starts |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2434 SPRITE_RENDER_H32_MODE4(137) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2435 SPRITE_RENDER_H32_MODE4(143) |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2436 case 234: |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2437 external_slot(context); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2438 CHECK_LIMIT |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2439 case 235: |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2440 external_slot(context); |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2441 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2442 //!HSYNC low |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2443 case 236: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2444 external_slot(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2445 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2446 case 237: |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2447 external_slot(context); |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2448 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2449 case 238: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2450 external_slot(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2451 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2452 SPRITE_RENDER_H32_MODE4(239) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2453 SPRITE_RENDER_H32_MODE4(245) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2454 case 251: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2455 external_slot(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2456 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2457 case 252: |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2458 external_slot(context); |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2459 if (context->regs[REG_MODE_1] & BIT_HSCRL_LOCK && context->vcounter < 16) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2460 context->hscroll_a = 0; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2461 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2462 context->hscroll_a = context->regs[REG_X_SCROLL]; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2463 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2464 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2465 case 253: |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2466 context->sprite_index = 0; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2467 context->slot_counter = MAX_DRAWS_H32_MODE4; |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2468 scan_sprite_table_mode4(context); |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2469 CHECK_LIMIT |
1135
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2470 case 254: |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2471 scan_sprite_table_mode4(context); |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2472 CHECK_LIMIT |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2473 case 255: |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2474 scan_sprite_table_mode4(context); |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2475 CHECK_LIMIT |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2476 case 0: |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2477 scan_sprite_table_mode4(context); |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2478 CHECK_LIMIT |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2479 case 1: |
8506b305e0e8
Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents:
1134
diff
changeset
|
2480 scan_sprite_table_mode4(context); |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2481 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2482 case 2: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2483 scan_sprite_table_mode4(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2484 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2485 case 3: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2486 scan_sprite_table_mode4(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2487 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2488 case 4: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2489 scan_sprite_table_mode4(context); |
1121
1913f9c28003
Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents:
1120
diff
changeset
|
2490 context->buf_a_off = 8; |
1913f9c28003
Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents:
1120
diff
changeset
|
2491 memset(context->tmp_buf_a, 0, 8); |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2492 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2493 COLUMN_RENDER_BLOCK_MODE4(0, 5) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2494 COLUMN_RENDER_BLOCK_MODE4(1, 9) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2495 COLUMN_RENDER_BLOCK_MODE4(2, 13) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2496 COLUMN_RENDER_BLOCK_MODE4(3, 17) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2497 COLUMN_RENDER_BLOCK_MODE4(4, 21) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2498 COLUMN_RENDER_BLOCK_MODE4(5, 25) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2499 COLUMN_RENDER_BLOCK_MODE4(6, 29) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2500 COLUMN_RENDER_BLOCK_MODE4(7, 33) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2501 COLUMN_RENDER_BLOCK_MODE4(8, 37) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2502 COLUMN_RENDER_BLOCK_MODE4(9, 41) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2503 COLUMN_RENDER_BLOCK_MODE4(10, 45) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2504 COLUMN_RENDER_BLOCK_MODE4(11, 49) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2505 COLUMN_RENDER_BLOCK_MODE4(12, 53) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2506 COLUMN_RENDER_BLOCK_MODE4(13, 57) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2507 COLUMN_RENDER_BLOCK_MODE4(14, 61) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2508 COLUMN_RENDER_BLOCK_MODE4(15, 65) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2509 COLUMN_RENDER_BLOCK_MODE4(16, 69) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2510 COLUMN_RENDER_BLOCK_MODE4(17, 73) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2511 COLUMN_RENDER_BLOCK_MODE4(18, 77) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2512 COLUMN_RENDER_BLOCK_MODE4(19, 81) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2513 COLUMN_RENDER_BLOCK_MODE4(20, 85) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2514 COLUMN_RENDER_BLOCK_MODE4(21, 89) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2515 COLUMN_RENDER_BLOCK_MODE4(22, 93) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2516 COLUMN_RENDER_BLOCK_MODE4(23, 97) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2517 COLUMN_RENDER_BLOCK_MODE4(24, 101) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2518 COLUMN_RENDER_BLOCK_MODE4(25, 105) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2519 COLUMN_RENDER_BLOCK_MODE4(26, 109) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2520 COLUMN_RENDER_BLOCK_MODE4(27, 113) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2521 COLUMN_RENDER_BLOCK_MODE4(28, 117) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2522 COLUMN_RENDER_BLOCK_MODE4(29, 121) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2523 COLUMN_RENDER_BLOCK_MODE4(30, 125) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2524 COLUMN_RENDER_BLOCK_MODE4(31, 129) |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2525 case 133: |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2526 external_slot(context); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2527 CHECK_LIMIT |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2528 case 134: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2529 external_slot(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2530 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2531 case 135: |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2532 external_slot(context); |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2533 CHECK_LIMIT |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2534 case 136: |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2535 external_slot(context); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2536 //set things up for sprite rendering in the next slot |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2537 memset(context->linebuf, 0, LINEBUF_SIZE); |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2538 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
2539 context->sprite_draws = MAX_DRAWS_H32_MODE4; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2540 CHECK_LIMIT |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2541 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2542 default: |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2543 context->hslot++; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2544 context->cycles += MCLKS_SLOT_H32; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2545 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2546 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2547 |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2548 static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2549 { |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2550 uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2551 uint8_t index_reset_value, max_draws, max_sprites; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2552 uint16_t vint_line, active_line; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2553 uint32_t bg_color; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2554 |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2555 if (mode_5) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2556 if (is_h40) { |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2557 buf_clear_slot = 163; |
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2558 index_reset_slot = 167; |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2559 bg_end_slot = BG_START_SLOT + LINEBUF_SIZE/2; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2560 max_draws = MAX_DRAWS-1; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2561 max_sprites = MAX_SPRITES_LINE; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2562 index_reset_value = 0x80; |
1174
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
2563 vint_slot = VINT_SLOT_H40; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2564 line_change = LINE_CHANGE_H40; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2565 jump_start = 182; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2566 jump_dest = 229; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2567 } else { |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2568 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2569 max_draws = MAX_DRAWS_H32-1; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2570 max_sprites = MAX_SPRITES_LINE_H32; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2571 buf_clear_slot = 128; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2572 index_reset_slot = 132; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2573 index_reset_value = 0x80; |
1174
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
2574 vint_slot = VINT_SLOT_H32; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2575 line_change = LINE_CHANGE_H32; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2576 jump_start = 147; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2577 jump_dest = 233; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2578 } |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2579 vint_line = context->inactive_start; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2580 active_line = 0x1FF; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2581 } else { |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2582 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2583 max_draws = MAX_DRAWS_H32_MODE4; |
1278
34d3cb05014d
Fix VDP buffer overrun that was causing sprite flickering in some games
Michael Pavone <pavone@retrodev.com>
parents:
1273
diff
changeset
|
2584 max_sprites = 8; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2585 buf_clear_slot = 136; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2586 index_reset_slot = 253; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2587 index_reset_value = 0; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2588 vint_line = context->inactive_start + 1; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2589 vint_slot = VINT_SLOT_MODE4; |
1177
67e0462c30ce
Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency
Michael Pavone <pavone@retrodev.com>
parents:
1175
diff
changeset
|
2590 line_change = LINE_CHANGE_MODE4; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2591 bg_color = render_map_color(0, 0, 0); |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2592 jump_start = 147; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2593 jump_dest = 233; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2594 if (context->regs[REG_MODE_1] & BIT_MODE_4) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2595 //FIXME: This is actually 0x1FF like in Mode 5 |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2596 active_line = 0; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2597 } else { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2598 //never active unless either mode 4 or mode 5 is turned on |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2599 active_line = 0x200; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2600 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2601 } |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2602 uint32_t *dst = ( |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2603 context->vcounter < context->inactive_start + context->border_bot |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2604 || context->vcounter > 0x200 - context->border_top |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2605 ) && context->hslot >= BG_START_SLOT && context->hslot < bg_end_slot |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2606 ? context->output + 2 * (context->hslot - BG_START_SLOT) |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2607 : NULL; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2608 |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2609 while(context->cycles < target_cycles) |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2610 { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2611 if (context->hslot == BG_START_SLOT && ( |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2612 context->vcounter < context->inactive_start + context->border_bot |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2613 || context->vcounter > 0x200 - context->border_top |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2614 )) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2615 dst = context->output + (context->hslot - BG_START_SLOT) * 2; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2616 } else if (context->hslot == bg_end_slot) { |
1272
be509813b2f2
Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents:
1271
diff
changeset
|
2617 advance_output_line(context); |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2618 dst = NULL; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2619 } |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2620 |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2621 if (context->hslot == buf_clear_slot) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2622 if (mode_5) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2623 context->cur_slot = max_draws; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2624 } else { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2625 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2626 context->sprite_draws = MAX_DRAWS_H32_MODE4; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2627 } |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2628 memset(context->linebuf, 0, LINEBUF_SIZE); |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2629 } else if (context->hslot == index_reset_slot) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2630 context->sprite_index = index_reset_value; |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2631 context->slot_counter = mode_5 ? 0 : max_sprites; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2632 } else if (context->vcounter == vint_line && context->hslot == vint_slot) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2633 context->flags2 |= FLAG2_VINT_PENDING; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2634 context->pending_vint_start = context->cycles; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2635 } |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2636 |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2637 if (dst) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2638 if (mode_5) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2639 bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2640 } else if (context->regs[REG_MODE_1] & BIT_MODE_4) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2641 bg_color = context->colors[CRAM_SIZE * 3 + 0x10 + (context->regs[REG_BG_COLOR] & 0xF)]; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2642 } |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2643 *(dst++) = bg_color; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2644 *(dst++) = bg_color; |
1267
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2645 if (context->hslot == (bg_end_slot-1)) { |
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2646 *(dst++) = bg_color; |
3772bb926be5
Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents:
1191
diff
changeset
|
2647 } |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2648 } |
1183
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
2649 |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
2650 if (!is_refresh(context, context->hslot)) { |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
2651 external_slot(context); |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
2652 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) { |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
2653 run_dma_src(context, context->hslot); |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
2654 } |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
2655 } |
8d8c71ebbbce
CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents:
1180
diff
changeset
|
2656 |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2657 if (is_h40) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2658 if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2659 context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40]; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2660 } else { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2661 context->cycles += MCLKS_SLOT_H40; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2662 } |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2663 } else { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2664 context->cycles += MCLKS_SLOT_H32; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2665 } |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2666 if (context->hslot == jump_start) { |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2667 context->hslot = jump_dest; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2668 } else { |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2669 context->hslot++; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
2670 } |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2671 if (context->hslot == line_change) { |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2672 vdp_advance_line(context); |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2673 if (context->vcounter == active_line) { |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2674 context->state = PREPARING; |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2675 return; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2676 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2677 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2678 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2679 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2680 |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2681 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2682 { |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2683 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40; |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2684 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5; |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2685 while(context->cycles < target_cycles) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2686 { |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2687 if (context->state == ACTIVE && context->vcounter == context->inactive_start) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2688 context->state = INACTIVE; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2689 } |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2690 |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2691 if (is_active(context)) { |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2692 if (mode_5) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2693 if (is_h40) { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2694 vdp_h40(context, target_cycles); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2695 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2696 vdp_h32(context, target_cycles); |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2697 } |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
2698 } else { |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2699 vdp_h32_mode4(context, target_cycles); |
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
2700 } |
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
2701 } else { |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
2702 vdp_inactive(context, target_cycles, is_h40, mode_5); |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2703 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2704 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2705 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2706 |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2707 uint32_t vdp_run_to_vblank(vdp_context * context) |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2708 { |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2709 uint32_t old_frame = context->frame; |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2710 while (context->frame == old_frame) { |
1179
1271b240b9c2
Fix vdp_run_to_vblank
Michael Pavone <pavone@retrodev.com>
parents:
1178
diff
changeset
|
2711 vdp_run_context(context, context->cycles + MCLKS_LINE); |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2712 } |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2713 return context->cycles; |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2714 } |
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2715 |
75 | 2716 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
2717 { | |
2718 for(;;) { | |
2719 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
2720 if (!dmalen) { | |
2721 dmalen = 0x10000; | |
2722 } | |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2723 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20); |
1321
0849e9356bfe
Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1320
diff
changeset
|
2724 if ( |
0849e9356bfe
Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1320
diff
changeset
|
2725 (context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 |
0849e9356bfe
Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1320
diff
changeset
|
2726 || (((context->cd & 0xF) == VRAM_WRITE) && !(context->regs[REG_MODE_2] & BIT_128K_VRAM))) { |
75 | 2727 //DMA copies take twice as long to complete since they require a read and a write |
2728 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
1321
0849e9356bfe
Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1320
diff
changeset
|
2729 //unless 128KB mode is enabled |
75 | 2730 min_dma_complete *= 2; |
2731 } | |
2732 min_dma_complete += context->cycles; | |
2733 if (target_cycles < min_dma_complete) { | |
2734 vdp_run_context(context, target_cycles); | |
2735 return; | |
2736 } else { | |
2737 vdp_run_context(context, min_dma_complete); | |
2738 if (!(context->flags & FLAG_DMA_RUN)) { | |
2739 return; | |
2740 } | |
2741 } | |
2742 } | |
2743 } | |
2744 | |
1154
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2745 static uint16_t get_ext_vcounter(vdp_context *context) |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2746 { |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2747 uint16_t line= context->vcounter & 0xFF; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2748 if (context->double_res) { |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2749 line <<= 1; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2750 if (line & 0x100) { |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2751 line |= 1; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2752 } |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2753 } |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2754 return line << 8; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2755 } |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2756 |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2757 void vdp_latch_hv(vdp_context *context) |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2758 { |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2759 context->hv_latch = context->hslot | get_ext_vcounter(context); |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2760 } |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2761 |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2762 uint16_t vdp_hv_counter_read(vdp_context * context) |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2763 { |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2764 if ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_1] & BIT_HVC_LATCH)) { |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2765 return context->hv_latch; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2766 } |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2767 uint16_t hv; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2768 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2769 hv = context->hslot; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2770 } else { |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2771 hv = context->hv_latch & 0xFF; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2772 } |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2773 hv |= get_ext_vcounter(context); |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2774 |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2775 return hv; |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2776 } |
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2777 |
75 | 2778 int vdp_control_port_write(vdp_context * context, uint16_t value) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2779 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2780 //printf("control port write: %X at %d\n", value, context->cycles); |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
2781 if (context->flags & FLAG_DMA_RUN) { |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
2782 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
2783 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2784 if (context->flags & FLAG_PENDING) { |
1318
bfdd450e7dea
Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents:
1315
diff
changeset
|
2785 context->address = (context->address & 0x3FFF) | (value << 14 & 0x1C000); |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2786 //It seems like the DMA enable bit doesn't so much enable DMA so much |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2787 //as it enables changing CD5 from control port writes |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2788 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23; |
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2789 context->cd = (context->cd & preserve) | ((value >> 2) & ~preserve & 0xFF); |
75 | 2790 context->flags &= ~FLAG_PENDING; |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2791 //Should these be taken care of here or after the first write? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2792 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2793 context->flags2 &= ~FLAG2_READ_PENDING; |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
2794 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2795 if (context->cd & 0x20) { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
2796 // |
75 | 2797 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
2798 //DMA copy or 68K -> VDP, transfer starts immediately | |
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
2799 context->dma_cd = context->cd; |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
2800 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot); |
1191
8dc50e50ced6
Remove accidentally committed debug logging
Michael Pavone <pavone@retrodev.com>
parents:
1189
diff
changeset
|
2801 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
8dc50e50ced6
Remove accidentally committed debug logging
Michael Pavone <pavone@retrodev.com>
parents:
1189
diff
changeset
|
2802 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
1289
6ad59a62e656
Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents:
1285
diff
changeset
|
2803 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately |
6ad59a62e656
Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents:
1285
diff
changeset
|
2804 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test |
6ad59a62e656
Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents:
1285
diff
changeset
|
2805 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible |
6ad59a62e656
Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents:
1285
diff
changeset
|
2806 //sticking with 3 slots for now until I can do some more captures |
6ad59a62e656
Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents:
1285
diff
changeset
|
2807 vdp_run_context(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5)); |
1285
76e47254596b
Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation
Michael Pavone <pavone@retrodev.com>
parents:
1278
diff
changeset
|
2808 context->flags |= FLAG_DMA_RUN; |
75 | 2809 return 1; |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
2810 } else { |
1285
76e47254596b
Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation
Michael Pavone <pavone@retrodev.com>
parents:
1278
diff
changeset
|
2811 context->flags |= FLAG_DMA_RUN; |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
2812 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
75 | 2813 } |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
2814 } else { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
2815 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
75 | 2816 } |
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
2817 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2818 } else { |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2819 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5; |
1151
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
2820 context->address = (context->address &0xC000) | (value & 0x3FFF); |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2821 context->cd = (context->cd & 0x3C) | (value >> 14); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2822 if ((value & 0xC000) == 0x8000) { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2823 //Register write |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2824 uint8_t reg = (value >> 8) & 0x1F; |
1123
d5412f76accc
Fix inactive start line for Mode 4 in vdp_next_hint. Fix an off by one error in the range of registers allowed to be written in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1122
diff
changeset
|
2825 if (reg < (mode_5 ? VDP_REGS : 0xB)) { |
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
2826 //printf("register %d set to %X\n", reg, value & 0xFF); |
480
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
2827 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) { |
1154
c83ec07ddbac
Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents:
1153
diff
changeset
|
2828 vdp_latch_hv(context); |
480
0737953132ad
Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents:
479
diff
changeset
|
2829 } |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
2830 if (reg == REG_BG_COLOR) { |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
2831 value &= 0x3F; |
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
503
diff
changeset
|
2832 } |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
2833 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
2834 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame); |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
2835 }*/ |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2836 context->regs[reg] = value; |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
2837 if (reg == REG_MODE_4) { |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
2838 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
2839 if (!context->double_res) { |
1106
cacbd3f18f03
Fix field flag handling bug introduced with VDP/render interface cleanup
Michael Pavone <pavone@retrodev.com>
parents:
1103
diff
changeset
|
2840 context->flags2 &= ~FLAG2_EVEN_FIELD; |
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
2841 } |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2842 } |
1335
26e72126f9d1
Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents:
1334
diff
changeset
|
2843 if (reg == REG_MODE_1 || reg == REG_MODE_2 || reg == REG_MODE_4) { |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2844 update_video_params(context); |
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
2845 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2846 } |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2847 } else if (mode_5) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2848 context->flags |= FLAG_PENDING; |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2849 //Should these be taken care of here or after the second write? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2850 //context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2851 //context->flags2 &= ~FLAG2_READ_PENDING; |
1120
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2852 } else { |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2853 context->flags &= ~FLAG_READ_FETCHED; |
e9369d6f0101
Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1117
diff
changeset
|
2854 context->flags2 &= ~FLAG2_READ_PENDING; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2855 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2856 } |
75 | 2857 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2858 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2859 |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2860 void vdp_control_port_write_pbc(vdp_context *context, uint8_t value) |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2861 { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2862 if (context->flags2 & FLAG2_BYTE_PENDING) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2863 uint16_t full_val = value << 8 | context->pending_byte; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2864 context->flags2 &= ~FLAG2_BYTE_PENDING; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2865 //TODO: Deal with fact that Vbus->VDP DMA doesn't do anything in PBC mode |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2866 vdp_control_port_write(context, full_val); |
1151
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
2867 if (context->cd == VRAM_READ) { |
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
2868 context->cd = VRAM_READ8; |
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
2869 } |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2870 } else { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2871 context->pending_byte = value; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2872 context->flags2 |= FLAG2_BYTE_PENDING; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2873 } |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2874 } |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2875 |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
2876 int vdp_data_port_write(vdp_context * context, uint16_t value) |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2877 { |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2878 //printf("data port write: %X at %d\n", value, context->cycles); |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
2879 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
2880 return -1; |
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
2881 } |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2882 if (context->flags & FLAG_PENDING) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2883 context->flags &= ~FLAG_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2884 //Should these be cleared here? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2885 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2886 context->flags2 &= ~FLAG2_READ_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2887 } |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
2888 /*if (context->fifo_cur == context->fifo_end) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2889 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
2890 }*/ |
460
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
2891 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
2892 context->flags &= ~FLAG_DMA_RUN; |
788ba843a731
Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
2893 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2894 while (context->fifo_write == context->fifo_read) { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2895 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2896 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2897 fifo_entry * cur = context->fifo + context->fifo_write; |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2898 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2899 cur->address = context->address; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2900 cur->value = value; |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2901 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2902 cur->cd = context->cd; |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2903 } else { |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2904 cur->cd = (context->cd & 2) | 1; |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2905 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2906 cur->partial = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2907 if (context->fifo_read < 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2908 context->fifo_read = context->fifo_write; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2909 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2910 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
1151
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
2911 increment_address(context); |
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
2912 return 0; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2913 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2914 |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2915 void vdp_data_port_write_pbc(vdp_context * context, uint8_t value) |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2916 { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2917 if (context->flags & FLAG_PENDING) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2918 context->flags &= ~FLAG_PENDING; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2919 //Should these be cleared here? |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2920 context->flags &= ~FLAG_READ_FETCHED; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2921 context->flags2 &= ~FLAG2_READ_PENDING; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2922 } |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2923 context->flags2 &= ~FLAG2_BYTE_PENDING; |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2924 /*if (context->fifo_cur == context->fifo_end) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2925 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2926 }*/ |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2927 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2928 context->flags &= ~FLAG_DMA_RUN; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2929 } |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2930 while (context->fifo_write == context->fifo_read) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2931 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2932 } |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2933 fifo_entry * cur = context->fifo + context->fifo_write; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2934 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2935 cur->address = context->address; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2936 cur->value = value; |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2937 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2938 cur->cd = context->cd; |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2939 } else { |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2940 cur->cd = (context->cd & 2) | 1; |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
2941 } |
1333
69c25e1188e5
Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents:
1331
diff
changeset
|
2942 cur->partial = 3; |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2943 if (context->fifo_read < 0) { |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2944 context->fifo_read = context->fifo_write; |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2945 } |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2946 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1); |
1151
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
2947 increment_address(context); |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2948 } |
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2949 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2950 void vdp_test_port_write(vdp_context * context, uint16_t value) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2951 { |
1318
bfdd450e7dea
Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents:
1315
diff
changeset
|
2952 context->test_port = value; |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2953 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2954 |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2955 uint16_t vdp_control_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2956 { |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2957 context->flags &= ~FLAG_PENDING; |
1151
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
2958 context->flags2 &= ~FLAG2_BYTE_PENDING; |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
2959 //Bits 15-10 are not fixed like Charles MacDonald's doc suggests, but instead open bus values that reflect 68K prefetch |
1117
928a65750345
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents:
1106
diff
changeset
|
2960 uint16_t value = context->system->get_open_bus_value(context->system) & 0xFC00; |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2961 if (context->fifo_read < 0) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2962 value |= 0x200; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2963 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
2964 if (context->fifo_read == context->fifo_write) { |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2965 value |= 0x100; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
2966 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2967 if (context->flags2 & FLAG2_VINT_PENDING) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
2968 value |= 0x80; |
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
2969 } |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
2970 if (context->flags & FLAG_DOT_OFLOW) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
2971 value |= 0x40; |
1156
b519965f6394
Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents:
1155
diff
changeset
|
2972 context->flags &= ~FLAG_DOT_OFLOW; |
494
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
2973 } |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
2974 if (context->flags2 & FLAG2_SPRITE_COLLIDE) { |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
2975 value |= 0x20; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
2976 context->flags2 &= ~FLAG2_SPRITE_COLLIDE; |
8ac0eb05642c
Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents:
481
diff
changeset
|
2977 } |
1077
1a66d5165ea7
Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents:
1076
diff
changeset
|
2978 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && !(context->flags2 & FLAG2_EVEN_FIELD)) { |
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
2979 value |= 0x10; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2980 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2981 uint32_t slot = context->hslot; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
2982 if (!is_active(context)) { |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
2983 value |= 0x8; |
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
2984 } |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2985 if (context->regs[REG_MODE_4] & BIT_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2986 if (slot < HBLANK_END_H40 || slot > HBLANK_START_H40) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2987 value |= 0x4; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2988 } |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2989 } else { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2990 if (slot < HBLANK_END_H32 || slot > HBLANK_START_H32) { |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2991 value |= 0x4; |
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
2992 } |
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
2993 } |
983
14d2f3b0e45d
Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
2994 if (context->cd & 0x20) { |
141
576f55711d8d
Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
2995 value |= 0x2; |
75 | 2996 } |
714
e29bc2918f69
Fix VDP status register PAL bit based on observations of the Titan Overdrive demo
Michael Pavone <pavone@retrodev.com>
parents:
711
diff
changeset
|
2997 if (context->flags2 & FLAG2_REGION_PAL) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2998 value |= 0x1; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
2999 } |
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
3000 //printf("status read at cycle %d returned %X\n", context->cycles, value); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3001 return value; |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3002 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3003 |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3004 uint16_t vdp_data_port_read(vdp_context * context) |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3005 { |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3006 if (context->flags & FLAG_PENDING) { |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3007 context->flags &= ~FLAG_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3008 //Should these be cleared here? |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3009 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3010 context->flags2 &= ~FLAG2_READ_PENDING; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3011 } |
138 | 3012 if (context->cd & 1) { |
991
f9ee6f746cb4
Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents:
984
diff
changeset
|
3013 warning("Read from VDP data port while writes are configured, CPU is now frozen. VDP Address: %X, CD: %X\n", context->address, context->cd); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3014 } |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3015 while (!(context->flags & FLAG_READ_FETCHED)) { |
622
b76d2a628ab9
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents:
621
diff
changeset
|
3016 vdp_run_context(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3017 } |
980
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3018 context->flags &= ~FLAG_READ_FETCHED; |
928442068afe
Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents:
953
diff
changeset
|
3019 return context->prefetch; |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3020 } |
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
3021 |
1149
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
3022 uint8_t vdp_data_port_read_pbc(vdp_context * context) |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
3023 { |
1153
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
3024 context->flags &= ~(FLAG_PENDING | FLAG_READ_FETCHED); |
2e3ad914bad3
BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1152
diff
changeset
|
3025 context->flags2 &= ~FLAG2_BYTE_PENDING; |
1151
681e8a13b261
Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents:
1150
diff
changeset
|
3026 |
1152
ddbb61be6119
Fix to pass a couple more tests in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents:
1151
diff
changeset
|
3027 context->cd = VRAM_READ8; |
1149
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
3028 return context->prefetch; |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
3029 } |
6b0da6021544
Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents:
1138
diff
changeset
|
3030 |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
3031 uint16_t vdp_test_port_read(vdp_context * context) |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
3032 { |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
3033 //TODO: Find out what actually gets returned here |
1318
bfdd450e7dea
Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents:
1315
diff
changeset
|
3034 return context->test_port; |
470
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
3035 } |
541c1ae8abf3
Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
3036 |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
3037 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
3038 { |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
3039 context->cycles -= deduction; |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3040 if (context->pending_vint_start >= deduction) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3041 context->pending_vint_start -= deduction; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3042 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3043 context->pending_vint_start = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3044 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3045 if (context->pending_hint_start >= deduction) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3046 context->pending_hint_start -= deduction; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3047 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3048 context->pending_hint_start = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3049 } |
471
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3050 if (context->fifo_read >= 0) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3051 int32_t idx = context->fifo_read; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3052 do { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3053 if (context->fifo[idx].cycle >= deduction) { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3054 context->fifo[idx].cycle -= deduction; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3055 } else { |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3056 context->fifo[idx].cycle = 0; |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3057 } |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3058 idx = (idx+1) & (FIFO_SIZE-1); |
f065769836e8
Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents:
470
diff
changeset
|
3059 } while(idx != context->fifo_write); |
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
3060 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
3061 } |
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
3062 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
3063 static uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context) |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3064 { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3065 if (context->hslot < 183) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3066 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3067 } else if (context->hslot < HSYNC_END_H40) { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3068 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3069 uint32_t hsync = 0; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3070 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++) |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3071 { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3072 hsync += h40_hsync_cycles[i]; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3073 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3074 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3075 return before_hsync + hsync + after_hsync; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3076 } else { |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3077 return (256-context->hslot) * MCLKS_SLOT_H40; |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3078 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3079 } |
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3080 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
3081 static uint32_t vdp_cycles_next_line(vdp_context * context) |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3082 { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3083 if (context->regs[REG_MODE_4] & BIT_H40) { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3084 //TODO: Handle "illegal" Mode 4/H40 combo |
647
5d58dcd94733
Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents:
629
diff
changeset
|
3085 if (context->hslot < LINE_CHANGE_H40) { |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
680
diff
changeset
|
3086 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3087 } else { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3088 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3089 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3090 } else { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3091 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3092 if (context->hslot < LINE_CHANGE_H32) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3093 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3094 } else if (context->hslot < 148) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3095 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3096 } else { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3097 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3098 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3099 } else { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3100 if (context->hslot < 148) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3101 return (148 - context->hslot + LINE_CHANGE_MODE4 - 233) * MCLKS_SLOT_H32; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3102 } else if (context->hslot < LINE_CHANGE_MODE4) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3103 return (LINE_CHANGE_MODE4 - context->hslot) * MCLKS_SLOT_H32; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3104 } else { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3105 return MCLKS_LINE - (context->hslot - LINE_CHANGE_MODE4) * MCLKS_SLOT_H32; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3106 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3107 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3108 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3109 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3110 |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3111 static void get_jump_params(vdp_context *context, uint32_t *jump_start, uint32_t *jump_dst) |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3112 { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3113 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3114 if (context->flags2 & FLAG2_REGION_PAL) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3115 if (context->regs[REG_MODE_2] & BIT_PAL) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3116 *jump_start = 0x10B; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3117 *jump_dst = 0x1D2; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3118 } else { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3119 *jump_start = 0x103; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3120 *jump_dst = 0x1CA; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3121 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3122 } else { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3123 if (context->regs[REG_MODE_2] & BIT_PAL) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3124 *jump_start = 0x100; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3125 *jump_dst = 0x1FA; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3126 } else { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3127 *jump_start = 0xEB; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3128 *jump_dst = 0x1E5; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3129 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3130 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3131 } else { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3132 *jump_start = 0xDB; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3133 *jump_dst = 0x1D5; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3134 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3135 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3136 |
1102
c15896605bf2
Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents:
1077
diff
changeset
|
3137 static uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target) |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3138 { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3139 uint32_t jump_start, jump_dst; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3140 get_jump_params(context, &jump_start, &jump_dst); |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3141 uint32_t lines; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3142 if (context->vcounter < target) { |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3143 if (target < jump_start || context->vcounter > jump_start) { |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3144 lines = target - context->vcounter; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3145 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3146 lines = jump_start - context->vcounter + target - jump_dst; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3147 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3148 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3149 if (context->vcounter < jump_start) { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
3150 lines = jump_start - context->vcounter + 512 - jump_dst; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3151 } else { |
718
eaba6789f316
Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents:
717
diff
changeset
|
3152 lines = 512 - context->vcounter; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3153 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3154 if (target < jump_start) { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3155 lines += target; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3156 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3157 lines += jump_start + target - jump_dst; |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3158 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3159 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3160 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context); |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3161 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3162 |
680
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
3163 uint32_t vdp_cycles_to_frame_end(vdp_context * context) |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
3164 { |
1167
e758ddbf0624
Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents:
1163
diff
changeset
|
3165 return context->cycles + vdp_cycles_to_line(context, context->inactive_start); |
680
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
3166 } |
4996369f1463
Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents:
678
diff
changeset
|
3167 |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3168 uint32_t vdp_next_hint(vdp_context * context) |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3169 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
3170 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3171 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3172 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3173 if (context->flags2 & FLAG2_HINT_PENDING) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3174 return context->pending_hint_start; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3175 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3176 uint32_t hint_line; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3177 if (context->state != ACTIVE) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3178 hint_line = context->regs[REG_HINT]; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3179 if (hint_line > context->inactive_start) { |
724
2174f92c5f9b
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents:
722
diff
changeset
|
3180 return 0xFFFFFFFF; |
2174f92c5f9b
Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents:
722
diff
changeset
|
3181 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3182 } else { |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3183 hint_line = context->vcounter + context->hint_counter + 1; |
1325
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3184 if (context->vcounter < context->inactive_start) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3185 if (hint_line > context->inactive_start) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3186 hint_line = context->regs[REG_HINT]; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3187 if (hint_line > context->inactive_start) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3188 return 0xFFFFFFFF; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3189 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3190 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3191 } else { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3192 uint32_t jump_start, jump_dst; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3193 get_jump_params(context, &jump_start, &jump_dst); |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3194 if (hint_line >= jump_start && context->vcounter < jump_dst) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3195 hint_line = (hint_line + jump_dst - jump_start) & 0x1FF; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3196 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3197 if (hint_line < context->vcounter && hint_line > context->inactive_start) { |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3198 return 0xFFFFFFFF; |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3199 } |
58bfbed6cdb5
Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents:
1322
diff
changeset
|
3200 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3201 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3202 return context->cycles + vdp_cycles_to_line(context, hint_line); |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3203 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3204 |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3205 static uint32_t vdp_next_vint_real(vdp_context * context) |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3206 { |
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
3207 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3208 return 0xFFFFFFFF; |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3209 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3210 if (context->flags2 & FLAG2_VINT_PENDING) { |
717
22dbdf50d33c
Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents:
714
diff
changeset
|
3211 return context->pending_vint_start; |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3212 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3213 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3214 |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3215 return vdp_next_vint_z80(context); |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3216 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3217 |
1171
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3218 uint32_t vdp_next_vint(vdp_context *context) |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3219 { |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3220 uint32_t ret = vdp_next_vint_real(context); |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3221 #ifdef TIMING_DEBUG |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3222 static uint32_t last = 0xFFFFFFFF; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3223 if (last != ret) { |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3224 printf("vdp_next_vint is %d at frame %d, line %d, hslot %d\n", ret, context->frame, context->vcounter, context->hslot); |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3225 } |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3226 last = ret; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3227 #endif |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3228 return ret; |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3229 } |
43fa92976ff2
Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents:
1170
diff
changeset
|
3230 |
333 | 3231 uint32_t vdp_next_vint_z80(vdp_context * context) |
3232 { | |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
3233 uint16_t vint_line = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->inactive_start : context->inactive_start + 1; |
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
3234 if (context->vcounter == vint_line) { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3235 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3236 if (context->regs[REG_MODE_4] & BIT_H40) { |
1175
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3237 if (context->hslot >= LINE_CHANGE_H40 || context->hslot <= VINT_SLOT_H40) { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3238 uint32_t cycles = context->cycles; |
1175
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3239 if (context->hslot >= LINE_CHANGE_H40) { |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3240 if (context->hslot < 183) { |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3241 cycles += (183 - context->hslot) * MCLKS_SLOT_H40; |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3242 } |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3243 |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3244 if (context->hslot < HSYNC_SLOT_H40) { |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3245 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40; |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3246 } |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3247 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ ) |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3248 { |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3249 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40]; |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3250 } |
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3251 cycles += (256 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40; |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3252 } |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3253 |
1175
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3254 cycles += (VINT_SLOT_H40 - (context->hslot >= LINE_CHANGE_H40 ? 0 : context->hslot)) * MCLKS_SLOT_H40; |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3255 return cycles; |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
3256 } |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3257 } else { |
1174
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
3258 if (context->hslot >= LINE_CHANGE_H32 || context->hslot <= VINT_SLOT_H32) { |
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
3259 if (context->hslot <= VINT_SLOT_H32) { |
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
3260 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32; |
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
3261 } else if (context->hslot < 233) { |
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
3262 return context->cycles + (VINT_SLOT_H32 + 256 - 233 + 148 - context->hslot) * MCLKS_SLOT_H32; |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3263 } else { |
1174
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
3264 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32; |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3265 } |
995
2bc27415565b
Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents:
991
diff
changeset
|
3266 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3267 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3268 } else { |
1177
67e0462c30ce
Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency
Michael Pavone <pavone@retrodev.com>
parents:
1175
diff
changeset
|
3269 if (context->hslot >= LINE_CHANGE_MODE4) { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3270 return context->cycles + (VINT_SLOT_MODE4 + 256 - context->hslot) * MCLKS_SLOT_H32; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3271 } |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3272 if (context->hslot <= VINT_SLOT_MODE4) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3273 return context->cycles + (VINT_SLOT_MODE4 - context->hslot) * MCLKS_SLOT_H32; |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3274 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3275 } |
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3276 } |
1169
82d8b9324b10
Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents:
1168
diff
changeset
|
3277 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line); |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3278 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3279 if (context->regs[REG_MODE_4] & BIT_H40) { |
1175
0e0386fa795c
Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1174
diff
changeset
|
3280 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40; |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3281 } else { |
1174
500d8deea802
Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents:
1173
diff
changeset
|
3282 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32; |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3283 } |
333 | 3284 } else { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3285 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32; |
333 | 3286 } |
623
66cc60215e5c
Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents:
622
diff
changeset
|
3287 return context->cycles + cycles_to_vint; |
333 | 3288 } |
3289 | |
953
08346262990b
Remove the int number argument to vdp_int_ack since it is no longer used
Michael Pavone <pavone@retrodev.com>
parents:
952
diff
changeset
|
3290 void vdp_int_ack(vdp_context * context) |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3291 { |
1160
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3292 //CPU interrupt acknowledge is only used in Mode 5 |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3293 if (context->regs[REG_MODE_2] & BIT_MODE_5) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3294 //Apparently the VDP interrupt controller is not very smart |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3295 //Instead of paying attention to what interrupt is being acknowledged it just |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3296 //clears the pending flag for whatever interrupt it is currently asserted |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3297 //which may be different from the interrupt it was asserting when the 68k |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3298 //started the interrupt process. The window for this is narrow and depends |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3299 //on the latency between the int enable register write and the interrupt being |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3300 //asserted, but Fatal Rewind depends on this due to some buggy code |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3301 if ((context->flags2 & FLAG2_VINT_PENDING) && (context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3302 context->flags2 &= ~FLAG2_VINT_PENDING; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3303 } else if((context->flags2 & FLAG2_HINT_PENDING) && (context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3304 context->flags2 &= ~FLAG2_HINT_PENDING; |
5f119fe935e7
Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
1157
diff
changeset
|
3305 } |
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3306 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3307 } |
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
3308 |