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annotate vdp.c @ 1865:4c322abd9fa5

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Split generic part of audio code into a separate file so it can be used in other targets besides SDL
author Michael Pavone <pavone@retrodev.com>
date Fri, 17 May 2019 08:43:30 -0700
parents 304d47a5c67f
children 84f16a804ce5
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140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
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1 /*
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2 Copyright 2013 Michael Pavone
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include "vdp.h"
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7 #include "blastem.h"
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8 #include <stdlib.h>
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9 #include <string.h>
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10 #include "render.h"
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11 #include "util.h"
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12
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b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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13 #define NTSC_INACTIVE_START 224
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14 #define PAL_INACTIVE_START 240
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15 #define MODE4_INACTIVE_START 192
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16 #define BUF_BIT_PRIORITY 0x40
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17 #define MAP_BIT_PRIORITY 0x8000
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18 #define MAP_BIT_H_FLIP 0x800
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19 #define MAP_BIT_V_FLIP 0x1000
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20
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21 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
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22 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
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3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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23
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24 #define MCLKS_SLOT_H40 16
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25 #define MCLKS_SLOT_H32 20
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26 #define VINT_SLOT_H40 0 //21 slots before HSYNC, 16 during, 10 after
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27 #define VINT_SLOT_H32 0 //old value was 23, but recent tests suggest the actual value is close to the H40 one
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28 #define VINT_SLOT_MODE4 4
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29 #define HSYNC_SLOT_H40 230
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30 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17)
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31 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results
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32 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results
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33 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result
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34 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results
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35 #define LINE_CHANGE_H40 165
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36 #define LINE_CHANGE_H32 133
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37 #define LINE_CHANGE_MODE4 249
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38 #define VBLANK_START_H40 (LINE_CHANGE_H40+2)
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39 #define VBLANK_START_H32 (LINE_CHANGE_H32+2)
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40 #define FIFO_LATENCY 3
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41
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42 #define BORDER_TOP_V24 27
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43 #define BORDER_TOP_V28 11
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44 #define BORDER_TOP_V24_PAL 54
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45 #define BORDER_TOP_V28_PAL 38
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46 #define BORDER_TOP_V30_PAL 30
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47
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48 #define BORDER_BOT_V24 24
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49 #define BORDER_BOT_V28 8
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50 #define BORDER_BOT_V24_PAL 48
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51 #define BORDER_BOT_V28_PAL 32
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52 #define BORDER_BOT_V30_PAL 24
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53
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54 enum {
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55 INACTIVE = 0,
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56 PREPARING, //used for line 0x1FF
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57 ACTIVE
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58 };
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59
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60 static int32_t color_map[1 << 12];
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61 static uint16_t mode4_address_map[0x4000];
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62 static uint32_t planar_to_chunky[256];
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63 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
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64
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65 static uint8_t debug_base[][3] = {
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66 {127, 127, 127}, //BG
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67 {0, 0, 127}, //A
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68 {127, 0, 0}, //Window
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69 {0, 127, 0}, //B
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70 {127, 0, 127} //Sprites
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71 };
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72
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73 static void update_video_params(vdp_context *context)
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74 {
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75 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
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76 if (context->regs[REG_MODE_2] & BIT_PAL) {
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77 if (context->flags2 & FLAG2_REGION_PAL) {
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78 context->inactive_start = PAL_INACTIVE_START;
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79 context->border_top = BORDER_TOP_V30_PAL;
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80 context->border_bot = BORDER_BOT_V30_PAL;
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81 } else {
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82 //the behavior here is rather weird and needs more investigation
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83 context->inactive_start = 0xF0;
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84 context->border_top = 1;
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85 context->border_bot = 3;
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86 }
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87 } else {
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88 context->inactive_start = NTSC_INACTIVE_START;
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89 if (context->flags2 & FLAG2_REGION_PAL) {
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90 context->border_top = BORDER_TOP_V28_PAL;
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91 context->border_bot = BORDER_BOT_V28_PAL;
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92 } else {
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93 context->border_top = BORDER_TOP_V28;
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94 context->border_bot = BORDER_TOP_V28;
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95 }
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96 }
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97 if (context->regs[REG_MODE_4] & BIT_H40) {
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98 context->max_sprites_frame = MAX_SPRITES_FRAME;
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99 context->max_sprites_line = MAX_SPRITES_LINE;
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100 } else {
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101 context->max_sprites_frame = MAX_SPRITES_FRAME_H32;
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102 context->max_sprites_line = MAX_SPRITES_LINE_H32;
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103 }
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104 if (context->state == INACTIVE) {
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105 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active
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106 if (context->vcounter < context->inactive_start) {
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107 context->state = ACTIVE;
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108 } else if (context->vcounter == 0x1FF) {
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109 context->state = PREPARING;
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110 }
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111 }
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112 } else {
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Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
113 context->inactive_start = MODE4_INACTIVE_START;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
114 if (context->flags2 & FLAG2_REGION_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
115 context->border_top = BORDER_TOP_V24_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
116 context->border_bot = BORDER_BOT_V24_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
117 } else {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
118 context->border_top = BORDER_TOP_V24;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
119 context->border_bot = BORDER_BOT_V24;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
120 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
121 if (!(context->regs[REG_MODE_1] & BIT_MODE_4)){
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
122 context->state = INACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
123 } else if (context->state == INACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
124 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
125 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
126 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
127 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
128 else if (context->vcounter == 0x1FF) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
129 context->state = PREPARING;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
130 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
131 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
132 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
133 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
134
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
135 static uint8_t color_map_init_done;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
136
1640
3602f3b20072 Small cleanup of vdp_context struct layout and removal of separately allocated buffers
Michael Pavone <pavone@retrodev.com>
parents: 1639
diff changeset
137 vdp_context *init_vdp_context(uint8_t region_pal)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
138 {
1640
3602f3b20072 Small cleanup of vdp_context struct layout and removal of separately allocated buffers
Michael Pavone <pavone@retrodev.com>
parents: 1639
diff changeset
139 vdp_context *context = calloc(1, sizeof(vdp_context) + VRAM_SIZE);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
140 if (headless) {
1168
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
141 context->output = malloc(LINEBUF_SIZE * sizeof(uint32_t));
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
142 context->output_pitch = 0;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
143 } else {
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
144 context->cur_buffer = FRAMEBUFFER_ODD;
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
145 context->fb = render_get_framebuffer(FRAMEBUFFER_ODD, &context->output_pitch);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
146 }
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
147 context->sprite_draws = MAX_DRAWS;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
148 context->fifo_write = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
149 context->fifo_read = -1;
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
150 context->regs[REG_HINT] = context->hint_counter = 0xFF;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
151
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
152 if (!color_map_init_done) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
153 uint8_t b,g,r;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
154 for (uint16_t color = 0; color < (1 << 12); color++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
155 if (color & FBUF_SHADOW) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
156 b = levels[(color >> 9) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
157 g = levels[(color >> 5) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
158 r = levels[(color >> 1) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
159 } else if(color & FBUF_HILIGHT) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
160 b = levels[((color >> 9) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
161 g = levels[((color >> 5) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
162 r = levels[((color >> 1) & 0x7) + 7];
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
163 } else if(color & FBUF_MODE4) {
1127
cb4771f4543a Fix Mode 4 color mapping
Michael Pavone <pavone@retrodev.com>
parents: 1125
diff changeset
164 b = levels[(color >> 4 & 0xC) | (color >> 6 & 0x2)];
1125
fba485949723 Brighten up Mode 4 colors
Michael Pavone <pavone@retrodev.com>
parents: 1124
diff changeset
165 g = levels[(color >> 2 & 0x8) | (color >> 1 & 0x4) | (color >> 4 & 0x2)];
fba485949723 Brighten up Mode 4 colors
Michael Pavone <pavone@retrodev.com>
parents: 1124
diff changeset
166 r = levels[(color << 1 & 0xC) | (color >> 1 & 0x2)];
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
167 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
168 b = levels[(color >> 8) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
169 g = levels[(color >> 4) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
170 r = levels[color & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
171 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
172 color_map[color] = render_map_color(r, g, b);
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
173 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
174 for (uint16_t mode4_addr = 0; mode4_addr < 0x4000; mode4_addr++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
175 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
176 uint16_t mode5_addr = mode4_addr & 0x3DFD;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
177 mode5_addr |= mode4_addr << 8 & 0x200;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
178 mode5_addr |= mode4_addr >> 8 & 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
179 mode4_address_map[mode4_addr] = mode5_addr;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
180 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
181 for (uint32_t planar = 0; planar < 256; planar++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
182 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
183 uint32_t chunky = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
184 for (int bit = 7; bit >= 0; bit--)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
185 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
186 chunky = chunky << 4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
187 chunky |= planar >> bit & 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
188 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
189 planar_to_chunky[planar] = chunky;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
190 }
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
191 color_map_init_done = 1;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
192 }
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
193 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++)
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
194 {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
195 uint8_t src = color & DBG_SRC_MASK;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
196 if (src > DBG_SRC_S) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
197 context->debugcolors[color] = 0;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
198 } else {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
199 uint8_t r,g,b;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
200 b = debug_base[src][0];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
201 g = debug_base[src][1];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
202 r = debug_base[src][2];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
203 if (color & DBG_PRIORITY)
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
204 {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
205 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
206 b += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
207 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
208 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
209 g += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
210 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
211 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
212 r += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
213 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
214 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
215 if (color & DBG_SHADOW) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
216 b /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
217 g /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
218 r /=2 ;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
219 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
220 if (color & DBG_HILIGHT) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
221 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
222 b += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
223 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
224 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
225 g += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
226 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
227 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
228 r += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
229 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
230 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
231 context->debugcolors[color] = render_map_color(r, g, b);
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
232 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
233 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
234 if (region_pal) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
235 context->flags2 |= FLAG2_REGION_PAL;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
236 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
237 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
238 if (!headless) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
239 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * context->border_top);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
240 }
1640
3602f3b20072 Small cleanup of vdp_context struct layout and removal of separately allocated buffers
Michael Pavone <pavone@retrodev.com>
parents: 1639
diff changeset
241 return context;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
243
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
244 void vdp_free(vdp_context *context)
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
245 {
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
246 free(context);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
247 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
248
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
249 static int is_refresh(vdp_context * context, uint32_t slot)
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
250 {
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
251 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
252 return slot == 250 || slot == 26 || slot == 59 || slot == 90 || slot == 122 || slot == 154;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
253 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
254 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
255 //These numbers are guesses based on H40 numbers
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
256 return slot == 243 || slot == 19 || slot == 51 || slot == 83 || slot == 115;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
257 //The numbers below are the refresh slots during active display
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
258 //return (slot == 29 || slot == 61 || slot == 93 || slot == 125);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
259 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
260 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
261
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
262 static void increment_address(vdp_context *context)
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
263 {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
264 context->address += context->regs[REG_AUTOINC];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
265 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
266 context->address++;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
267 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
268 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
269
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
270 static void render_sprite_cells(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
271 {
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
272 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
273 context->serial_address = d->address;
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
274 if (context->cur_slot >= context->sprite_draws) {
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
275
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
276 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
277 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
278 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
279 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
280 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
281 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
282 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
283 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
284 }
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
285 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
286 context->cur_slot--;
143
e5487ef04619 Fix infinite loop bug in sprite rendering
Mike Pavone <pavone@retrodev.com>
parents: 142
diff changeset
287 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
1029
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
288 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
289 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
290 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
291 } else if (context->vdpmem[address] >> 4) {
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
292 context->flags2 |= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
293 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
294 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
295 x += dir;
1029
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
296 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
297 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
298 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
299 } else if (context->vdpmem[address] & 0xF) {
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
300 context->flags2 |= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
301 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
303 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 }
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
305 } else {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
306 context->cur_slot--;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
307 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
308 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
310 static void fetch_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
311 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
312 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
313 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
314 uint32_t address = mode4_address_map[d->address & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
315 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
316 context->fetch_tmp[1] = context->vdpmem[address + 1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
317 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
318 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
319
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
320 static void render_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
321 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
322 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
323 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
324 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
325 pixels |= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
326 uint32_t address = mode4_address_map[(d->address + 2) & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
327 pixels |= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
328 pixels |= planar_to_chunky[context->vdpmem[address + 1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
329 int x = d->x_pos & 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
330 for (int i = 28; i >= 0; i -= 4, x++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
331 {
1155
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
332 if (context->linebuf[x] && (pixels >> i & 0xF)) {
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
333 if (
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
334 ((context->regs[REG_MODE_1] & BIT_SPRITE_8PX) && x > 8)
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
335 || ((!(context->regs[REG_MODE_1] & BIT_SPRITE_8PX)) && x < 256)
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
336 ) {
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
337 context->flags2 |= FLAG2_SPRITE_COLLIDE;
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
338 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
339 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
340 context->linebuf[x] = pixels >> i & 0xF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
341 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
342 }
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
343 context->sprite_index--;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
344 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
345 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
346
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
347 static uint32_t mode5_sat_address(vdp_context *context)
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
348 {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
349 uint32_t addr = context->regs[REG_SAT] << 9;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
350 if (!(context->regs[REG_MODE_2] & BIT_128K_VRAM)) {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
351 addr &= 0xFFFF;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
352 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
353 if (context->regs[REG_MODE_4] & BIT_H40) {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
354 addr &= 0x1FC00;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
355 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
356 return addr;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
357 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
358
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
359 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
360 {
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
361 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
362 uint16_t sat_address = mode5_sat_address(context);
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
363 uint16_t current_index = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
364 uint8_t count = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
365 do {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
366 uint16_t address = current_index * 8 + sat_address;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
367 uint16_t cache_address = current_index * 4;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
368 uint8_t height = ((context->sat_cache[cache_address+2] & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
369 uint8_t width = (((context->sat_cache[cache_address+2] >> 2) & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
370 int16_t y = ((context->sat_cache[cache_address] & 0x3) << 8 | context->sat_cache[cache_address+1]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
371 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
372 uint16_t link = context->sat_cache[cache_address+3] & 0x7F;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
373 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
374 uint8_t pri = context->vdpmem[address + 4] >> 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
375 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
376 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
377 current_index = link;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
378 count++;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
379 } while (current_index != 0 && count < 80);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
380 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
381 uint16_t sat_address = (context->regs[REG_SAT] & 0x7E) << 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
382 for (int i = 0; i < 64; i++)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
383 {
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
384 uint8_t y = context->vdpmem[mode4_address_map[sat_address + (i ^ 1)]];
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
385 if (y == 0xD0) {
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
386 break;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
387 }
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
388 uint8_t x = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2 + 1]];
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
389 uint16_t tile_address = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2]] * 32
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
390 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
391 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
392 tile_address &= ~32;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
393 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
394 printf("Sprite %d: X=%d, Y=%d, Pat=%X\n", i, x, y, tile_address);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
395 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
396 }
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
397 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
398
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
399 #define VRAM_READ 0 //0000
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
400 #define VRAM_WRITE 1 //0001
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
401 //2 would trigger register write 0010
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
402 #define CRAM_WRITE 3 //0011
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
403 #define VSRAM_READ 4 //0100
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
404 #define VSRAM_WRITE 5//0101
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
405 //6 would trigger regsiter write 0110
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
406 //7 is a mystery //0111
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
407 #define CRAM_READ 8 //1000
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
408 //9 is also a mystery //1001
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
409 //A would trigger register write 1010
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
410 //B is a mystery 1011
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
411 #define VRAM_READ8 0xC //1100
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
412 //D is a mystery 1101
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
413 //E would trigger register write 1110
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
414 //F is a mystery 1111
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
415
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
416 //Possible theory on how bits work
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
417 //CD0 = Read/Write flag
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
418 //CD2,(CD1|CD3) = RAM type
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
419 // 00 = VRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
420 // 01 = CRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
421 // 10 = VSRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
422 // 11 = VRAM8
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
423 //Would result in
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
424 // 7 = VRAM8 write
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
425 // 9 = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
426 // B = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
427 // D = VRAM8 write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
428 // F = VRAM8 write alais
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
429
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
430 #define DMA_START 0x20
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
431
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
432 static const char * cd_name(uint8_t cd)
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
433 {
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
434 switch (cd & 0xF)
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
435 {
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
436 case VRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
437 return "VRAM read";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
438 case VRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
439 return "VRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
440 case CRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
441 return "CRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
442 case VSRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
443 return "VSRAM read";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
444 case VSRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
445 return "VSRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
446 case VRAM_READ8:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
447 return "VRAM read (undocumented 8-bit mode)";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
448 default:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
449 return "invalid";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
450 }
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
451 }
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
452
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
453 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
454 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
455 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
456 printf("**Mode Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
457 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1331
9bba5ff5beb8 Add 128K VRAM bit to VDP register print in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1325
diff changeset
458 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d, %dK VRAM\n"
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
459 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
460 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n",
757
483f7e7926a6 More clang warning cleanup
Michael Pavone <pavone@retrodev.com>
parents: 748
diff changeset
461 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", (context->regs[REG_MODE_1] & BIT_PAL_SEL) != 0,
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
462 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
463 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
1331
9bba5ff5beb8 Add 128K VRAM bit to VDP register print in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1325
diff changeset
464 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, context->regs[REG_MODE_1] & BIT_128K_VRAM ? 128 : 64,
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
465 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
466 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
467 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
468 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
469 printf("\n**Table Group**\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
470 "02: %.2X | Scroll A Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
471 "03: %.2X | Window Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
472 "04: %.2X | Scroll B Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
473 "05: %.2X | Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
474 "0D: %.2X | HScroll Data Table: $%.4X\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
475 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
476 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
477 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
478 context->regs[REG_SAT], mode5_sat_address(context),
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
479 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
480 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
481 printf("\n**Table Group**\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
482 "02: %.2X | Background Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
483 "05: %.2X | Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
484 "06: %.2X | Sprite Tile Base: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
485 "08: %.2X | Background X Scroll: %d\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
486 "09: %.2X | Background Y Scroll: %d\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
487 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0xE) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
488 context->regs[REG_SAT], (context->regs[REG_SAT] & 0x7E) << 7,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
489 context->regs[REG_STILE_BASE], (context->regs[REG_STILE_BASE] & 2) << 11,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
490 context->regs[REG_X_SCROLL], context->regs[REG_X_SCROLL],
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
491 context->regs[REG_Y_SCROLL], context->regs[REG_Y_SCROLL]);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
492
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
493 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
494 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
495 printf("\n**Misc Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
496 "07: %.2X | Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
497 "0A: %.2X | H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
498 "0F: %.2X | Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
499 "10: %.2X | Scroll A/B Size: %sx%s\n",
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
500 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR],
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
501 context->regs[REG_HINT], context->regs[REG_HINT],
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
502 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
503 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
504 char * src_types[] = {"68K", "68K", "Copy", "Fill"};
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
505 printf("\n**DMA Group**\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
506 "13: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
507 "14: %.2X | DMA Length: $%.4X words\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
508 "15: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
509 "16: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
510 "17: %.2X | DMA Source Address: $%.6X, Type: %s\n",
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
511 context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
512 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
513 context->regs[REG_DMASRC_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
514 context->regs[REG_DMASRC_M],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
515 context->regs[REG_DMASRC_H],
629
9089951a1994 Small fix to display of DMA source address in vr debug command
Michael Pavone <pavone@retrodev.com>
parents: 624
diff changeset
516 context->regs[REG_DMASRC_H] << 17 | context->regs[REG_DMASRC_M] << 9 | context->regs[REG_DMASRC_L] << 1,
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
517 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]);
1628
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
518 uint8_t old_flags = context->flags;
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
519 uint8_t old_flags2 = context->flags2;
438
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
520 printf("\n**Internal Group**\n"
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
521 "Address: %X\n"
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
522 "CD: %X - %s\n"
647
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
523 "Pending: %s\n"
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
524 "VCounter: %d\n"
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
525 "HCounter: %d\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
526 "VINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
527 "HINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
528 "Status: %X\n",
1150
322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1149
diff changeset
529 context->address, context->cd, cd_name(context->cd),
322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1149
diff changeset
530 (context->flags & FLAG_PENDING) ? "word" : (context->flags2 & FLAG2_BYTE_PENDING) ? "byte" : "none",
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
531 context->vcounter, context->hslot*2, (context->flags2 & FLAG2_VINT_PENDING) ? "true" : "false",
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
532 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context));
1628
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
533 //restore flags as calling vdp_control_port_read can change them
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
534 context->flags = old_flags;
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
535 context->flags2 = old_flags2;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
536 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
537
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
538 static uint8_t is_active(vdp_context *context)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
539 {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
540 return context->state != INACTIVE && (context->regs[REG_MODE_2] & BIT_DISP_EN) != 0;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
541 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
542
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
543 static void scan_sprite_table(uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
544 {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
545 if (context->sprite_index && ((uint8_t)context->slot_counter) < context->max_sprites_line) {
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 line += 1;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
547 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
548 uint8_t height_mult;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
549 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
550 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
551 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
552 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
553 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
554 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
555 ymin = 256;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
556 height_mult = 16;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
557 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
558 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
559 ymin = 128;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
560 height_mult = 8;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
561 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
562 context->sprite_index &= 0x7F;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
563 //TODO: Implement squirelly behavior documented by Kabuto
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
564 if (context->sprite_index >= context->max_sprites_frame) {
38
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
565 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
566 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
567 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
568 uint16_t address = context->sprite_index * 4;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
569 line += ymin;
1346
f7ca42e020fd Fix sprite rendering in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1344
diff changeset
570 line &= ymask;
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
571 uint16_t y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
572 uint8_t height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
573 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
574 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
575 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
576 context->sprite_info_list[context->slot_counter].size = context->sat_cache[address+2];
1358
3716b90d3470 Fix regression in Mode 4 sprite rendering
Michael Pavone <pavone@retrodev.com>
parents: 1357
diff changeset
577 context->sprite_info_list[context->slot_counter++].index = context->sprite_index;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
578 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
579 context->sprite_index = context->sat_cache[address+3] & 0x7F;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
580 if (context->sprite_index && ((uint8_t)context->slot_counter) < context->max_sprites_line)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
581 {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
582 //TODO: Implement squirelly behavior documented by Kabuto
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
583 if (context->sprite_index >= context->max_sprites_frame) {
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
584 context->sprite_index = 0;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
585 return;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
586 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
587 address = context->sprite_index * 4;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
588 y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
589 height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
590 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
591 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
592 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
593 context->sprite_info_list[context->slot_counter].size = context->sat_cache[address+2];
1358
3716b90d3470 Fix regression in Mode 4 sprite rendering
Michael Pavone <pavone@retrodev.com>
parents: 1357
diff changeset
594 context->sprite_info_list[context->slot_counter++].index = context->sprite_index;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
595 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
596 context->sprite_index = context->sat_cache[address+3] & 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
597 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
598 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
599 //TODO: Seems like the overflow flag should be set here if we run out of sprite info slots without hitting the end of the list
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
600 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
601
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
602 static void scan_sprite_table_mode4(vdp_context * context)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
603 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
604 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
605 uint32_t line = context->vcounter;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
606 line &= 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
607
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
608 uint32_t sat_address = mode4_address_map[(context->regs[REG_SAT] << 7 & 0x3F00) + context->sprite_index];
1138
25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping
Michael Pavone <pavone@retrodev.com>
parents: 1137
diff changeset
609 uint32_t y = context->vdpmem[sat_address+1];
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
610 uint32_t size = (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) ? 16 : 8;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
611
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
612 if (y == 0xd0) {
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
613 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
614 return;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
615 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
616 if (y <= line && line < (y + size)) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
617 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
618 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
619 context->flags |= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
620 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
621 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
622 context->sprite_info_list[--(context->slot_counter)].size = size;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
623 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
1358
3716b90d3470 Fix regression in Mode 4 sprite rendering
Michael Pavone <pavone@retrodev.com>
parents: 1357
diff changeset
624 context->sprite_info_list[context->slot_counter].y = y;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
625 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
626 context->sprite_index++;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
627 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
628
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
629 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1138
25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping
Michael Pavone <pavone@retrodev.com>
parents: 1137
diff changeset
630 y = context->vdpmem[sat_address];
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
631 if (y == 0xd0) {
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
632 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
633 return;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
634 } else {
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
635 if (y <= line && line < (y + size)) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
636 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
637 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
638 context->flags |= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
639 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
640 }
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
641 context->sprite_info_list[--(context->slot_counter)].size = size;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
642 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
1358
3716b90d3470 Fix regression in Mode 4 sprite rendering
Michael Pavone <pavone@retrodev.com>
parents: 1357
diff changeset
643 context->sprite_info_list[context->slot_counter].y = y;
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
644 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
645 context->sprite_index++;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
646 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
647 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
648
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
649 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
650 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
651
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
652 static void read_sprite_x(uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
653 {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
654 if (context->cur_slot == context->max_sprites_line) {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
655 context->cur_slot = 0;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
656 }
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
657 if (context->cur_slot < context->slot_counter) {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
658 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
659 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
660 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
661 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
662 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
663 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
664 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
665 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
666 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
667 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
668 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
669 height *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
670 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
671 uint16_t ymask, ymin;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
672 if (context->double_res) {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
673 ymask = 0x3FF;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
674 ymin = 256;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
675 } else {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
676 ymask = 0x1FF;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
677 ymin = 128;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
678 }
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
679 uint16_t att_addr = mode5_sat_address(context) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
680 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1];
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
681 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
682 uint8_t row;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
683 uint16_t cache_addr = context->sprite_info_list[context->cur_slot].index * 4;
1346
f7ca42e020fd Fix sprite rendering in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1344
diff changeset
684 line = (line + ymin) & ymask;
1338
3706b683cd48 Fix sprite rendering for negative line. Fixes remaining visual glitch in the Titancade scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1337
diff changeset
685 int16_t y = ((context->sat_cache[cache_addr] << 8 | context->sat_cache[cache_addr+1]) & ymask)/* - ymin*/;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
686 if (tileinfo & MAP_BIT_V_FLIP) {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
687 row = (y + height - 1) - line;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
688 } else {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
689 row = line-y;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
690 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
691 row &= ymask >> 4;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
692 uint16_t address;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
693 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
694 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
695 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
696 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
697 }
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
698 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
699 if (x) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
700 context->flags |= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
701 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
702 context->flags |= FLAG_MASKED;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
703 }
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
704
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
705 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
706 int16_t i;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
707 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
708 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
709 --context->sprite_draws;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
710 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
711 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
712 }
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
713 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
714 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
715 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
716 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
717 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
718 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
719 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
720 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
721 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
722 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
723 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35
233c7737c152 Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents: 34
diff changeset
724 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
725 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
726 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
727 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
728 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
729 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
730 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
731 }
1000
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
732 //Used to be i < width
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
733 //TODO: Confirm this is the right condition on hardware
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
734 if (!context->sprite_draws) {
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
735 context->flags |= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
736 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
737 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
738 context->flags |= FLAG_DOT_OFLOW;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
739 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
740 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
741 context->cur_slot++;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
742 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
743
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
744 static void read_sprite_x_mode4(vdp_context * context)
427
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
745 {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
746 if (context->cur_slot >= context->slot_counter) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
747 uint32_t address = (context->regs[REG_SAT] << 7 & 0x3F00) + 0x80 + context->sprite_info_list[context->cur_slot].index * 2;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
748 address = mode4_address_map[address];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
749 --context->sprite_draws;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
750 uint32_t tile_address = context->vdpmem[address] * 32 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
751 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
752 tile_address &= ~32;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
753 }
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
754 tile_address += (context->vcounter - context->sprite_info_list[context->cur_slot].y)* 4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
755 context->sprite_draw_list[context->sprite_draws].x_pos = context->vdpmem[address + 1];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
756 context->sprite_draw_list[context->sprite_draws].address = tile_address;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
757 context->cur_slot--;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
758 }
427
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
759 }
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
760
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
761 #define CRAM_BITS 0xEEE
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
762 #define VSRAM_BITS 0x7FF
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
763 #define VSRAM_DIRTY_BITS 0xF800
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
764
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
765 //rough estimate of slot number at which border display starts
1270
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
766 #define BG_START_SLOT 6
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
767
1431
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
768 static void update_color_map(vdp_context *context, uint16_t index, uint16_t value)
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
769 {
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
770 context->colors[index] = color_map[value & CRAM_BITS];
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
771 context->colors[index + SHADOW_OFFSET] = color_map[(value & CRAM_BITS) | FBUF_SHADOW];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
772 context->colors[index + HIGHLIGHT_OFFSET] = color_map[(value & CRAM_BITS) | FBUF_HILIGHT];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
773 context->colors[index + MODE4_OFFSET] = color_map[(value & CRAM_BITS) | FBUF_MODE4];
1431
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
774 }
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
775
1428
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
776 void write_cram_internal(vdp_context * context, uint16_t addr, uint16_t value)
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
777 {
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
778 context->cram[addr] = value;
1431
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
779 update_color_map(context, addr, value);
1428
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
780 }
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
781
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
782 static void write_cram(vdp_context * context, uint16_t address, uint16_t value)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
783 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
784 uint16_t addr;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
785 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
786 addr = (address/2) & (CRAM_SIZE-1);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
787 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
788 addr = address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
789 value = (value << 1 & 0xE) | (value << 2 & 0xE0) | (value & 0xE00);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
790 }
1428
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
791 write_cram_internal(context, addr, value);
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
792
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
793 if (context->hslot >= BG_START_SLOT && (
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
794 context->vcounter < context->inactive_start + context->border_bot
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
795 || context->vcounter > 0x200 - context->border_top
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
796 )) {
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
797 uint8_t bg_end_slot = BG_START_SLOT + (context->regs[REG_MODE_4] & BIT_H40) ? LINEBUF_SIZE/2 : (256+HORIZ_BORDER)/2;
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
798 if (context->hslot < bg_end_slot) {
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
799 uint32_t color = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->colors[addr] : context->colors[addr + MODE4_OFFSET];
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
800 context->output[(context->hslot - BG_START_SLOT)*2 + 1] = color;
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
801 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
802 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
803 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
804
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
805 static void vdp_advance_dma(vdp_context * context)
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
806 {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
807 context->regs[REG_DMASRC_L] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
808 if (!context->regs[REG_DMASRC_L]) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
809 context->regs[REG_DMASRC_M] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
810 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
811 context->address += context->regs[REG_AUTOINC];
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
812 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
813 context->regs[REG_DMALEN_H] = dma_len >> 8;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
814 context->regs[REG_DMALEN_L] = dma_len;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
815 if (!dma_len) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
816 context->flags &= ~FLAG_DMA_RUN;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
817 context->cd &= 0xF;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
818 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
819 }
1019
e34334e6c682 Fix GST savestate loading to deal with SAT cache to fix sprite corruption on savestate load. Clear out Z80 native_pc so the Z80 state does not get hosed when loading a savestate while the emulator is already running
Michael Pavone <pavone@retrodev.com>
parents: 1001
diff changeset
820
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
821 static void vdp_check_update_sat(vdp_context *context, uint32_t address, uint16_t value)
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
822 {
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
823 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
824 if (!(address & 4)) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
825 uint32_t sat_address = mode5_sat_address(context);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
826 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
827 uint16_t cache_address = address - sat_address;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
828 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
829 context->sat_cache[cache_address] = value >> 8;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
830 context->sat_cache[cache_address^1] = value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
831 }
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
832 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
833 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
834 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
835
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
836 void vdp_check_update_sat_byte(vdp_context *context, uint32_t address, uint8_t value)
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
837 {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
838 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
839 if (!(address & 4)) {
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
840 uint32_t sat_address = mode5_sat_address(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
841 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
842 uint16_t cache_address = address - sat_address;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
843 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
844 context->sat_cache[cache_address] = value;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
845 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
846 }
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
847 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
848 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
849
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
850 static void write_vram_word(vdp_context *context, uint32_t address, uint16_t value)
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
851 {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
852 address = (address & 0x3FC) | (address >> 1 & 0xFC01) | (address >> 9 & 0x2);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
853 address ^= 1;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
854 //TODO: Support an option to actually have 128KB of VRAM
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
855 context->vdpmem[address] = value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
856 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
857
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
858 static void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value)
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
859 {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
860 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
861 address &= 0xFFFF;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
862 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
863 address = mode4_address_map[address & 0x3FFF];
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
864 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
865 context->vdpmem[address] = value;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
866 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
867
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
868 #define DMA_FILL 0x80
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
869 #define DMA_COPY 0xC0
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
870 #define DMA_TYPE_MASK 0xC0
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
871 static void external_slot(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
872 {
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
873 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL && context->fifo_read < 0) {
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
874 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
875 fifo_entry * cur = context->fifo + context->fifo_read;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
876 cur->cycle = context->cycles;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
877 cur->address = context->address;
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
878 cur->partial = 1;
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
879 vdp_advance_dma(context);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
880 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
881 fifo_entry * start = context->fifo + context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
882 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
883 switch (start->cd & 0xF)
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
884 {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
885 case VRAM_WRITE:
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
886 if ((context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) == (BIT_128K_VRAM|BIT_MODE_5)) {
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
887 vdp_check_update_sat(context, start->address, start->value);
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
888 write_vram_word(context, start->address, start->value);
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
889 } else {
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
890 uint8_t byte = start->partial == 1 ? start->value >> 8 : start->value;
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
891 vdp_check_update_sat_byte(context, start->address ^ 1, byte);
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
892 write_vram_byte(context, start->address ^ 1, byte);
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
893 if (!start->partial) {
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
894 start->address = start->address ^ 1;
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
895 start->partial = 1;
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
896 //skip auto-increment and removal of entry from fifo
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
897 return;
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
898 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
899 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
900 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
901 case CRAM_WRITE: {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
902 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
903 if (start->partial == 3) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
904 uint16_t val;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
905 if ((start->address & 1) && (context->regs[REG_MODE_2] & BIT_MODE_5)) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
906 val = (context->cram[start->address >> 1 & (CRAM_SIZE-1)] & 0xFF) | start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
907 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
908 uint16_t address = (context->regs[REG_MODE_2] & BIT_MODE_5) ? start->address >> 1 & (CRAM_SIZE-1) : start->address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
909 val = (context->cram[address] & 0xFF00) | start->value;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
910 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
911 write_cram(context, start->address, val);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
912 } else {
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
913 write_cram(context, start->address, start->partial ? context->fifo[context->fifo_write].value : start->value);
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
914 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
915 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
916 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
917 case VSRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
918 if (((start->address/2) & 63) < VSRAM_SIZE) {
1432
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
919 //printf("VSRAM Write: %X to %X @ frame: %d, vcounter: %d, hslot: %d, cycle: %d\n", start->value, start->address, context->frame, context->vcounter, context->hslot, context->cycles);
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
920 if (start->partial == 3) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
921 if (start->address & 1) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
922 context->vsram[(start->address/2) & 63] &= 0xFF;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
923 context->vsram[(start->address/2) & 63] |= start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
924 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
925 context->vsram[(start->address/2) & 63] &= 0xFF00;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
926 context->vsram[(start->address/2) & 63] |= start->value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
927 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
928 } else {
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
929 context->vsram[(start->address/2) & 63] = start->partial ? context->fifo[context->fifo_write].value : start->value;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
930 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
931 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
932
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
933 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
934 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
935 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
936 if (context->fifo_read == context->fifo_write) {
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
937 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) {
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
938 context->flags |= FLAG_DMA_RUN;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
939 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
940 context->fifo_read = -1;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
941 }
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
942 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_COPY) {
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
943 if (context->flags & FLAG_READ_FETCHED) {
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
944 write_vram_byte(context, context->address ^ 1, context->prefetch);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
945
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
946 //Update DMA state
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
947 vdp_advance_dma(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
948
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
949 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
950 } else {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
951 context->prefetch = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
952
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
953 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
954 }
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
955 } else if (!(context->cd & 1) && !(context->flags & (FLAG_READ_FETCHED|FLAG_PENDING))) {
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
956 switch(context->cd & 0xF)
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
957 {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
958 case VRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
959 if (context->flags2 & FLAG2_READ_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
960 context->prefetch |= context->vdpmem[context->address | 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
961 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
962 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
963 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
964 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
965 } else {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
966 //TODO: 128K VRAM Mode
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
967 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
968 context->flags2 |= FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
969 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
970 break;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
971 case VRAM_READ8: {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
972 uint32_t address = context->address ^ 1;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
973 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
974 address = mode4_address_map[address & 0x3FFF];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
975 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
976 context->prefetch = context->vdpmem[address];
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
977 context->prefetch |= context->fifo[context->fifo_write].value & 0xFF00;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
978 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
979 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
980 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
981 break;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
982 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
983 case CRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
984 context->prefetch = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
985 context->prefetch |= context->fifo[context->fifo_write].value & ~CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
986 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
987 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
988 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
989 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
990 case VSRAM_READ: {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
991 uint16_t address = (context->address /2) & 63;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
992 if (address >= VSRAM_SIZE) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
993 address = 0;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
994 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
995 context->prefetch = context->vsram[address] & VSRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
996 context->prefetch |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
997 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
998 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
999 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
1000 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
1001 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
1002 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1003 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1004 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1005
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1006 static void run_dma_src(vdp_context * context, int32_t slot)
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1007 {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1008 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1009 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1010 if (context->fifo_write == context->fifo_read) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1011 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1012 }
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1013 fifo_entry * cur = NULL;
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1014 if (!(context->regs[REG_DMASRC_H] & 0x80))
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1015 {
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1016 //68K -> VDP
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
1017 if (slot == -1 || !is_refresh(context, slot-1)) {
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1018 cur = context->fifo + context->fifo_write;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
1019 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1020 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1021 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1022 cur->cd = context->cd;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1023 cur->partial = 0;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1024 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1025 context->fifo_read = context->fifo_write;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1026 }
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1027 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1028 vdp_advance_dma(context);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1029 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1030 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1031 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1032
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1033 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1034 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1035
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1036 static void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1037 {
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1038 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1039 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1040 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
1041 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1042 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1043 }
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1044 window_line_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1045 v_offset_mask = 0xF;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1046 vscroll_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1047 } else {
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1048 window_line_shift = 3;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1049 v_offset_mask = 0x7;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1050 vscroll_shift = 3;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1051 }
1344
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1052 //TODO: Further research on vscroll latch behavior and the "first column bug"
1422
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
1053 if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
1054 if (!column) {
1344
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1055 if (context->regs[REG_MODE_4] & BIT_H40) {
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1056 //Based on observed behavior documented by Eke-Eke, I'm guessing the VDP
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1057 //ends up fetching the last value on the VSRAM bus in the H40 case
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1058 //getting the last latched value should be close enough for now
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1059 if (!vsram_off) {
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1060 context->vscroll_latch[0] = context->vscroll_latch[1];
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1061 }
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1062 } else {
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1063 //supposedly it's always forced to 0 in the H32 case
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1064 context->vscroll_latch[0] = context->vscroll_latch[1] = 0;
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1065 }
1422
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
1066 } else if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
1067 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off];
1344
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1068 }
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1069 }
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1070 if (!vsram_off) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1071 uint16_t left_col, right_col;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1072 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
920
e64168bb2b25 Fix calculation of window start column when it's on the right side. This removes graphical glitches in Afterburner 2, Fireshark and Dungeons and Dragons: Warriors of the Eternal Sun and probably others
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
1073 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2 + 2;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1074 right_col = 42;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1075 } else {
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1076 left_col = 0;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1077 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1078 if (right_col) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1079 right_col += 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1080 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1081 }
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1082 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1083 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1084 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1085 bottom_line = context->double_res ? 481 : 241;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1086 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1087 top_line = 0;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1088 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1089 }
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1090 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1091 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1092 uint16_t line_offset, offset, mask;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
1093 if (context->regs[REG_MODE_4] & BIT_H40) {
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1094 address &= 0xF000;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1095 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1096 mask = 0x7F;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
1097
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1098 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1099 address &= 0xF800;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1100 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1101 mask = 0x3F;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1102 }
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1103 if (context->double_res) {
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1104 mask <<= 1;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1105 mask |= 1;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1106 }
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
1107 offset = address + line_offset + (((column - 2) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1108 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1109 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
1110 offset = address + line_offset + (((column - 1) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1111 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1112 context->v_offset = (line) & v_offset_mask;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1113 context->flags |= FLAG_WINDOW;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1114 return;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1115 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1116 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1117 }
1290
aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk
Michael Pavone <pavone@retrodev.com>
parents: 1289
diff changeset
1118 //TODO: Verify behavior for 0x20 case
aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk
Michael Pavone <pavone@retrodev.com>
parents: 1289
diff changeset
1119 uint16_t vscroll = 0xFF | (context->regs[REG_SCROLL] & 0x30) << 4;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1120 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1121 vscroll <<= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1122 vscroll |= 1;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1123 }
710
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents: 708
diff changeset
1124 vscroll &= context->vscroll_latch[vsram_off] + line;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1125 context->v_offset = vscroll & v_offset_mask;
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
1126 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1127 vscroll >>= vscroll_shift;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1128 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1129 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1130 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1131 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1132 case 0:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1133 hscroll_mask = 0x1F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1134 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1135 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1136 case 0x1:
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1137 hscroll_mask = 0x3F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1138 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1139 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1140 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1141 //TODO: Verify this behavior
1334
7757d605e365 Adjust how the invalid size is handled for the horizontal dimmension of a plane. Fixes some garbage on the spinning cube scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1333
diff changeset
1142 hscroll_mask = 0x1F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1143 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1144 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1145 case 0x3:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1146 hscroll_mask = 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1147 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1148 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1149 }
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1150 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1151 for (int i = 0; i < 2; i++) {
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1152 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1153 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1154 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1155 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1156 if (i) {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1157 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1158 } else {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1159 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1160 }
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1161 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1162 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1163
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1164 static void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1165 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
1166 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1167 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1168
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1169 static void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1170 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
1171 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1172 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1173
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1174 static void read_map_mode4(uint16_t column, uint32_t line, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1175 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1176 uint32_t address = (context->regs[REG_SCROLL_A] & 0xE) << 10;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1177 //add row
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1178 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1179 if (column < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1180 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1181 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1182 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1183 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1184 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1185 address += (vscroll >> 3) * 2 * 32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1186 //add column
1136
52f25c41abdd Fix horizontal scrolling in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1135
diff changeset
1187 address += ((column - (context->hscroll_a >> 3)) & 31) * 2;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1188 //adjust for weird VRAM mapping in Mode 4
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1189 address = mode4_address_map[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1190 context->col_1 = (context->vdpmem[address] << 8) | context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1191 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1192
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1193 static void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1194 {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1195 uint16_t address;
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1196 uint16_t vflip_base;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1197 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1198 address = ((col & 0x3FF) << 6);
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1199 vflip_base = 60;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1200 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1201 address = ((col & 0x7FF) << 5);
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1202 vflip_base = 28;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1203 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1204 if (col & MAP_BIT_V_FLIP) {
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1205 address += vflip_base - 4 * context->v_offset;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1206 } else {
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1207 address += 4 * context->v_offset;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1208 }
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1209 uint8_t pal_priority = (col >> 9) & 0x70;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1210 uint32_t bits = *((uint32_t *)(&context->vdpmem[address]));
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1211 if (col & MAP_BIT_H_FLIP) {
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1212 uint32_t shift = 28;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1213 for (int i = 0; i < 4; i++)
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1214 {
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1215 uint8_t right = pal_priority | ((bits >> shift) & 0xF);
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1216 shift -= 4;
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1217 tmp_buf[offset++] = pal_priority | ((bits >> shift) & 0xF);
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1218 shift -= 4;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1219 offset &= SCROLL_BUFFER_MASK;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1220 tmp_buf[offset++] = right;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1221 offset &= SCROLL_BUFFER_MASK;
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1222 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1223 } else {
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1224 for (int i = 0; i < 4; i++)
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1225 {
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1226 uint8_t right = pal_priority | (bits & 0xF);
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1227 bits >>= 4;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1228 tmp_buf[offset++] = pal_priority | (bits & 0xF);
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1229 offset &= SCROLL_BUFFER_MASK;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1230 bits >>= 4;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1231 tmp_buf[offset++] = right;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1232 offset &= SCROLL_BUFFER_MASK;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1233 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1234 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1235 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1236
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1237 static void render_map_1(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1238 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1239 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1240 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1241
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1242 static void render_map_2(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1243 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1244 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1245 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1246
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1247 static void render_map_3(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1248 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1249 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1250 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1251
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1252 static void fetch_map_mode4(uint16_t col, uint32_t line, vdp_context *context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1253 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1254 //calculate pixel row to fetch
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1255 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1256 if (col < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1257 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1258 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1259 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1260 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1261 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1262 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1263 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1264 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1265 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1266
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1267 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1268 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1269 context->fetch_tmp[1] = context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1270 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1271
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1272 static uint8_t composite_normal(vdp_context *context, uint8_t *debug_dst, uint8_t sprite, uint8_t plane_a, uint8_t plane_b, uint8_t bg_index)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1273 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1274 uint8_t pixel = bg_index;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1275 uint8_t src = DBG_SRC_BG;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1276 if (plane_b & 0xF) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1277 pixel = plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1278 src = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1279 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1280 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1281 pixel = plane_a;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1282 src = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1283 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1284 if (sprite & 0xF && (sprite & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1285 pixel = sprite;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1286 src = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1287 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1288 *debug_dst = src;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1289 return pixel;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1290 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1291 typedef struct {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1292 uint8_t index, intensity;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1293 } sh_pixel;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1294
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1295 static sh_pixel composite_highlight(vdp_context *context, uint8_t *debug_dst, uint8_t sprite, uint8_t plane_a, uint8_t plane_b, uint8_t bg_index)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1296 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1297 uint8_t pixel = bg_index;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1298 uint8_t src = DBG_SRC_BG;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1299 uint8_t intensity = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1300 if (plane_b & 0xF) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1301 pixel = plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1302 src = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1303 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1304 intensity = plane_b & BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1305 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1306 pixel = plane_a;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1307 src = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1308 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1309 intensity |= plane_a & BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1310 if (sprite & 0xF && (sprite & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1311 if ((sprite & 0x3F) == 0x3E) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1312 intensity += BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1313 } else if ((sprite & 0x3F) == 0x3F) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1314 intensity = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1315 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1316 pixel = sprite;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1317 src = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1318 if ((pixel & 0xF) == 0xE) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1319 intensity = BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1320 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1321 intensity |= pixel & BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1322 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1323 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1324 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1325 *debug_dst = src;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1326 return (sh_pixel){.index = pixel, .intensity = intensity};
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1327 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1328
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1329 static void render_normal(vdp_context *context, int32_t col, uint8_t *dst, uint8_t *debug_dst, int plane_a_off, int plane_b_off)
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1330 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1331 int start = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1332 if (!col && (context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1333 memset(dst, 0, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1334 memset(debug_dst, DBG_SRC_BG, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1335 dst += 8;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1336 debug_dst += 8;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1337 start = 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1338 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1339 uint8_t *sprite_buf = context->linebuf + col * 8 + start;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1340 for (int i = start; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1341 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1342 uint8_t sprite, plane_a, plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1343 plane_a = context->tmp_buf_a[plane_a_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1344 plane_b = context->tmp_buf_b[plane_b_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1345 sprite = *sprite_buf;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1346 *(dst++) = composite_normal(context, debug_dst, sprite, plane_a, plane_b, context->regs[REG_BG_COLOR]) & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1347 debug_dst++;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1348 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1349 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1350
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1351 static void render_highlight(vdp_context *context, int32_t col, uint8_t *dst, uint8_t *debug_dst, int plane_a_off, int plane_b_off)
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1352 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1353 int start = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1354 if (!col && (context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1355 memset(dst, SHADOW_OFFSET + (context->regs[REG_BG_COLOR] & 0x3F), 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1356 memset(debug_dst, DBG_SRC_BG | DBG_SHADOW, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1357 dst += 8;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1358 debug_dst += 8;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1359 start = 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1360 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1361 uint8_t *sprite_buf = context->linebuf + col * 8 + start;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1362 for (int i = start; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1363 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1364 uint8_t sprite, plane_a, plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1365 plane_a = context->tmp_buf_a[plane_a_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1366 plane_b = context->tmp_buf_b[plane_b_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1367 sprite = *sprite_buf;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1368 sh_pixel pixel = composite_highlight(context, debug_dst, sprite, plane_a, plane_b, context->regs[REG_BG_COLOR]);
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1369 uint8_t final_pixel;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1370 if (pixel.intensity == BUF_BIT_PRIORITY << 1) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1371 final_pixel = (pixel.index & 0x3F) + HIGHLIGHT_OFFSET;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1372 } else if (pixel.intensity) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1373 final_pixel = pixel.index & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1374 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1375 final_pixel = (pixel.index & 0x3F) + SHADOW_OFFSET;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1376 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1377 debug_dst++;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1378 *(dst++) = final_pixel;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1379 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1380 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1381
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1382 static void render_testreg(vdp_context *context, int32_t col, uint8_t *dst, uint8_t *debug_dst, int plane_a_off, int plane_b_off, uint8_t output_disabled, uint8_t test_layer)
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1383 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1384 if (output_disabled) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1385 switch (test_layer)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1386 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1387 case 0:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1388 for (int i = 0; i < 16; i++)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1389 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1390 *(dst++) = 0x3F; //TODO: confirm this on hardware
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1391 *(debug_dst++) = DBG_SRC_BG;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1392 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1393 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1394 case 1: {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1395 uint8_t *sprite_buf = context->linebuf + col * 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1396 for (int i = 0; i < 16; i++)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1397 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1398 *(dst++) = *(sprite_buf++) & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1399 *(debug_dst++) = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1400 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1401 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1402 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1403 case 2:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1404 for (int i = 0; i < 16; i++)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1405 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1406 *(dst++) = context->tmp_buf_a[(plane_a_off++) & SCROLL_BUFFER_MASK] & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1407 *(debug_dst++) = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1408 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1409 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1410 case 3:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1411 for (int i = 0; i < 16; i++)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1412 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1413 *(dst++) = context->tmp_buf_b[(plane_b_off++) & SCROLL_BUFFER_MASK] & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1414 *(debug_dst++) = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1415 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1416 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1417 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1418 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1419 int start = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1420 uint8_t *sprite_buf = context->linebuf + col * 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1421 if (!col && (context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1422 //TODO: Confirm how test register interacts with column 0 blanking
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1423 uint8_t pixel = 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1424 uint8_t src = DBG_SRC_BG;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1425 for (int i = 0; i < 8; ++i)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1426 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1427 switch (test_layer)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1428 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1429 case 1:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1430 pixel &= sprite_buf[i];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1431 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1432 src = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1433 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1434 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1435 case 2:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1436 pixel &= context->tmp_buf_a[(plane_a_off + i) & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1437 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1438 src = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1439 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1440 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1441 case 3:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1442 pixel &= context->tmp_buf_b[(plane_b_off + i) & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1443 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1444 src = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1445 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1446 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1447 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1448
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1449 *(dst++) = pixel;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1450 *(debug_dst++) = src;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1451 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1452 plane_a_off += 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1453 plane_b_off += 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1454 sprite_buf += 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1455 start = 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1456 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1457 for (int i = start; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1458 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1459 uint8_t sprite, plane_a, plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1460 plane_a = context->tmp_buf_a[plane_a_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1461 plane_b = context->tmp_buf_b[plane_b_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1462 sprite = *sprite_buf;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1463 uint8_t pixel = composite_normal(context, debug_dst, sprite, plane_a, plane_b, 0x3F) & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1464 switch (test_layer)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1465 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1466 case 1:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1467 pixel &= sprite;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1468 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1469 *debug_dst = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1470 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1471 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1472 case 2:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1473 pixel &= plane_a;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1474 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1475 *debug_dst = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1476 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1477 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1478 case 3:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1479 pixel &= plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1480 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1481 *debug_dst = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1482 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1483 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1484 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1485 debug_dst++;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1486 *(dst++) = pixel;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1487 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1488 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1489 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1490
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1491 static void render_testreg_highlight(vdp_context *context, int32_t col, uint8_t *dst, uint8_t *debug_dst, int plane_a_off, int plane_b_off, uint8_t output_disabled, uint8_t test_layer)
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1492 {
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1493 int start = 0;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1494 uint8_t *sprite_buf = context->linebuf + col * 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1495 if (!col && (context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1496 //TODO: Confirm how test register interacts with column 0 blanking
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1497 uint8_t pixel = 0x3F;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1498 uint8_t src = DBG_SRC_BG | DBG_SHADOW;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1499 for (int i = 0; i < 8; ++i)
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1500 {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1501 switch (test_layer)
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1502 {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1503 case 1:
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1504 pixel &= sprite_buf[i];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1505 if (pixel) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1506 src = DBG_SRC_S | DBG_SHADOW;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1507 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1508 break;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1509 case 2:
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1510 pixel &= context->tmp_buf_a[(plane_a_off + i) & SCROLL_BUFFER_MASK];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1511 if (pixel) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1512 src = DBG_SRC_A | DBG_SHADOW;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1513 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1514 break;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1515 case 3:
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1516 pixel &= context->tmp_buf_b[(plane_b_off + i) & SCROLL_BUFFER_MASK];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1517 if (pixel) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1518 src = DBG_SRC_B | DBG_SHADOW;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1519 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1520 break;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1521 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1522
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1523 *(dst++) = SHADOW_OFFSET + pixel;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1524 *(debug_dst++) = src;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1525 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1526 plane_a_off += 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1527 plane_b_off += 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1528 sprite_buf += 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1529 start = 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1530 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1531 for (int i = start; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i)
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1532 {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1533 uint8_t sprite, plane_a, plane_b;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1534 plane_a = context->tmp_buf_a[plane_a_off & SCROLL_BUFFER_MASK];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1535 plane_b = context->tmp_buf_b[plane_b_off & SCROLL_BUFFER_MASK];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1536 sprite = *sprite_buf;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1537 sh_pixel pixel = composite_highlight(context, debug_dst, sprite, plane_a, plane_b, 0x3F);
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1538 if (output_disabled) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1539 pixel.index = 0x3F;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1540 } else {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1541 pixel.index &= 0x3F;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1542 }
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1543 switch (test_layer)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1544 {
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1545 case 1:
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1546 pixel.index &= sprite;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1547 if (pixel.index) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1548 *debug_dst = DBG_SRC_S;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1549 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1550 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1551 case 2:
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1552 pixel.index &= plane_a;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1553 if (pixel.index) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1554 *debug_dst = DBG_SRC_A;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1555 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1556 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1557 case 3:
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1558 pixel.index &= plane_b;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1559 if (pixel.index) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1560 *debug_dst = DBG_SRC_B;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1561 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1562 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1563 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1564 if (pixel.intensity == BUF_BIT_PRIORITY << 1) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1565 pixel.index += HIGHLIGHT_OFFSET;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1566 } else if (!pixel.intensity) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1567 pixel.index += SHADOW_OFFSET;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1568 }
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1569 debug_dst++;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1570 *(dst++) = pixel.index;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1571 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1572 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1573
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1574 static void render_map_output(uint32_t line, int32_t col, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1575 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1576 uint8_t *dst;
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1577 uint8_t *debug_dst;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1578 uint8_t output_disabled = (context->test_port & TEST_BIT_DISABLE) != 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1579 uint8_t test_layer = context->test_port >> 7 & 3;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
1580 if (context->state == PREPARING && !test_layer) {
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1581 if (col) {
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1582 col -= 2;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1583 dst = context->compositebuf + BORDER_LEFT + col * 8;
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1584 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1585 dst = context->compositebuf;
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1586 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1587 memset(dst, 0, BORDER_LEFT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1588 context->done_composite = dst + BORDER_LEFT;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1589 return;
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1590 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1591 memset(dst, 0, 16);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1592 context->done_composite = dst + 16;
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1593 return;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1594 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1595 line &= 0xFF;
1180
e2b81a0f8fd8 Undo poorly thought out minor optimization that screwed up rendering
Michael Pavone <pavone@retrodev.com>
parents: 1179
diff changeset
1596 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1597 uint8_t *sprite_buf;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1598 uint8_t sprite, plane_a, plane_b;
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1599 int plane_a_off, plane_b_off;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1600 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1601 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1602 col-=2;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1603 dst = context->compositebuf + BORDER_LEFT + col * 8;
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1604 debug_dst = context->layer_debug_buf + BORDER_LEFT + col * 8;
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1605
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1606
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1607 uint8_t a_src, src;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1608 if (context->flags & FLAG_WINDOW) {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1609 plane_a_off = context->buf_a_off;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1610 a_src = DBG_SRC_W;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1611 } else {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1612 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF);
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1613 a_src = DBG_SRC_A;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1614 }
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1615 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF);
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1616 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1617
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1618 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1619 if (output_disabled || test_layer) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1620 render_testreg_highlight(context, col, dst, debug_dst, plane_a_off, plane_b_off, output_disabled, test_layer);
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1621 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1622 render_highlight(context, col, dst, debug_dst, plane_a_off, plane_b_off);
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1623 }
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1624 } else {
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1625 if (output_disabled || test_layer) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1626 render_testreg(context, col, dst, debug_dst, plane_a_off, plane_b_off, output_disabled, test_layer);
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1627 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1628 render_normal(context, col, dst, debug_dst, plane_a_off, plane_b_off);
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
1629 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1630 }
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1631 dst += 16;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1632 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1633 dst = context->compositebuf;
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1634 debug_dst = context->layer_debug_buf;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1635 uint8_t pixel = 0;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1636 if (output_disabled) {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1637 pixel = 0x3F;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1638 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1639 if (test_layer) {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1640 switch(test_layer)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1641 {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1642 case 1:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1643 memset(dst, 0, BORDER_LEFT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1644 memset(debug_dst, DBG_SRC_BG, BORDER_LEFT);
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1645 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1646 case 2: {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1647 //plane A
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1648 //TODO: Deal with Window layer
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1649 int i;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1650 i = 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1651 uint8_t buf_off = context->buf_a_off - (context->hscroll_a & 0xF) + (16 - BORDER_LEFT);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1652 //uint8_t *src = context->tmp_buf_a + ((context->buf_a_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_a & 0xF))) & SCROLL_BUFFER_MASK);
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1653 for (; i < BORDER_LEFT; buf_off++, i++, dst++, debug_dst++)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1654 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1655 *dst = context->tmp_buf_a[buf_off & SCROLL_BUFFER_MASK];
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1656 *debug_dst = DBG_SRC_A;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1657 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1658 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1659 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1660 case 3: {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1661 //plane B
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1662 int i;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1663 i = 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1664 uint8_t buf_off = context->buf_b_off - (context->hscroll_b & 0xF) + (16 - BORDER_LEFT);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1665 //uint8_t *src = context->tmp_buf_b + ((context->buf_b_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_b & 0xF))) & SCROLL_BUFFER_MASK);
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1666 for (; i < BORDER_LEFT; buf_off++, i++, dst++, debug_dst++)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1667 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1668 *dst = context->tmp_buf_b[buf_off & SCROLL_BUFFER_MASK];
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1669 *debug_dst = DBG_SRC_B;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1670 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1671 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1672 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1673 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1674 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1675 memset(dst, pixel, BORDER_LEFT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1676 memset(debug_dst, DBG_SRC_BG, BORDER_LEFT);
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1677 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1678 dst += BORDER_LEFT;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1679 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1680 context->done_composite = dst;
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1681 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1682 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1683 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1684
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1685 static void render_map_mode4(uint32_t line, int32_t col, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1686 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1687 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1688 if (col < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1689 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1690 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1691 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1692 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1693 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1694 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1695 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1696 //vflip
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1697 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1698 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1699
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1700 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1701 pixels |= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1702
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1703 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4 + 2];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1704 pixels |= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1705 pixels |= planar_to_chunky[context->vdpmem[address+1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1706
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1707 int i, i_inc, i_limit;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1708 if (context->col_1 & 0x200) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1709 //hflip
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1710 i = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1711 i_inc = 4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1712 i_limit = 32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1713 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1714 i = 28;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1715 i_inc = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1716 i_limit = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1717 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1718 uint8_t pal_priority = (context->col_1 >> 7 & 0x10) | (context->col_1 >> 6 & 0x40);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1719 for (uint8_t *dst = context->tmp_buf_a + context->buf_a_off; i != i_limit; i += i_inc, dst++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1720 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1721 *dst = (pixels >> i & 0xF) | pal_priority;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1722 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1723 context->buf_a_off = (context->buf_a_off + 8) & 15;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1724
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1725 uint8_t *dst = context->compositebuf + col * 8 + BORDER_LEFT;
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1726 uint8_t *debug_dst = context->layer_debug_buf + col * 8 + BORDER_LEFT;
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
1727 if (context->state == PREPARING) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1728 memset(dst, 0, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1729 memset(debug_dst, DBG_SRC_BG, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1730 context->done_composite = dst + 8;
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
1731 return;
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
1732 }
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1733
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1734 if (col || !(context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1735 uint8_t *sprite_src = context->linebuf + col * 8;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1736 if (context->regs[REG_MODE_1] & BIT_SPRITE_8PX) {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1737 sprite_src += 8;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1738 }
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1739 for (int i = 0; i < 8; i++, sprite_src++)
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1740 {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1741 uint8_t *bg_src = context->tmp_buf_a + ((8 + i + col * 8 - (context->hscroll_a & 0x7)) & 15);
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1742 if ((*bg_src & 0x4F) > 0x40 || !*sprite_src) {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1743 //background plane has priority and is opaque or sprite layer is transparent
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1744 uint8_t pixel = *bg_src & 0x1F;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1745 *(dst++) = pixel + MODE4_OFFSET;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1746 *(debug_dst++) = pixel ? DBG_SRC_A : DBG_SRC_BG;
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1747 } else {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1748 //sprite layer is opaque and not covered by high priority BG pixels
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1749 *(dst++) = (*sprite_src | 0x10) + MODE4_OFFSET;
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1750 *(debug_dst++) = DBG_SRC_S;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1751 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1752 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1753 context->done_composite = dst;
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1754 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1755 memset(dst, 0, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1756 memset(dst, DBG_SRC_BG, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1757 context->done_composite = dst + 8;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1758 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1759 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1760
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1761 static uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19};
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1762
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1763 static void vdp_advance_line(vdp_context *context)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1764 {
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1765 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1766 static uint32_t last_line = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1767 if (last_line != 0xFFFFFFFF) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1768 uint32_t diff = context->cycles - last_line;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1769 if (diff != MCLKS_LINE) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1770 printf("Line %d took %d cycles\n", context->vcounter, diff);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1771 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1772 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1773 last_line = context->cycles;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1774 #endif
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1775 uint16_t jump_start, jump_end;
1156
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1776 uint8_t is_mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1777 if (is_mode_5) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1778 if (context->flags2 & FLAG2_REGION_PAL) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1779 if (context->regs[REG_MODE_2] & BIT_PAL) {
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1780 jump_start = 0x10B;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1781 jump_end = 0x1D2;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1782 } else {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1783 jump_start = 0x103;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1784 jump_end = 0x1CA;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1785 }
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1786 } else if (context->regs[REG_MODE_2] & BIT_PAL) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1787 jump_start = 0x100;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1788 jump_end = 0x1FA;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1789 } else {
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1790 jump_start = 0xEB;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1791 jump_end = 0x1E5;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1792 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1793 } else {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1794 jump_start = 0xDB;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1795 jump_end = 0x1D5;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1796 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1797
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1798 if (context->enabled_debuggers & (1 << VDP_DEBUG_CRAM | 1 << VDP_DEBUG_COMPOSITE)) {
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1799 uint32_t line = context->vcounter;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1800 if (line >= jump_end) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1801 line -= jump_end - jump_start;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1802 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1803 uint32_t total_lines = (context->flags2 & FLAG2_REGION_PAL) ? 313 : 262;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1804
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1805 if (total_lines - line <= context->border_top) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1806 line -= total_lines - context->border_top;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1807 } else {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1808 line += context->border_top;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1809 }
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1810 if (context->enabled_debuggers & (1 << VDP_DEBUG_CRAM)) {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1811 uint32_t *fb = context->debug_fbs[VDP_DEBUG_CRAM] + context->debug_fb_pitch[VDP_DEBUG_CRAM] * line / sizeof(uint32_t);
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1812 for (int i = 0; i < 64; i++)
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1813 {
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1814 for (int x = 0; x < 8; x++)
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1815 {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1816 *(fb++) = context->colors[i];
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1817 }
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1818 }
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1819 }
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1820 if (
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1821 context->enabled_debuggers & (1 << VDP_DEBUG_COMPOSITE)
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1822 && line < (context->inactive_start + context->border_bot + context->border_top)
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1823 ) {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1824 uint32_t *fb = context->debug_fbs[VDP_DEBUG_COMPOSITE] + context->debug_fb_pitch[VDP_DEBUG_COMPOSITE] * line / sizeof(uint32_t);
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1825 for (int i = 0; i < LINEBUF_SIZE; i++)
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1826 {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1827 *(fb++) = context->debugcolors[context->layer_debug_buf[i]];
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1828 }
1299
da1ffc4026c4 Fix latching of V32 mode bit
Michael Pavone <pavone@retrodev.com>
parents: 1290
diff changeset
1829 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1830 }
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1831
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1832 context->vcounter++;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1833 if (context->vcounter == jump_start) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1834 context->vcounter = jump_end;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1835 } else {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1836 context->vcounter &= 0x1FF;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1837 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1838 if (context->state == PREPARING) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1839 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1840 }
1377
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
1841 if (context->vcounter == 0x1FF) {
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
1842 context->flags2 &= ~FLAG2_PAUSE;
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
1843 }
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1844
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1845 if (context->state != ACTIVE) {
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1846 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1847 } else if (context->hint_counter) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1848 context->hint_counter--;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1849 } else {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1850 context->flags2 |= FLAG2_HINT_PENDING;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1851 context->pending_hint_start = context->cycles;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1852 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1853 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1854 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1855
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1856 static void vdp_update_per_frame_debug(vdp_context *context)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1857 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1858 if (context->enabled_debuggers & (1 << VDP_DEBUG_PLANE)) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1859 uint32_t pitch;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1860 uint32_t *fb = render_get_framebuffer(context->debug_fb_indices[VDP_DEBUG_PLANE], &pitch);
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1861 uint16_t hscroll_mask;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1862 uint16_t v_mul;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1863 uint16_t vscroll_mask = 0x1F | (context->regs[REG_SCROLL] & 0x30) << 1;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1864 switch(context->regs[REG_SCROLL] & 0x3)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1865 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1866 case 0:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1867 hscroll_mask = 0x1F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1868 v_mul = 64;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1869 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1870 case 0x1:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1871 hscroll_mask = 0x3F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1872 v_mul = 128;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1873 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1874 case 0x2:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1875 //TODO: Verify this behavior
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1876 hscroll_mask = 0x1F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1877 v_mul = 0;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1878 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1879 case 0x3:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1880 hscroll_mask = 0x7F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1881 v_mul = 256;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1882 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1883 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1884 uint16_t table_address;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1885 switch(context->debug_modes[VDP_DEBUG_PLANE] % 3)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1886 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1887 case 0:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1888 table_address = context->regs[REG_SCROLL_A] << 10 & 0xE000;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1889 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1890 case 1:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1891 table_address = context->regs[REG_SCROLL_B] << 13 & 0xE000;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1892 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1893 case 2:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1894 table_address = context->regs[REG_WINDOW] << 10;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1895 if (context->regs[REG_MODE_4] & BIT_H40) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1896 table_address &= 0xF000;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1897 v_mul = 128;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1898 hscroll_mask = 0x3F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1899 } else {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1900 table_address &= 0xF800;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1901 v_mul = 64;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1902 hscroll_mask = 0x1F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1903 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1904 vscroll_mask = 0x1F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1905 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1906 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1907 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR & 0x3F]];
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1908 for (uint16_t row = 0; row < 128; row++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1909 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1910 uint16_t row_address = table_address + (row & vscroll_mask) * v_mul;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1911 for (uint16_t col = 0; col < 128; col++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1912 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1913 uint16_t address = row_address + (col & hscroll_mask) * 2;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1914 //pccv hnnn nnnn nnnn
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1915 //
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1916 uint16_t entry = context->vdpmem[address] << 8 | context->vdpmem[address + 1];
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1917 uint8_t pal = entry >> 9 & 0x30;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1918
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1919 uint32_t *dst = fb + (row * pitch * 8 / sizeof(uint32_t)) + col * 8;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1920 address = (entry & 0x7FF) * 32;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1921 int y_diff = 4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1922 if (entry & 0x1000) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1923 y_diff = -4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1924 address += 7 * 4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1925 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1926 int x_diff = 1;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1927 if (entry & 0x800) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1928 x_diff = -1;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1929 address += 3;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1930 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1931 for (int y = 0; y < 8; y++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1932 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1933 uint16_t trow_address = address;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1934 uint32_t *row_dst = dst;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1935 for (int x = 0; x < 4; x++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1936 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1937 uint8_t byte = context->vdpmem[trow_address];
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1938 trow_address += x_diff;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1939 uint8_t left, right;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1940 if (x_diff > 0) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1941 left = byte >> 4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1942 right = byte & 0xF;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1943 } else {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1944 left = byte & 0xF;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1945 right = byte >> 4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1946 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1947 *(row_dst++) = left ? context->colors[left|pal] : bg_color;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1948 *(row_dst++) = right ? context->colors[right|pal] : bg_color;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1949 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1950 address += y_diff;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1951 dst += pitch / sizeof(uint32_t);
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1952 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1953 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1954 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1955 render_framebuffer_updated(context->debug_fb_indices[VDP_DEBUG_PLANE], 1024);
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1956 }
1634
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1957
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1958 if (context->enabled_debuggers & (1 << VDP_DEBUG_VRAM)) {
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1959 uint32_t pitch;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1960 uint32_t *fb = render_get_framebuffer(context->debug_fb_indices[VDP_DEBUG_VRAM], &pitch);
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1961
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1962 uint8_t pal = (context->debug_modes[VDP_DEBUG_VRAM] % 4) << 4;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1963 for (int y = 0; y < 512; y++)
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1964 {
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1965 uint32_t *line = fb + y * pitch / sizeof(uint32_t);
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1966 int row = y >> 4;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1967 int yoff = y >> 1 & 7;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1968 for (int col = 0; col < 64; col++)
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1969 {
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1970 uint16_t address = (row * 64 + col) * 32 + yoff * 4;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1971 for (int x = 0; x < 4; x++)
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1972 {
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1973 uint8_t byte = context->vdpmem[address++];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1974 uint8_t left = byte >> 4 | pal;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1975 uint8_t right = byte & 0xF | pal;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1976 *(line++) = context->colors[left];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1977 *(line++) = context->colors[left];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1978 *(line++) = context->colors[right];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1979 *(line++) = context->colors[right];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1980 }
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1981 }
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1982 }
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1983
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1984 render_framebuffer_updated(context->debug_fb_indices[VDP_DEBUG_VRAM], 1024);
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1985 }
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1986
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1987 if (context->enabled_debuggers & (1 << VDP_DEBUG_CRAM)) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1988 uint32_t starting_line = 512 - 32*4;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1989 uint32_t *line = context->debug_fbs[VDP_DEBUG_CRAM]
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1990 + context->debug_fb_pitch[VDP_DEBUG_CRAM] * starting_line / sizeof(uint32_t);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1991 for (int pal = 0; pal < 4; pal ++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1992 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1993 uint32_t *cur;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1994 for (int y = 0; y < 31; y++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1995 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1996 cur = line;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1997 for (int offset = 0; offset < 16; offset++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1998 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1999 for (int x = 0; x < 31; x++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2000 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2001 *(cur++) = context->colors[pal * 16 + offset];
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2002 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2003 *(cur++) = 0xFF000000;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2004 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2005 line += context->debug_fb_pitch[VDP_DEBUG_CRAM] / sizeof(uint32_t);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2006 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2007 cur = line;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2008 for (int x = 0; x < 512; x++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2009 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2010 *(cur++) = 0xFF000000;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2011 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2012 line += context->debug_fb_pitch[VDP_DEBUG_CRAM] / sizeof(uint32_t);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2013 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2014 render_framebuffer_updated(context->debug_fb_indices[VDP_DEBUG_CRAM], 512);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2015 context->debug_fbs[VDP_DEBUG_CRAM] = render_get_framebuffer(context->debug_fb_indices[VDP_DEBUG_CRAM], &context->debug_fb_pitch[VDP_DEBUG_CRAM]);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2016 }
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
2017 if (context->enabled_debuggers & (1 << VDP_DEBUG_COMPOSITE)) {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
2018 render_framebuffer_updated(context->debug_fb_indices[VDP_DEBUG_COMPOSITE], LINEBUF_SIZE);
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
2019 context->debug_fbs[VDP_DEBUG_COMPOSITE] = render_get_framebuffer(context->debug_fb_indices[VDP_DEBUG_COMPOSITE], &context->debug_fb_pitch[VDP_DEBUG_COMPOSITE]);
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
2020 }
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
2021 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
2022
1629
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2023 void vdp_force_update_framebuffer(vdp_context *context)
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2024 {
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2025 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL)
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2026 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2027 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28;
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2028
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2029 uint16_t to_fill = lines_max - context->output_lines;
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2030 memset(
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2031 ((char *)context->fb) + context->output_pitch * context->output_lines,
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2032 0,
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2033 to_fill * context->output_pitch
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2034 );
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2035 render_framebuffer_updated(context->cur_buffer, context->h40_lines > context->output_lines / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2036 context->fb = render_get_framebuffer(context->cur_buffer, &context->output_pitch);
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
2037 vdp_update_per_frame_debug(context);
1629
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2038 }
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2039
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2040 static void advance_output_line(vdp_context *context)
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2041 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2042 if (headless) {
1168
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
2043 if (context->vcounter == context->inactive_start) {
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
2044 context->frame++;
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
2045 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2046 context->vcounter &= 0x1FF;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2047 } else {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2048 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2049 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2050 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2051
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2052 if (context->output_lines == lines_max) {
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2053 render_framebuffer_updated(context->cur_buffer, context->h40_lines > (context->inactive_start + context->border_top) / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2054 context->cur_buffer = context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN : FRAMEBUFFER_ODD;
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2055 context->fb = render_get_framebuffer(context->cur_buffer, &context->output_pitch);
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
2056 vdp_update_per_frame_debug(context);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2057 context->h40_lines = 0;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2058 context->frame++;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2059 context->output_lines = 0;
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2060 }
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2061 uint32_t output_line = context->vcounter;
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2062 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2063 //vcounter increment occurs much later in Mode 4
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2064 output_line++;
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2065 }
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2066 if (output_line < context->inactive_start + context->border_bot && context->output_lines > 0) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2067 output_line = context->output_lines++;//context->border_top + context->vcounter;
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2068 } else if (output_line >= 0x200 - context->border_top) {
1385
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2069 if (output_line == 0x200 - context->border_top) {
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2070 //We're at the top of the display, force context->output_lines to be zero to avoid
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2071 //potential screen rolling if the mode is changed at an inopportune time
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2072 context->output_lines = 0;
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2073 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2074 output_line = context->output_lines++;//context->vcounter - (0x200 - context->border_top);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2075 } else {
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2076 context->output = NULL;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2077 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2078 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * output_line);
1271
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2079 #ifdef DEBUG_FB_FILL
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2080 for (int i = 0; i < LINEBUF_SIZE; i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2081 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2082 context->output[i] = 0xFFFF00FF;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2083 }
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2084 #endif
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2085 if (context->output && (context->regs[REG_MODE_4] & BIT_H40)) {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2086 context->h40_lines++;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
2087 }
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
2088 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2089 }
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2090
1401
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2091 void vdp_release_framebuffer(vdp_context *context)
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2092 {
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2093 render_framebuffer_updated(context->cur_buffer, context->h40_lines > (context->inactive_start + context->border_top) / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
1401
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2094 context->output = context->fb = NULL;
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2095 }
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2096
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2097 void vdp_reacquire_framebuffer(vdp_context *context)
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2098 {
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2099 context->fb = render_get_framebuffer(context->cur_buffer, &context->output_pitch);
1401
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2100 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL)
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2101 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2102 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28;
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2103 if (context->output_lines <= lines_max && context->output_lines > 0) {
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2104 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * (context->output_lines - 1));
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2105 } else {
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2106 context->output = NULL;
1401
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2107 }
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2108 }
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2109
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2110 static void render_border_garbage(vdp_context *context, uint32_t address, uint8_t *buf, uint8_t buf_off, uint16_t col)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2111 {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2112 uint8_t base = col >> 9 & 0x30;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2113 for (int i = 0; i < 4; i++, address++)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2114 {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2115 uint8_t byte = context->vdpmem[address & 0xFFFF];
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2116 buf[(buf_off++) & SCROLL_BUFFER_MASK] = base | byte >> 4;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2117 buf[(buf_off++) & SCROLL_BUFFER_MASK] = base | byte & 0xF;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2118 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2119 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2120
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2121 static void draw_right_border(vdp_context *context)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2122 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2123 uint8_t *dst = context->compositebuf + BORDER_LEFT + ((context->regs[REG_MODE_4] & BIT_H40) ? 320 : 256);
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2124 uint8_t pixel = context->regs[REG_BG_COLOR] & 0x3F;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2125 if ((context->test_port & TEST_BIT_DISABLE) != 0) {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2126 pixel = 0x3F;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2127 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2128 uint8_t test_layer = context->test_port >> 7 & 3;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2129 if (test_layer) {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2130 switch(test_layer)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2131 {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2132 case 1:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2133 memset(dst, 0, BORDER_RIGHT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2134 dst += BORDER_RIGHT;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2135 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2136 case 2: {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2137 //plane A
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2138 //TODO: Deal with Window layer
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2139 int i;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2140 i = 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2141 uint8_t buf_off = context->buf_a_off - (context->hscroll_a & 0xF);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2142 //uint8_t *src = context->tmp_buf_a + ((context->buf_a_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_a & 0xF))) & SCROLL_BUFFER_MASK);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2143 for (; i < BORDER_RIGHT; buf_off++, i++, dst++)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2144 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2145 *dst = context->tmp_buf_a[buf_off & SCROLL_BUFFER_MASK] & 0x3F;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2146 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2147 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2148 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2149 case 3: {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2150 //plane B
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2151 int i;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2152 i = 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2153 uint8_t buf_off = context->buf_b_off - (context->hscroll_b & 0xF);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2154 //uint8_t *src = context->tmp_buf_b + ((context->buf_b_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_b & 0xF))) & SCROLL_BUFFER_MASK);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2155 for (; i < BORDER_RIGHT; buf_off++, i++, dst++)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2156 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2157 *dst = context->tmp_buf_b[buf_off & SCROLL_BUFFER_MASK] & 0x3F;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2158 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2159 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2160 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2161 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2162 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2163 memset(dst, 0, BORDER_RIGHT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2164 dst += BORDER_RIGHT;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2165 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2166 context->done_composite = dst;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2167 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2168 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2169 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2170
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2171 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; }
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
2172 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2173 #define OUTPUT_PIXEL(slot) if ((slot) >= BG_START_SLOT) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2174 uint8_t *src = context->compositebuf + ((slot) - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2175 uint32_t *dst = context->output + ((slot) - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2176 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2177 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2178 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2179 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2180 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2181 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2182 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2183 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2184 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2185 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2186 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2187
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2188 #define OUTPUT_PIXEL_H40(slot) if (slot <= (BG_START_SLOT + LINEBUF_SIZE/2)) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2189 uint8_t *src = context->compositebuf + (slot - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2190 uint32_t *dst = context->output + (slot - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2191 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2192 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2193 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2194 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2195 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2196 if (slot != (BG_START_SLOT + LINEBUF_SIZE/2)) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2197 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2198 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2199 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2200 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2201 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2202 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2203 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2204
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2205 #define OUTPUT_PIXEL_H32(slot) if (slot <= (BG_START_SLOT + (256+HORIZ_BORDER)/2)) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2206 uint8_t *src = context->compositebuf + (slot - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2207 uint32_t *dst = context->output + (slot - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2208 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2209 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2210 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2211 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2212 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2213 if (slot != (BG_START_SLOT + (256+HORIZ_BORDER)/2)) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2214 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2215 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2216 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2217 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2218 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2219 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2220 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2221
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2222 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2223 case startcyc:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2224 OUTPUT_PIXEL(startcyc)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2225 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2226 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2227 case ((startcyc+1)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2228 OUTPUT_PIXEL((startcyc+1)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2229 external_slot(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2230 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2231 case ((startcyc+2)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2232 OUTPUT_PIXEL((startcyc+2)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2233 render_map_1(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2234 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2235 case ((startcyc+3)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2236 OUTPUT_PIXEL((startcyc+3)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2237 render_map_2(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2238 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2239 case ((startcyc+4)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2240 OUTPUT_PIXEL((startcyc+4)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2241 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2242 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2243 case ((startcyc+5)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2244 OUTPUT_PIXEL((startcyc+5)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2245 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2246 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2247 case ((startcyc+6)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2248 OUTPUT_PIXEL((startcyc+6)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2249 render_map_3(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2250 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2251 case ((startcyc+7)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2252 OUTPUT_PIXEL((startcyc+7)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2253 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2254 CHECK_LIMIT
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2255
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2256 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2257 case startcyc:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2258 OUTPUT_PIXEL(startcyc)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2259 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2260 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2261 case (startcyc+1):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2262 /* refresh, so don't run dma src */\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2263 OUTPUT_PIXEL((startcyc+1)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2264 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2265 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2266 CHECK_ONLY\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2267 case (startcyc+2):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2268 OUTPUT_PIXEL((startcyc+2)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2269 render_map_1(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2270 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2271 case (startcyc+3):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2272 OUTPUT_PIXEL((startcyc+3)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2273 render_map_2(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2274 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2275 case (startcyc+4):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2276 OUTPUT_PIXEL((startcyc+4)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2277 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2278 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2279 case (startcyc+5):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2280 OUTPUT_PIXEL((startcyc+5)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2281 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2282 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2283 case (startcyc+6):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2284 OUTPUT_PIXEL((startcyc+6)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2285 render_map_3(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2286 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2287 case (startcyc+7):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2288 OUTPUT_PIXEL((startcyc+7)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2289 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2290 CHECK_LIMIT
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2291
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2292 #define COLUMN_RENDER_BLOCK_MODE4(column, startcyc) \
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2293 case startcyc:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2294 OUTPUT_PIXEL(startcyc)\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2295 read_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2296 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2297 case ((startcyc+1)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2298 OUTPUT_PIXEL((startcyc+1)&0xFF)\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2299 if (column & 3) {\
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2300 scan_sprite_table_mode4(context);\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2301 } else {\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2302 external_slot(context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2303 }\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2304 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2305 case ((startcyc+2)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2306 OUTPUT_PIXEL((startcyc+2)&0xFF)\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2307 fetch_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2308 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2309 case ((startcyc+3)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2310 OUTPUT_PIXEL((startcyc+3)&0xFF)\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2311 render_map_mode4(context->vcounter, column, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2312 CHECK_LIMIT
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2313
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2314 #define CHECK_LIMIT_HSYNC(slot) \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2315 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2316 if (slot >= HSYNC_SLOT_H40 && slot < HSYNC_END_H40) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2317 context->cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2318 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2319 context->cycles += slot_cycles;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2320 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2321 if (slot == 182) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2322 context->hslot = 229;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2323 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2324 context->hslot++;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2325 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2326 CHECK_ONLY
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
2327
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2328 #define SPRITE_RENDER_H40(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2329 case slot:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2330 OUTPUT_PIXEL_H40(slot)\
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2331 if ((slot) == BG_START_SLOT + LINEBUF_SIZE/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2332 advance_output_line(context);\
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2333 if (!context->output) {\
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2334 context->output = dummy_buffer;\
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2335 }\
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2336 }\
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2337 if (slot == 168 || slot == 247 || slot == 248) {\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2338 render_border_garbage(\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2339 context,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2340 context->sprite_draw_list[context->cur_slot].address,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2341 context->tmp_buf_b,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2342 context->buf_b_off + (slot == 247 ? 0 : 8),\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2343 slot == 247 ? context->col_1 : context->col_2\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2344 );\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2345 if (slot == 248) {\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2346 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2347 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2348 }\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2349 } else if (slot == 243) {\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2350 render_border_garbage(\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2351 context,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2352 context->sprite_draw_list[context->cur_slot].address,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2353 context->tmp_buf_a,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2354 context->buf_a_off,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2355 context->col_1\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2356 );\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2357 } else if (slot == 169) {\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2358 draw_right_border(context);\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2359 }\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2360 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2361 scan_sprite_table(context->vcounter, context);\
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2362 CHECK_LIMIT_HSYNC(slot)
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
2363
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2364 //Note that the line advancement check will fail if BG_START_SLOT is > 6
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2365 //as we're bumping up against the hcounter jump
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2366 #define SPRITE_RENDER_H32(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2367 case slot:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2368 OUTPUT_PIXEL_H32(slot)\
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2369 if ((slot) == BG_START_SLOT + (256+HORIZ_BORDER)/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2370 advance_output_line(context);\
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2371 if (!context->output) {\
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2372 context->output = dummy_buffer;\
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2373 }\
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2374 }\
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2375 if (slot == 136 || slot == 247 || slot == 248) {\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2376 render_border_garbage(\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2377 context,\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2378 context->sprite_draw_list[context->cur_slot].address,\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2379 context->tmp_buf_b,\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2380 context->buf_b_off + (slot == 247 ? 0 : 8),\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2381 slot == 247 ? context->col_1 : context->col_2\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2382 );\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2383 if (slot == 248) {\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2384 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2385 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2386 }\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2387 } else if (slot == 137) {\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2388 draw_right_border(context);\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2389 }\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2390 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2391 scan_sprite_table(context->vcounter, context);\
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
2392 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2393 if (slot == 147) {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2394 context->hslot = 233;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2395 } else {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2396 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2397 }\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2398 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2399 CHECK_ONLY
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2400
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2401 #define MODE4_CHECK_SLOT_LINE(slot) \
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2402 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2403 if ((slot) == BG_START_SLOT + (256+HORIZ_BORDER)/2) {\
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2404 advance_output_line(context);\
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2405 if (!context->output) {\
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2406 context->output = dummy_buffer;\
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2407 }\
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2408 }\
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2409 if ((slot) == 147) {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2410 context->hslot = 233;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2411 } else {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2412 context->hslot++;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2413 }\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2414 context->cycles += slot_cycles;\
1163
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2415 if ((slot+1) == LINE_CHANGE_MODE4) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2416 vdp_advance_line(context);\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2417 if (context->vcounter == 192) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2418 return;\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2419 }\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2420 }\
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2421 CHECK_ONLY
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2422
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2423 #define CALC_SLOT(slot, increment) ((slot+increment) > 147 && (slot+increment) < 233 ? (slot+increment-148+233): (slot+increment))
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2424
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2425 #define SPRITE_RENDER_H32_MODE4(slot) \
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2426 case slot:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2427 OUTPUT_PIXEL_H32(slot)\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2428 read_sprite_x_mode4(context);\
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2429 MODE4_CHECK_SLOT_LINE(slot)\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2430 case CALC_SLOT(slot, 1):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2431 OUTPUT_PIXEL(CALC_SLOT(slot, 1))\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2432 read_sprite_x_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2433 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot,1))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2434 case CALC_SLOT(slot, 2):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2435 OUTPUT_PIXEL(CALC_SLOT(slot, 2))\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2436 fetch_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2437 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 2))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2438 case CALC_SLOT(slot, 3):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2439 OUTPUT_PIXEL(CALC_SLOT(slot, 3))\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2440 render_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2441 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 3))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2442 case CALC_SLOT(slot, 4):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2443 OUTPUT_PIXEL(CALC_SLOT(slot, 4))\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2444 fetch_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2445 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 4))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2446 case CALC_SLOT(slot, 5):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2447 OUTPUT_PIXEL(CALC_SLOT(slot, 5))\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2448 render_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2449 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 5))
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2450
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2451 static uint32_t dummy_buffer[LINEBUF_SIZE];
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
2452 static void vdp_h40(vdp_context * context, uint32_t target_cycles)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2453 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2454 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2455 uint32_t mask;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2456 uint32_t const slot_cycles = MCLKS_SLOT_H40;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2457 uint8_t bgindex = context->regs[REG_BG_COLOR] & 0x3F;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2458 uint8_t test_layer = context->test_port >> 7 & 3;
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2459 if (!context->output) {
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2460 //This shouldn't happen normally, but it can theoretically
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2461 //happen when doing border busting
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2462 context->output = dummy_buffer;
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2463 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2464 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2465 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2466 for (;;)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2467 {
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2468 case 165:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2469 OUTPUT_PIXEL(165)
1432
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2470 if (!(context->regs[REG_MODE_3] & BIT_VSCROLL)) {
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2471 //TODO: Develop some tests on hardware to see when vscroll latch actually happens for full plane mode
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2472 //See note in vdp_h32 for why this was originally moved out of read_map_scroll
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2473 //Skitchin' has a similar problem, but uses H40 mode. It seems to be able to hit the extern slot at 232
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2474 //pretty consistently
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2475 context->vscroll_latch[0] = context->vsram[0];
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2476 context->vscroll_latch[1] = context->vsram[1];
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2477 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2478 if (context->state == PREPARING) {
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2479 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2480 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2481 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2482 }
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2483 CHECK_LIMIT
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2484 case 166:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2485 OUTPUT_PIXEL(166)
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2486 if (context->state == PREPARING) {
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2487 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2488 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2489 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2490 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2491 if (context->vcounter == context->inactive_start) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2492 context->hslot++;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2493 context->cycles += slot_cycles;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2494 return;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2495 }
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2496 CHECK_LIMIT
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2497 //sprite attribute table scan starts
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2498 case 167:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2499 OUTPUT_PIXEL(167)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2500 context->sprite_index = 0x80;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2501 context->slot_counter = 0;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2502 render_border_garbage(
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2503 context,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2504 context->sprite_draw_list[context->cur_slot].address,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2505 context->tmp_buf_b, context->buf_b_off,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2506 context->col_1
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2507 );
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2508 render_sprite_cells(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2509 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2510 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2511 SPRITE_RENDER_H40(168)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2512 SPRITE_RENDER_H40(169)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2513 SPRITE_RENDER_H40(170)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2514 SPRITE_RENDER_H40(171)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2515 SPRITE_RENDER_H40(172)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2516 SPRITE_RENDER_H40(173)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2517 SPRITE_RENDER_H40(174)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2518 SPRITE_RENDER_H40(175)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2519 SPRITE_RENDER_H40(176)
1365
6dd2c3edd0b5 Add a bit of a hack to HINT start cycle to give correct values in my test ROM and further improve prevelance of CRAM dot noise in Outrunners and OD2
Michael Pavone <pavone@retrodev.com>
parents: 1362
diff changeset
2520 SPRITE_RENDER_H40(177)//End of border?
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2521 SPRITE_RENDER_H40(178)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2522 SPRITE_RENDER_H40(179)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2523 SPRITE_RENDER_H40(180)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2524 SPRITE_RENDER_H40(181)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2525 SPRITE_RENDER_H40(182)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2526 SPRITE_RENDER_H40(229)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2527 //!HSYNC asserted
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2528 SPRITE_RENDER_H40(230)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2529 SPRITE_RENDER_H40(231)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2530 case 232:
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2531 external_slot(context);
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2532 CHECK_LIMIT_HSYNC(232)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2533 SPRITE_RENDER_H40(233)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2534 SPRITE_RENDER_H40(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2535 SPRITE_RENDER_H40(235)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2536 SPRITE_RENDER_H40(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2537 SPRITE_RENDER_H40(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2538 SPRITE_RENDER_H40(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2539 SPRITE_RENDER_H40(239)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2540 SPRITE_RENDER_H40(240)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2541 SPRITE_RENDER_H40(241)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2542 SPRITE_RENDER_H40(242)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2543 SPRITE_RENDER_H40(243) //provides "garbage" for border when plane A selected
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2544 case 244:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2545 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2546 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2547 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2548 mask |= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2549 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2550 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2551 mask |= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2552 }
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2553 render_border_garbage(context, address, context->tmp_buf_a, context->buf_a_off+8, context->col_2);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2554 address += (context->vcounter & mask) * 4;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2555 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2556 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2557 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
2558 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2559 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2560 context->cycles += h40_hsync_cycles[14];
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2561 CHECK_ONLY //provides "garbage" for border when plane A selected
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2562 //!HSYNC high
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2563 SPRITE_RENDER_H40(245)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2564 SPRITE_RENDER_H40(246)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2565 SPRITE_RENDER_H40(247) //provides "garbage" for border when plane B selected
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2566 SPRITE_RENDER_H40(248) //provides "garbage" for border when plane B selected
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2567 case 249:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2568 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2569 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2570 SPRITE_RENDER_H40(250)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2571 case 251:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2572 render_map_1(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2573 scan_sprite_table(context->vcounter, context);//Just a guess
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2574 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2575 case 252:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2576 render_map_2(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2577 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2578 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2579 case 253:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2580 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2581 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2582 SPRITE_RENDER_H40(254)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2583 case 255:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2584 render_map_3(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2585 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2586 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2587 case 0:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2588 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2589 scan_sprite_table(context->vcounter, context);//Just a guess
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2590 //seems like the sprite table scan fills a shift register
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2591 //values are FIFO, but unused slots precede used slots
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2592 //so we set cur_slot to slot_counter and let it wrap around to
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2593 //the beginning of the list
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2594 context->cur_slot = context->slot_counter;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2595 context->sprite_draws = MAX_DRAWS;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
2596 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2597 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2598 COLUMN_RENDER_BLOCK(2, 1)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2599 COLUMN_RENDER_BLOCK(4, 9)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2600 COLUMN_RENDER_BLOCK(6, 17)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2601 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2602 COLUMN_RENDER_BLOCK(10, 33)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2603 COLUMN_RENDER_BLOCK(12, 41)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2604 COLUMN_RENDER_BLOCK(14, 49)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2605 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2606 COLUMN_RENDER_BLOCK(18, 65)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2607 COLUMN_RENDER_BLOCK(20, 73)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2608 COLUMN_RENDER_BLOCK(22, 81)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2609 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2610 COLUMN_RENDER_BLOCK(26, 97)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2611 COLUMN_RENDER_BLOCK(28, 105)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2612 COLUMN_RENDER_BLOCK(30, 113)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2613 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2614 COLUMN_RENDER_BLOCK(34, 129)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2615 COLUMN_RENDER_BLOCK(36, 137)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2616 COLUMN_RENDER_BLOCK(38, 145)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2617 COLUMN_RENDER_BLOCK_REFRESH(40, 153)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2618 case 161:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2619 OUTPUT_PIXEL(161)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2620 external_slot(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2621 CHECK_LIMIT
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2622 case 162:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2623 OUTPUT_PIXEL(162)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2624 external_slot(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2625 CHECK_LIMIT
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2626 //sprite render to line buffer starts
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2627 case 163:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2628 OUTPUT_PIXEL(163)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2629 context->cur_slot = MAX_DRAWS-1;
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2630 memset(context->linebuf, 0, LINEBUF_SIZE);
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2631 render_border_garbage(
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2632 context,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2633 context->sprite_draw_list[context->cur_slot].address,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2634 context->tmp_buf_a, context->buf_a_off,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2635 context->col_1
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2636 );
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2637 render_sprite_cells(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2638 CHECK_LIMIT
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2639 case 164:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2640 OUTPUT_PIXEL(164)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2641 render_border_garbage(
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2642 context,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2643 context->sprite_draw_list[context->cur_slot].address,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2644 context->tmp_buf_a, context->buf_a_off + 8,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2645 context->col_2
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2646 );
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2647 render_sprite_cells(context);
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2648 if (context->flags & FLAG_DMA_RUN) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2649 run_dma_src(context, -1);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2650 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2651 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2652 context->cycles += slot_cycles;
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2653 vdp_advance_line(context);
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2654 CHECK_ONLY
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2655 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2656 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2657 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2658 context->cycles += slot_cycles;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2659 return;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2660 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2661 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2662
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
2663 static void vdp_h32(vdp_context * context, uint32_t target_cycles)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2664 {
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2665 uint16_t address;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2666 uint32_t mask;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2667 uint32_t const slot_cycles = MCLKS_SLOT_H32;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2668 uint8_t bgindex = context->regs[REG_BG_COLOR] & 0x3F;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2669 uint8_t test_layer = context->test_port >> 7 & 3;
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2670 if (!context->output) {
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2671 //This shouldn't happen normally, but it can theoretically
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2672 //happen when doing border busting
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2673 context->output = dummy_buffer;
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2674 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2675 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2676 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2677 for (;;)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2678 {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2679 case 133:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2680 OUTPUT_PIXEL(133)
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2681 if (context->state == PREPARING) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2682 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2683 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2684 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2685 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2686 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2687 case 134:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2688 OUTPUT_PIXEL(134)
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2689 if (context->state == PREPARING) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2690 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2691 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2692 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2693 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2694 if (context->vcounter == context->inactive_start) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2695 context->hslot++;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2696 context->cycles += slot_cycles;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2697 return;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2698 }
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2699 CHECK_LIMIT
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2700 //sprite attribute table scan starts
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2701 case 135:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2702 OUTPUT_PIXEL(135)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2703 context->sprite_index = 0x80;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2704 context->slot_counter = 0;
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2705 render_border_garbage(
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2706 context,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2707 context->sprite_draw_list[context->cur_slot].address,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2708 context->tmp_buf_b, context->buf_b_off,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2709 context->col_1
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2710 );
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2711 render_sprite_cells(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2712 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2713 CHECK_LIMIT
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2714 SPRITE_RENDER_H32(136)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2715 SPRITE_RENDER_H32(137)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2716 SPRITE_RENDER_H32(138)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2717 SPRITE_RENDER_H32(139)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2718 SPRITE_RENDER_H32(140)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2719 SPRITE_RENDER_H32(141)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2720 SPRITE_RENDER_H32(142)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2721 SPRITE_RENDER_H32(143)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2722 SPRITE_RENDER_H32(144)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2723 case 145:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2724 OUTPUT_PIXEL(145)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2725 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2726 CHECK_LIMIT
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2727 SPRITE_RENDER_H32(146)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2728 SPRITE_RENDER_H32(147)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2729 SPRITE_RENDER_H32(233)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2730 SPRITE_RENDER_H32(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2731 SPRITE_RENDER_H32(235)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2732 //HSYNC start
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2733 SPRITE_RENDER_H32(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2734 SPRITE_RENDER_H32(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2735 SPRITE_RENDER_H32(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2736 SPRITE_RENDER_H32(239)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2737 SPRITE_RENDER_H32(240)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2738 SPRITE_RENDER_H32(241)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2739 SPRITE_RENDER_H32(242)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2740 case 243:
1422
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2741 if (!(context->regs[REG_MODE_3] & BIT_VSCROLL)) {
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2742 //TODO: Develop some tests on hardware to see when vscroll latch actually happens for full plane mode
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2743 //Top Gear 2 has a very efficient HINT routine that can occassionally hit this slot with a VSRAM write
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2744 //Since CRAM-updatnig HINT routines seem to indicate that my HINT latency is perhaps slightly too high
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2745 //the most reasonable explanation is that vscroll is latched before this slot, but tests are needed
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2746 //to confirm that one way or another
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2747 context->vscroll_latch[0] = context->vsram[0];
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2748 context->vscroll_latch[1] = context->vsram[1];
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2749 }
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2750 external_slot(context);
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2751 //provides "garbage" for border when plane A selected
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2752 render_border_garbage(
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2753 context,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2754 context->sprite_draw_list[context->cur_slot].address,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2755 context->tmp_buf_a,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2756 context->buf_a_off,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2757 context->col_1
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2758 );
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2759 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2760 case 244:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2761 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2762 mask = 0;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2763 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2764 mask |= 0xF8;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2765 }
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2766 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2767 mask |= 0x7;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2768 }
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2769 render_border_garbage(context, address, context->tmp_buf_a, context->buf_a_off+8, context->col_2);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2770 address += (context->vcounter & mask) * 4;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2771 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2772 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2773 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2774 CHECK_LIMIT //provides "garbage" for border when plane A selected
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2775 SPRITE_RENDER_H32(245)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2776 SPRITE_RENDER_H32(246)
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2777 SPRITE_RENDER_H32(247) //provides "garbage" for border when plane B selected
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2778 SPRITE_RENDER_H32(248) //provides "garbage" for border when plane B selected
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2779 //!HSYNC high
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2780 case 249:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2781 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2782 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2783 SPRITE_RENDER_H32(250)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2784 case 251:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2785 render_map_1(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2786 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2787 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2788 case 252:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2789 render_map_2(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2790 scan_sprite_table(context->vcounter, context);//Just a guess
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2791 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2792 case 253:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2793 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2794 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2795 case 254:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2796 render_sprite_cells(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2797 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2798 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2799 case 255:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2800 render_map_3(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2801 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2802 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2803 case 0:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2804 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2805 scan_sprite_table(context->vcounter, context);//Just a guess
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2806 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2807 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2808 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2809 context->cur_slot = context->slot_counter;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2810 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2811 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2812 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2813 COLUMN_RENDER_BLOCK(2, 1)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2814 COLUMN_RENDER_BLOCK(4, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2815 COLUMN_RENDER_BLOCK(6, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2816 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2817 COLUMN_RENDER_BLOCK(10, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2818 COLUMN_RENDER_BLOCK(12, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2819 COLUMN_RENDER_BLOCK(14, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2820 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2821 COLUMN_RENDER_BLOCK(18, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2822 COLUMN_RENDER_BLOCK(20, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2823 COLUMN_RENDER_BLOCK(22, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2824 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2825 COLUMN_RENDER_BLOCK(26, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2826 COLUMN_RENDER_BLOCK(28, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2827 COLUMN_RENDER_BLOCK(30, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2828 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2829 case 129:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2830 OUTPUT_PIXEL(129)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2831 external_slot(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2832 CHECK_LIMIT
1269
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2833 case 130: {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2834 OUTPUT_PIXEL(130)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2835 external_slot(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2836 CHECK_LIMIT
1269
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2837 }
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2838 //sprite render to line buffer starts
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2839 case 131:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2840 OUTPUT_PIXEL(131)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2841 context->cur_slot = MAX_DRAWS_H32-1;
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2842 memset(context->linebuf, 0, LINEBUF_SIZE);
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2843 render_border_garbage(
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2844 context,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2845 context->sprite_draw_list[context->cur_slot].address,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2846 context->tmp_buf_a, context->buf_a_off,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2847 context->col_1
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2848 );
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2849 render_sprite_cells(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2850 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2851 case 132:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2852 OUTPUT_PIXEL(132)
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2853 render_border_garbage(
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2854 context,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2855 context->sprite_draw_list[context->cur_slot].address,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2856 context->tmp_buf_a, context->buf_a_off + 8,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2857 context->col_2
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2858 );
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2859 render_sprite_cells(context);
1173
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2860 if (context->flags & FLAG_DMA_RUN) {
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2861 run_dma_src(context, -1);
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2862 }
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2863 context->hslot++;
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2864 context->cycles += slot_cycles;
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2865 vdp_advance_line(context);
1173
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2866 CHECK_ONLY
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2867 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2868 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2869 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2870 context->cycles += MCLKS_SLOT_H32;
503
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2871 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2872 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2873
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2874 static void vdp_h32_mode4(vdp_context * context, uint32_t target_cycles)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2875 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2876 uint16_t address;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2877 uint32_t mask;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2878 uint32_t const slot_cycles = MCLKS_SLOT_H32;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2879 uint8_t bgindex = 0x10 | (context->regs[REG_BG_COLOR] & 0xF) + MODE4_OFFSET;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2880 uint8_t test_layer = context->test_port >> 7 & 3;
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2881 if (!context->output) {
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2882 //This shouldn't happen normally, but it can theoretically
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2883 //happen when doing border busting
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2884 context->output = dummy_buffer;
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
2885 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2886 switch(context->hslot)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2887 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2888 for (;;)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2889 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2890 //sprite rendering starts
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2891 SPRITE_RENDER_H32_MODE4(137)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2892 SPRITE_RENDER_H32_MODE4(143)
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2893 case 234:
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2894 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2895 CHECK_LIMIT
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2896 case 235:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2897 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2898 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2899 //!HSYNC low
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2900 case 236:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2901 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2902 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2903 case 237:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2904 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2905 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2906 case 238:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2907 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2908 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2909 SPRITE_RENDER_H32_MODE4(239)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2910 SPRITE_RENDER_H32_MODE4(245)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2911 case 251:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2912 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2913 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2914 case 252:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2915 external_slot(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2916 if (context->regs[REG_MODE_1] & BIT_HSCRL_LOCK && context->vcounter < 16) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2917 context->hscroll_a = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2918 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2919 context->hscroll_a = context->regs[REG_X_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2920 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2921 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2922 case 253:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2923 context->sprite_index = 0;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2924 context->slot_counter = MAX_DRAWS_H32_MODE4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2925 scan_sprite_table_mode4(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2926 CHECK_LIMIT
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2927 case 254:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2928 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2929 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2930 case 255:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2931 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2932 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2933 case 0: {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2934 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2935 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2936 }
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2937 case 1:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2938 scan_sprite_table_mode4(context);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2939 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2940 case 2:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2941 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2942 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2943 case 3:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2944 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2945 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2946 case 4: {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2947 scan_sprite_table_mode4(context);
1121
1913f9c28003 Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents: 1120
diff changeset
2948 context->buf_a_off = 8;
1913f9c28003 Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents: 1120
diff changeset
2949 memset(context->tmp_buf_a, 0, 8);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2950 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2951 }
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2952 COLUMN_RENDER_BLOCK_MODE4(0, 5)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2953 COLUMN_RENDER_BLOCK_MODE4(1, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2954 COLUMN_RENDER_BLOCK_MODE4(2, 13)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2955 COLUMN_RENDER_BLOCK_MODE4(3, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2956 COLUMN_RENDER_BLOCK_MODE4(4, 21)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2957 COLUMN_RENDER_BLOCK_MODE4(5, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2958 COLUMN_RENDER_BLOCK_MODE4(6, 29)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2959 COLUMN_RENDER_BLOCK_MODE4(7, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2960 COLUMN_RENDER_BLOCK_MODE4(8, 37)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2961 COLUMN_RENDER_BLOCK_MODE4(9, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2962 COLUMN_RENDER_BLOCK_MODE4(10, 45)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2963 COLUMN_RENDER_BLOCK_MODE4(11, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2964 COLUMN_RENDER_BLOCK_MODE4(12, 53)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2965 COLUMN_RENDER_BLOCK_MODE4(13, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2966 COLUMN_RENDER_BLOCK_MODE4(14, 61)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2967 COLUMN_RENDER_BLOCK_MODE4(15, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2968 COLUMN_RENDER_BLOCK_MODE4(16, 69)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2969 COLUMN_RENDER_BLOCK_MODE4(17, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2970 COLUMN_RENDER_BLOCK_MODE4(18, 77)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2971 COLUMN_RENDER_BLOCK_MODE4(19, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2972 COLUMN_RENDER_BLOCK_MODE4(20, 85)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2973 COLUMN_RENDER_BLOCK_MODE4(21, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2974 COLUMN_RENDER_BLOCK_MODE4(22, 93)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2975 COLUMN_RENDER_BLOCK_MODE4(23, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2976 COLUMN_RENDER_BLOCK_MODE4(24, 101)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2977 COLUMN_RENDER_BLOCK_MODE4(25, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2978 COLUMN_RENDER_BLOCK_MODE4(26, 109)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2979 COLUMN_RENDER_BLOCK_MODE4(27, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2980 COLUMN_RENDER_BLOCK_MODE4(28, 117)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2981 COLUMN_RENDER_BLOCK_MODE4(29, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2982 COLUMN_RENDER_BLOCK_MODE4(30, 125)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2983 COLUMN_RENDER_BLOCK_MODE4(31, 129)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2984 case 133:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2985 OUTPUT_PIXEL(133)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2986 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2987 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2988 case 134:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2989 OUTPUT_PIXEL(134)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2990 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2991 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2992 case 135:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2993 OUTPUT_PIXEL(135)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2994 external_slot(context);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2995 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2996 case 136: {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2997 OUTPUT_PIXEL(136)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2998 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2999 //set things up for sprite rendering in the next slot
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3000 memset(context->linebuf, 0, LINEBUF_SIZE);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3001 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3002 context->sprite_draws = MAX_DRAWS_H32_MODE4;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3003 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
3004 }}
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3005 default:
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3006 context->hslot++;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3007 context->cycles += MCLKS_SLOT_H32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3008 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3009 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3010
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3011 static void inactive_test_output(vdp_context *context, uint8_t is_h40, uint8_t test_layer)
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3012 {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3013 uint8_t max_slot = is_h40 ? 169 : 136;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3014 if (context->hslot > max_slot) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3015 return;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3016 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3017 uint8_t *dst = context->compositebuf + (context->hslot >> 3) * SCROLL_BUFFER_DRAW;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3018 int32_t len;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3019 uint32_t src_off;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3020 if (context->hslot) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3021 dst -= SCROLL_BUFFER_DRAW - BORDER_LEFT;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3022 src_off = 0;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3023 len = context->hslot == max_slot ? BORDER_RIGHT : SCROLL_BUFFER_DRAW;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3024 } else {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3025 src_off = SCROLL_BUFFER_DRAW - BORDER_LEFT;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3026 len = BORDER_LEFT;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3027 }
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
3028 uint8_t *src = NULL;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3029 if (test_layer == 2) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3030 //plane A
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3031 src_off += context->buf_a_off + context->hscroll_a;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3032 src = context->tmp_buf_a;
1369
3e7a921718de Fix handling of test register selected sprite layer in border area. Gets rid of the border garbage in the "disco floor/ceiling" scene of OD2
Michael Pavone <pavone@retrodev.com>
parents: 1368
diff changeset
3033 } else if (test_layer == 3){
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3034 //plane B
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3035 src_off += context->buf_b_off + context->hscroll_b;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3036 src = context->tmp_buf_b;
1369
3e7a921718de Fix handling of test register selected sprite layer in border area. Gets rid of the border garbage in the "disco floor/ceiling" scene of OD2
Michael Pavone <pavone@retrodev.com>
parents: 1368
diff changeset
3037 } else {
3e7a921718de Fix handling of test register selected sprite layer in border area. Gets rid of the border garbage in the "disco floor/ceiling" scene of OD2
Michael Pavone <pavone@retrodev.com>
parents: 1368
diff changeset
3038 //sprite layer
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3039 memset(dst, 0, len);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3040 dst += len;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3041 len = 0;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3042 }
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
3043 if (src) {
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
3044 for (; len >=0; len--, dst++, src_off++)
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
3045 {
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
3046 *dst = src[src_off & SCROLL_BUFFER_MASK] & 0x3F;
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
3047 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3048 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3049 context->done_composite = dst;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3050 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_DRAW;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3051 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_DRAW;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3052 }
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3053
1362
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3054 static void check_switch_inactive(vdp_context *context, uint8_t is_h40)
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3055 {
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3056 //technically the second hcounter check should be different for H40, but this is probably close enough for now
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3057 if (context->state == ACTIVE && context->vcounter == context->inactive_start && (context->hslot >= (is_h40 ? 167 : 135) || context->hslot < 133)) {
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3058 context->state = INACTIVE;
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3059 }
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3060 }
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3061
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3062 static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3063 {
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3064 uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest, latch_slot;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3065 uint8_t index_reset_value, max_draws, max_sprites;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3066 uint16_t vint_line, active_line;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3067 uint32_t bg_color;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3068
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3069 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3070 if (is_h40) {
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3071 latch_slot = 165;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
3072 buf_clear_slot = 163;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
3073 index_reset_slot = 167;
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3074 bg_end_slot = BG_START_SLOT + LINEBUF_SIZE/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3075 max_draws = MAX_DRAWS-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3076 max_sprites = MAX_SPRITES_LINE;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3077 index_reset_value = 0x80;
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3078 vint_slot = VINT_SLOT_H40;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3079 line_change = LINE_CHANGE_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3080 jump_start = 182;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3081 jump_dest = 229;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3082 } else {
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3083 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3084 max_draws = MAX_DRAWS_H32-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3085 max_sprites = MAX_SPRITES_LINE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3086 buf_clear_slot = 128;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3087 index_reset_slot = 132;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3088 index_reset_value = 0x80;
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3089 vint_slot = VINT_SLOT_H32;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3090 line_change = LINE_CHANGE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3091 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3092 jump_dest = 233;
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3093 latch_slot = 243;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3094 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3095 vint_line = context->inactive_start;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3096 active_line = 0x1FF;
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3097 if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3098 latch_slot = 220;
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3099 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3100 } else {
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3101 latch_slot = 220;
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3102 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3103 max_draws = MAX_DRAWS_H32_MODE4;
1278
34d3cb05014d Fix VDP buffer overrun that was causing sprite flickering in some games
Michael Pavone <pavone@retrodev.com>
parents: 1273
diff changeset
3104 max_sprites = 8;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3105 buf_clear_slot = 136;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3106 index_reset_slot = 253;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3107 index_reset_value = 0;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3108 vint_line = context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3109 vint_slot = VINT_SLOT_MODE4;
1177
67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency
Michael Pavone <pavone@retrodev.com>
parents: 1175
diff changeset
3110 line_change = LINE_CHANGE_MODE4;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3111 bg_color = render_map_color(0, 0, 0);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3112 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3113 jump_dest = 233;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3114 if (context->regs[REG_MODE_1] & BIT_MODE_4) {
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
3115 active_line = 0x1FF;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3116 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3117 //never active unless either mode 4 or mode 5 is turned on
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3118 active_line = 0x200;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3119 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3120 }
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3121 uint32_t *dst;
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3122 uint8_t *debug_dst;
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
3123 if (context->output && context->hslot >= BG_START_SLOT && context->hslot < bg_end_slot) {
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3124 dst = context->output + 2 * (context->hslot - BG_START_SLOT);
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3125 debug_dst = context->layer_debug_buf + 2 * (context->hslot - BG_START_SLOT);
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3126 } else {
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3127 dst = NULL;
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3128 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3129
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3130 uint8_t test_layer = context->test_port >> 7 & 3;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3131
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3132 while(context->cycles < target_cycles)
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3133 {
1362
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3134 check_switch_inactive(context, is_h40);
1834
304d47a5c67f Get rid of writes to INVALID_LINE in the framebuffer and fix a crash in OD2 from the recent accuracy work
Michael Pavone <pavone@retrodev.com>
parents: 1821
diff changeset
3135 if (context->hslot == BG_START_SLOT && context->output) {
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3136 dst = context->output + (context->hslot - BG_START_SLOT) * 2;
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3137 debug_dst = context->layer_debug_buf + 2 * (context->hslot - BG_START_SLOT);
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3138 } else if (context->hslot == bg_end_slot) {
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
3139 advance_output_line(context);
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3140 dst = NULL;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3141 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3142 //this will need some tweaking to properly interact with 128K mode,
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3143 //but this should be good enough for now
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3144 context->serial_address += 1024;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3145 if (test_layer) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3146 switch (context->hslot & 7)
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3147 {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3148 case 3:
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3149 render_border_garbage(context, context->serial_address, context->tmp_buf_a, context->buf_a_off, context->col_1);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3150 break;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3151 case 4:
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3152 render_border_garbage(context, context->serial_address, context->tmp_buf_a, context->buf_a_off+8, context->col_2);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3153 break;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3154 case 7:
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3155 render_border_garbage(context, context->serial_address, context->tmp_buf_b, context->buf_b_off, context->col_1);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3156 break;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3157 case 0:
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3158 render_border_garbage(context, context->serial_address, context->tmp_buf_b, context->buf_b_off+8, context->col_2);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3159 inactive_test_output(context, is_h40, test_layer);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3160 break;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3161 }
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3162 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3163
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3164 if (context->hslot == buf_clear_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3165 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3166 context->cur_slot = max_draws;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3167 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3168 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3169 context->sprite_draws = MAX_DRAWS_H32_MODE4;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3170 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3171 memset(context->linebuf, 0, LINEBUF_SIZE);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3172 } else if (context->hslot == index_reset_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3173 context->sprite_index = index_reset_value;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
3174 context->slot_counter = mode_5 ? 0 : max_sprites;
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3175 } else if (context->hslot == latch_slot) {
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3176 //it seems unlikely to me that vscroll actually gets latched when the display is off
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3177 //but it's the only straightforward way to reconcile what I'm seeing between Skitchin
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3178 //(which seems to expect vscroll to be latched early) and the intro of Gunstar Heroes
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3179 //(which disables the display and ends up with garbage if vscroll is latched during that period)
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3180 //without it. Some more tests are definitely needed
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3181 context->vscroll_latch[0] = context->vsram[0];
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3182 context->vscroll_latch[1] = context->vsram[1];
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3183 } else if (context->vcounter == vint_line && context->hslot == vint_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3184 context->flags2 |= FLAG2_VINT_PENDING;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3185 context->pending_vint_start = context->cycles;
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
3186 } else if (context->vcounter == context->inactive_start && context->hslot == 1 && (context->regs[REG_MODE_4] & BIT_INTERLACE)) {
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
3187 context->flags2 ^= FLAG2_EVEN_FIELD;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3188 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3189
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3190 if (dst) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3191 uint8_t bg_index;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3192 if (mode_5) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3193 bg_index = context->regs[REG_BG_COLOR] & 0x3F;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3194 bg_color = context->colors[bg_index];
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3195 } else if (context->regs[REG_MODE_1] & BIT_MODE_4) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3196 bg_index = 0x10 + (context->regs[REG_BG_COLOR] & 0xF);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3197 bg_color = context->colors[MODE4_OFFSET + bg_index];
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3198 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3199 if (context->done_composite) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3200 uint8_t pixel = context->compositebuf[dst-context->output];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3201 if (!(pixel & 0x3F | test_layer)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3202 pixel = pixel & 0xC0 | bg_index;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3203 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3204 *(dst++) = context->colors[pixel];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3205 if ((dst - context->output) == (context->done_composite - context->compositebuf)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3206 context->done_composite = NULL;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3207 memset(context->compositebuf, 0, sizeof(context->compositebuf));
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3208 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3209 } else {
1343
033dda2d4598 Fix transition from active to inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1342
diff changeset
3210 *(dst++) = bg_color;
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3211 *(debug_dst++) = DBG_SRC_BG;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3212 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3213 if (context->done_composite) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3214 uint8_t pixel = context->compositebuf[dst-context->output];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3215 if (!(pixel & 0x3F | test_layer)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3216 pixel = pixel & 0xC0 | bg_index;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3217 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3218 *(dst++) = context->colors[pixel];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3219 if ((dst - context->output) == (context->done_composite - context->compositebuf)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3220 context->done_composite = NULL;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3221 memset(context->compositebuf, 0, sizeof(context->compositebuf));
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3222 }
1343
033dda2d4598 Fix transition from active to inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1342
diff changeset
3223 } else {
033dda2d4598 Fix transition from active to inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1342
diff changeset
3224 *(dst++) = bg_color;
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3225 *(debug_dst++) = DBG_SRC_BG;
1343
033dda2d4598 Fix transition from active to inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1342
diff changeset
3226 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3227
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3228 if (context->hslot == (bg_end_slot-1)) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3229 if (context->done_composite) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3230 uint8_t pixel = context->compositebuf[dst-context->output];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3231 if (!(pixel & 0x3F | test_layer)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3232 pixel = pixel & 0xC0 | bg_index;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3233 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3234 *(dst++) = context->colors[pixel];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3235 if ((dst - context->output) == (context->done_composite - context->compositebuf)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3236 context->done_composite = NULL;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3237 memset(context->compositebuf, 0, sizeof(context->compositebuf));
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3238 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3239 } else {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3240 *(dst++) = bg_color;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3241 *(debug_dst++) = DBG_SRC_BG;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3242 }
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3243 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3244 }
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3245
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3246 if (!is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3247 external_slot(context);
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3248 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3249 run_dma_src(context, context->hslot);
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3250 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3251 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3252
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3253 if (is_h40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3254 if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3255 context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3256 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3257 context->cycles += MCLKS_SLOT_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3258 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3259 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3260 context->cycles += MCLKS_SLOT_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3261 }
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3262 if (context->hslot == jump_start) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3263 context->hslot = jump_dest;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3264 } else {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3265 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3266 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3267 if (context->hslot == line_change) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3268 vdp_advance_line(context);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3269 if (context->vcounter == active_line) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3270 context->state = PREPARING;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3271 return;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3272 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3273 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3274 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3275 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3276
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3277 void vdp_run_context_full(vdp_context * context, uint32_t target_cycles)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3278 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3279 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3280 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3281 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3282 {
1362
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3283 check_switch_inactive(context, is_h40);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3284
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3285 if (is_active(context)) {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3286 if (mode_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3287 if (is_h40) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3288 vdp_h40(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3289 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3290 vdp_h32(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3291 }
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
3292 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3293 vdp_h32_mode4(context, target_cycles);
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
3294 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
3295 } else {
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3296 vdp_inactive(context, target_cycles, is_h40, mode_5);
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3297 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3298 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3299 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3300
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3301 void vdp_run_context(vdp_context *context, uint32_t target_cycles)
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3302 {
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3303 //TODO: Deal with H40 hsync shenanigans
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3304 uint32_t slot_cyc = context->regs[REG_MODE_4] & BIT_H40 ? 15 : 19;
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3305 if (target_cycles < slot_cyc) {
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3306 //avoid overflow
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3307 return;
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3308 }
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3309 vdp_run_context_full(context, target_cycles - slot_cyc);
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3310 }
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3311
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3312 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3313 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3314 uint32_t old_frame = context->frame;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3315 while (context->frame == old_frame) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3316 vdp_run_context_full(context, context->cycles + MCLKS_LINE);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3317 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3318 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3319 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3320
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3321 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3322 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3323 for(;;) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3324 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3325 if (!dmalen) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3326 dmalen = 0x10000;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3327 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3328 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20);
1321
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
3329 if (
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3330 (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_COPY
1321
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
3331 || (((context->cd & 0xF) == VRAM_WRITE) && !(context->regs[REG_MODE_2] & BIT_128K_VRAM))) {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3332 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3333 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
1321
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
3334 //unless 128KB mode is enabled
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3335 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3336 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3337 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3338 if (target_cycles < min_dma_complete) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3339 vdp_run_context_full(context, target_cycles);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3340 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3341 } else {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3342 vdp_run_context_full(context, min_dma_complete);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3343 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3344 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3345 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3346 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3347 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3348 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3349
1154
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3350 static uint16_t get_ext_vcounter(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3351 {
1437
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3352 uint16_t line= context->vcounter;
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3353 if (context->regs[REG_MODE_4] & BIT_INTERLACE) {
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3354 if (context->double_res) {
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3355 line <<= 1;
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3356 } else {
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3357 line &= 0x1FE;
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3358 }
1154
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3359 if (line & 0x100) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3360 line |= 1;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3361 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3362 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3363 return line << 8;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3364 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3365
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3366 void vdp_latch_hv(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3367 {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3368 context->hv_latch = context->hslot | get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3369 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3370
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3371 uint16_t vdp_hv_counter_read(vdp_context * context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3372 {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3373 if ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_1] & BIT_HVC_LATCH)) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3374 return context->hv_latch;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3375 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3376 uint16_t hv;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3377 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3378 hv = context->hslot;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3379 } else {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3380 hv = context->hv_latch & 0xFF;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3381 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3382 hv |= get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3383
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3384 return hv;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3385 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3386
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3387 int vdp_control_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3388 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3389 //printf("control port write: %X at %d\n", value, context->cycles);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3390 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3391 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3392 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3393 if (context->flags & FLAG_PENDING) {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
3394 context->address = (context->address & 0x3FFF) | (value << 14 & 0x1C000);
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3395 //It seems like the DMA enable bit doesn't so much enable DMA so much
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3396 //as it enables changing CD5 from control port writes
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3397 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3398 context->cd = (context->cd & preserve) | ((value >> 2) & ~preserve & 0xFF);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3399 context->flags &= ~FLAG_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3400 //Should these be taken care of here or after the first write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3401 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3402 context->flags2 &= ~FLAG2_READ_PENDING;
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
3403 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3404 if (context->cd & 0x20) {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3405 //
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3406 if((context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) != DMA_FILL) {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3407 //DMA copy or 68K -> VDP, transfer starts immediately
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3408 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot);
1191
8dc50e50ced6 Remove accidentally committed debug logging
Michael Pavone <pavone@retrodev.com>
parents: 1189
diff changeset
3409 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
8dc50e50ced6 Remove accidentally committed debug logging
Michael Pavone <pavone@retrodev.com>
parents: 1189
diff changeset
3410 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]);
1289
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
3411 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
3412 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
3413 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
3414 //sticking with 3 slots for now until I can do some more captures
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3415 vdp_run_context_full(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5));
1285
76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation
Michael Pavone <pavone@retrodev.com>
parents: 1278
diff changeset
3416 context->flags |= FLAG_DMA_RUN;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3417 return 1;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3418 } else {
1285
76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation
Michael Pavone <pavone@retrodev.com>
parents: 1278
diff changeset
3419 context->flags |= FLAG_DMA_RUN;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3420 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3421 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3422 } else {
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
3423 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3424 }
63
a6dd5b7a971b Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents: 58
diff changeset
3425 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3426 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3427 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3428 context->address = (context->address &0xC000) | (value & 0x3FFF);
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3429 context->cd = (context->cd & 0x3C) | (value >> 14);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3430 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3431 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3432 uint8_t reg = (value >> 8) & 0x1F;
1123
d5412f76accc Fix inactive start line for Mode 4 in vdp_next_hint. Fix an off by one error in the range of registers allowed to be written in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1122
diff changeset
3433 if (reg < (mode_5 ? VDP_REGS : 0xB)) {
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
3434 //printf("register %d set to %X\n", reg, value & 0xFF);
480
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
3435 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) {
1154
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3436 vdp_latch_hv(context);
480
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
3437 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
3438 if (reg == REG_BG_COLOR) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
3439 value &= 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
3440 }
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
3441 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3442 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame);
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
3443 }*/
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3444 context->regs[reg] = value;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3445 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3446 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES);
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
3447 if (!context->double_res) {
1106
cacbd3f18f03 Fix field flag handling bug introduced with VDP/render interface cleanup
Michael Pavone <pavone@retrodev.com>
parents: 1103
diff changeset
3448 context->flags2 &= ~FLAG2_EVEN_FIELD;
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
3449 }
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3450 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
3451 if (reg == REG_MODE_1 || reg == REG_MODE_2 || reg == REG_MODE_4) {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3452 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3453 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3454 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3455 } else if (mode_5) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3456 context->flags |= FLAG_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3457 //Should these be taken care of here or after the second write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3458 //context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3459 //context->flags2 &= ~FLAG2_READ_PENDING;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3460 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3461 context->flags &= ~FLAG_READ_FETCHED;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3462 context->flags2 &= ~FLAG2_READ_PENDING;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3463 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3464 }
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3465 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3466 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3467
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3468 void vdp_control_port_write_pbc(vdp_context *context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3469 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3470 if (context->flags2 & FLAG2_BYTE_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3471 uint16_t full_val = value << 8 | context->pending_byte;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3472 context->flags2 &= ~FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3473 //TODO: Deal with fact that Vbus->VDP DMA doesn't do anything in PBC mode
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3474 vdp_control_port_write(context, full_val);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3475 if (context->cd == VRAM_READ) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3476 context->cd = VRAM_READ8;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3477 }
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3478 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3479 context->pending_byte = value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3480 context->flags2 |= FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3481 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3482 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3483
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3484 int vdp_data_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3485 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3486 //printf("data port write: %X at %d\n", value, context->cycles);
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3487 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) != DMA_FILL) {
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3488 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3489 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3490 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3491 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3492 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3493 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3494 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3495 }
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
3496 /*if (context->fifo_cur == context->fifo_end) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3497 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
3498 }*/
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3499 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
3500 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
3501 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3502 while (context->fifo_write == context->fifo_read) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3503 vdp_run_context_full(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3504 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3505 fifo_entry * cur = context->fifo + context->fifo_write;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3506 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3507 cur->address = context->address;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3508 cur->value = value;
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3509 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3510 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3511 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3512 cur->cd = (context->cd & 2) | 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3513 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3514 cur->partial = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3515 if (context->fifo_read < 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3516 context->fifo_read = context->fifo_write;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3517 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3518 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3519 increment_address(context);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3520 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3521 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3522
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3523 void vdp_data_port_write_pbc(vdp_context * context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3524 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3525 if (context->flags & FLAG_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3526 context->flags &= ~FLAG_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3527 //Should these be cleared here?
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3528 context->flags &= ~FLAG_READ_FETCHED;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3529 context->flags2 &= ~FLAG2_READ_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3530 }
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3531 context->flags2 &= ~FLAG2_BYTE_PENDING;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3532 /*if (context->fifo_cur == context->fifo_end) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3533 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3534 }*/
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3535 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3536 context->flags &= ~FLAG_DMA_RUN;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3537 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3538 while (context->fifo_write == context->fifo_read) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3539 vdp_run_context_full(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3540 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3541 fifo_entry * cur = context->fifo + context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3542 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3543 cur->address = context->address;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3544 cur->value = value;
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3545 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3546 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3547 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3548 cur->cd = (context->cd & 2) | 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3549 }
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
3550 cur->partial = 3;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3551 if (context->fifo_read < 0) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3552 context->fifo_read = context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3553 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3554 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3555 increment_address(context);
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3556 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3557
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3558 void vdp_test_port_write(vdp_context * context, uint16_t value)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3559 {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
3560 context->test_port = value;
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3561 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3562
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3563 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3564 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3565 context->flags &= ~FLAG_PENDING;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3566 context->flags2 &= ~FLAG2_BYTE_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3567 //Bits 15-10 are not fixed like Charles MacDonald's doc suggests, but instead open bus values that reflect 68K prefetch
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3568 uint16_t value = context->system->get_open_bus_value(context->system) & 0xFC00;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3569 if (context->fifo_read < 0) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3570 value |= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3571 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3572 if (context->fifo_read == context->fifo_write) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3573 value |= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3574 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3575 if (context->flags2 & FLAG2_VINT_PENDING) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3576 value |= 0x80;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3577 }
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3578 if (context->flags & FLAG_DOT_OFLOW) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3579 value |= 0x40;
1156
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
3580 context->flags &= ~FLAG_DOT_OFLOW;
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3581 }
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3582 if (context->flags2 & FLAG2_SPRITE_COLLIDE) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3583 value |= 0x20;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3584 context->flags2 &= ~FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3585 }
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
3586 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && !(context->flags2 & FLAG2_EVEN_FIELD)) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3587 value |= 0x10;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3588 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3589 uint32_t slot = context->hslot;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3590 if (!is_active(context)) {
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
3591 value |= 0x8;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
3592 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3593 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3594 if (slot < HBLANK_END_H40 || slot > HBLANK_START_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3595 value |= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3596 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3597 } else {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3598 if (slot < HBLANK_END_H32 || slot > HBLANK_START_H32) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3599 value |= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3600 }
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
3601 }
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3602 if (context->cd & 0x20) {
141
576f55711d8d Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents: 138
diff changeset
3603 value |= 0x2;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3604 }
714
e29bc2918f69 Fix VDP status register PAL bit based on observations of the Titan Overdrive demo
Michael Pavone <pavone@retrodev.com>
parents: 711
diff changeset
3605 if (context->flags2 & FLAG2_REGION_PAL) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3606 value |= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3607 }
459
c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
3608 //printf("status read at cycle %d returned %X\n", context->cycles, value);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3609 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3610 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3611
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3612 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3613 {
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3614 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3615 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3616 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3617 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3618 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3619 }
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
3620 if (context->cd & 1) {
991
f9ee6f746cb4 Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents: 984
diff changeset
3621 warning("Read from VDP data port while writes are configured, CPU is now frozen. VDP Address: %X, CD: %X\n", context->address, context->cd);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3622 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3623 while (!(context->flags & FLAG_READ_FETCHED)) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3624 vdp_run_context_full(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3625 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3626 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3627 return context->prefetch;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3628 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3629
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3630 uint8_t vdp_data_port_read_pbc(vdp_context * context)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3631 {
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3632 context->flags &= ~(FLAG_PENDING | FLAG_READ_FETCHED);
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3633 context->flags2 &= ~FLAG2_BYTE_PENDING;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3634
1152
ddbb61be6119 Fix to pass a couple more tests in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1151
diff changeset
3635 context->cd = VRAM_READ8;
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3636 return context->prefetch;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3637 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3638
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3639 uint16_t vdp_test_port_read(vdp_context * context)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3640 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3641 //TODO: Find out what actually gets returned here
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
3642 return context->test_port;
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3643 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3644
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3645 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3646 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3647 context->cycles -= deduction;
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3648 if (context->pending_vint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3649 context->pending_vint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3650 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3651 context->pending_vint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3652 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3653 if (context->pending_hint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3654 context->pending_hint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3655 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3656 context->pending_hint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3657 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3658 if (context->fifo_read >= 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3659 int32_t idx = context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3660 do {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3661 if (context->fifo[idx].cycle >= deduction) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3662 context->fifo[idx].cycle -= deduction;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3663 } else {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3664 context->fifo[idx].cycle = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3665 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3666 idx = (idx+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3667 } while(idx != context->fifo_write);
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3668 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3669 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3670
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
3671 static uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context)
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3672 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3673 if (context->hslot < 183) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3674 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3675 } else if (context->hslot < HSYNC_END_H40) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3676 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3677 uint32_t hsync = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3678 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3679 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3680 hsync += h40_hsync_cycles[i];
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3681 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3682 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3683 return before_hsync + hsync + after_hsync;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3684 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3685 return (256-context->hslot) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3686 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3687 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3688
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
3689 static uint32_t vdp_cycles_next_line(vdp_context * context)
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3690 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3691 if (context->regs[REG_MODE_4] & BIT_H40) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3692 //TODO: Handle "illegal" Mode 4/H40 combo
647
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
3693 if (context->hslot < LINE_CHANGE_H40) {
697
7f96bd1cb1be Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents: 680
diff changeset
3694 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3695 } else {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3696 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3697 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3698 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3699 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3700 if (context->hslot < LINE_CHANGE_H32) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3701 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3702 } else if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3703 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3704 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3705 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3706 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3707 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3708 if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3709 return (148 - context->hslot + LINE_CHANGE_MODE4 - 233) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3710 } else if (context->hslot < LINE_CHANGE_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3711 return (LINE_CHANGE_MODE4 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3712 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3713 return MCLKS_LINE - (context->hslot - LINE_CHANGE_MODE4) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3714 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3715 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3716 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3717 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3718
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3719 static void get_jump_params(vdp_context *context, uint32_t *jump_start, uint32_t *jump_dst)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3720 {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3721 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3722 if (context->flags2 & FLAG2_REGION_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3723 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3724 *jump_start = 0x10B;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3725 *jump_dst = 0x1D2;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3726 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3727 *jump_start = 0x103;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3728 *jump_dst = 0x1CA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3729 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3730 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3731 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3732 *jump_start = 0x100;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3733 *jump_dst = 0x1FA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3734 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3735 *jump_start = 0xEB;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3736 *jump_dst = 0x1E5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3737 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3738 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3739 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3740 *jump_start = 0xDB;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3741 *jump_dst = 0x1D5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3742 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3743 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3744
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
3745 static uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target)
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3746 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3747 uint32_t jump_start, jump_dst;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3748 get_jump_params(context, &jump_start, &jump_dst);
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3749 uint32_t lines;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3750 if (context->vcounter < target) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3751 if (target < jump_start || context->vcounter > jump_start) {
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3752 lines = target - context->vcounter;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3753 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3754 lines = jump_start - context->vcounter + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3755 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3756 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3757 if (context->vcounter < jump_start) {
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
3758 lines = jump_start - context->vcounter + 512 - jump_dst;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3759 } else {
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
3760 lines = 512 - context->vcounter;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3761 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3762 if (target < jump_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3763 lines += target;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3764 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3765 lines += jump_start + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3766 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3767 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3768 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context);
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3769 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3770
680
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
3771 uint32_t vdp_cycles_to_frame_end(vdp_context * context)
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
3772 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3773 return context->cycles + vdp_cycles_to_line(context, context->inactive_start);
680
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
3774 }
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
3775
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3776 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3777 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3778 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3779 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3780 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3781 if (context->flags2 & FLAG2_HINT_PENDING) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3782 return context->pending_hint_start;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3783 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3784 uint32_t hint_line;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3785 if (context->state != ACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3786 hint_line = context->regs[REG_HINT];
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3787 if (hint_line > context->inactive_start) {
724
2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents: 722
diff changeset
3788 return 0xFFFFFFFF;
2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents: 722
diff changeset
3789 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3790 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3791 hint_line = context->vcounter + context->hint_counter + 1;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3792 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3793 if (hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3794 hint_line = context->regs[REG_HINT];
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3795 if (hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3796 return 0xFFFFFFFF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3797 }
1366
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3798 if (hint_line >= context->vcounter) {
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3799 //Next interrupt is for a line in the next frame that
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3800 //is higher than the line we're on now so just passing
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3801 //that line number to vdp_cycles_to_line will yield the wrong
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3802 //result
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3803 return context->cycles + vdp_cycles_to_line(context, 0) + hint_line * MCLKS_LINE;
1366
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3804 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3805 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3806 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3807 uint32_t jump_start, jump_dst;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3808 get_jump_params(context, &jump_start, &jump_dst);
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3809 if (hint_line >= jump_start && context->vcounter < jump_dst) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3810 hint_line = (hint_line + jump_dst - jump_start) & 0x1FF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3811 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3812 if (hint_line < context->vcounter && hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3813 return 0xFFFFFFFF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3814 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3815 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3816 }
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3817 return context->cycles + vdp_cycles_to_line(context, hint_line);
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3818 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3819
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3820 static uint32_t vdp_next_vint_real(vdp_context * context)
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3821 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3822 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3823 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3824 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3825 if (context->flags2 & FLAG2_VINT_PENDING) {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3826 return context->pending_vint_start;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3827 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3828
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3829
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3830 return vdp_next_vint_z80(context);
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3831 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3832
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3833 uint32_t vdp_next_vint(vdp_context *context)
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3834 {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3835 uint32_t ret = vdp_next_vint_real(context);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3836 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3837 static uint32_t last = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3838 if (last != ret) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3839 printf("vdp_next_vint is %d at frame %d, line %d, hslot %d\n", ret, context->frame, context->vcounter, context->hslot);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3840 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3841 last = ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3842 #endif
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3843 return ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3844 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3845
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3846 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3847 {
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3848 uint16_t vint_line = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->inactive_start : context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3849 if (context->vcounter == vint_line) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3850 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3851 if (context->regs[REG_MODE_4] & BIT_H40) {
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3852 if (context->hslot >= LINE_CHANGE_H40 || context->hslot <= VINT_SLOT_H40) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3853 uint32_t cycles = context->cycles;
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3854 if (context->hslot >= LINE_CHANGE_H40) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3855 if (context->hslot < 183) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3856 cycles += (183 - context->hslot) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3857 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3858
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3859 if (context->hslot < HSYNC_SLOT_H40) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3860 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3861 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3862 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ )
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3863 {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3864 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3865 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3866 cycles += (256 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3867 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3868
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3869 cycles += (VINT_SLOT_H40 - (context->hslot >= LINE_CHANGE_H40 ? 0 : context->hslot)) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3870 return cycles;
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
3871 }
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3872 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3873 if (context->hslot >= LINE_CHANGE_H32 || context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3874 if (context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3875 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32;
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3876 } else if (context->hslot < 233) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3877 return context->cycles + (VINT_SLOT_H32 + 256 - 233 + 148 - context->hslot) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3878 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3879 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3880 }
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
3881 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3882 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3883 } else {
1177
67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency
Michael Pavone <pavone@retrodev.com>
parents: 1175
diff changeset
3884 if (context->hslot >= LINE_CHANGE_MODE4) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3885 return context->cycles + (VINT_SLOT_MODE4 + 256 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3886 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3887 if (context->hslot <= VINT_SLOT_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3888 return context->cycles + (VINT_SLOT_MODE4 - context->hslot) * MCLKS_SLOT_H32;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3889 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3890 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3891 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3892 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3893 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3894 if (context->regs[REG_MODE_4] & BIT_H40) {
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3895 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3896 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3897 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3898 }
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3899 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3900 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32;
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3901 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3902 return context->cycles + cycles_to_vint;
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3903 }
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3904
1377
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3905 uint32_t vdp_next_nmi(vdp_context *context)
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3906 {
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3907 if (!(context->flags2 & FLAG2_PAUSE)) {
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3908 return 0xFFFFFFFF;
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3909 }
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3910 return context->cycles + vdp_cycles_to_line(context, 0x1FF);
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3911 }
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3912
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3913 void vdp_pbc_pause(vdp_context *context)
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3914 {
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3915 context->flags2 |= FLAG2_PAUSE;
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3916 }
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3917
953
08346262990b Remove the int number argument to vdp_int_ack since it is no longer used
Michael Pavone <pavone@retrodev.com>
parents: 952
diff changeset
3918 void vdp_int_ack(vdp_context * context)
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3919 {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3920 //CPU interrupt acknowledge is only used in Mode 5
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3921 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3922 //Apparently the VDP interrupt controller is not very smart
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3923 //Instead of paying attention to what interrupt is being acknowledged it just
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3924 //clears the pending flag for whatever interrupt it is currently asserted
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3925 //which may be different from the interrupt it was asserting when the 68k
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3926 //started the interrupt process. The window for this is narrow and depends
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3927 //on the latency between the int enable register write and the interrupt being
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3928 //asserted, but Fatal Rewind depends on this due to some buggy code
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3929 if ((context->flags2 & FLAG2_VINT_PENDING) && (context->regs[REG_MODE_2] & BIT_VINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3930 context->flags2 &= ~FLAG2_VINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3931 } else if((context->flags2 & FLAG2_HINT_PENDING) && (context->regs[REG_MODE_1] & BIT_HINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3932 context->flags2 &= ~FLAG2_HINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3933 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3934 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3935 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3936
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3937 void vdp_serialize(vdp_context *context, serialize_buffer *buf)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3938 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3939 save_int8(buf, VRAM_SIZE / 1024);//VRAM size in KB, needed for future proofing
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3940 save_buffer8(buf, context->vdpmem, VRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3941 save_buffer16(buf, context->cram, CRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3942 save_buffer16(buf, context->vsram, VSRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3943 save_buffer8(buf, context->sat_cache, SAT_CACHE_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3944 for (int i = 0; i <= REG_DMASRC_H; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3945 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3946 save_int8(buf, context->regs[i]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3947 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3948 save_int32(buf, context->address);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3949 save_int32(buf, context->serial_address);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3950 save_int8(buf, context->cd);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3951 uint8_t fifo_size;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3952 if (context->fifo_read < 0) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3953 fifo_size = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3954 } else if (context->fifo_write > context->fifo_read) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3955 fifo_size = context->fifo_write - context->fifo_read;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3956 } else {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3957 fifo_size = context->fifo_write + FIFO_SIZE - context->fifo_read;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3958 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3959 save_int8(buf, fifo_size);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3960 for (int i = 0, cur = context->fifo_read; i < fifo_size; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3961 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3962 fifo_entry *entry = context->fifo + cur;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3963 cur = (cur + 1) & (FIFO_SIZE - 1);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3964 save_int32(buf, entry->cycle);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3965 save_int32(buf, entry->address);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3966 save_int16(buf, entry->value);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3967 save_int8(buf, entry->cd);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3968 save_int8(buf, entry->partial);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3969 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3970 //FIXME: Flag bits should be rearranged for maximum correspondence to status reg
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3971 save_int16(buf, context->flags2 << 8 | context->flags);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3972 save_int32(buf, context->frame);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3973 save_int16(buf, context->vcounter);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3974 save_int8(buf, context->hslot);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3975 save_int16(buf, context->hv_latch);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3976 save_int8(buf, context->state);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3977 save_int16(buf, context->hscroll_a);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3978 save_int16(buf, context->hscroll_b);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3979 save_int16(buf, context->vscroll_latch[0]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3980 save_int16(buf, context->vscroll_latch[1]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3981 save_int16(buf, context->col_1);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3982 save_int16(buf, context->col_2);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3983 save_int16(buf, context->test_port);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3984 save_buffer8(buf, context->tmp_buf_a, SCROLL_BUFFER_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3985 save_buffer8(buf, context->tmp_buf_b, SCROLL_BUFFER_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3986 save_int8(buf, context->buf_a_off);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3987 save_int8(buf, context->buf_b_off);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3988 //FIXME: Sprite rendering state is currently a mess
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3989 save_int8(buf, context->sprite_index);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3990 save_int8(buf, context->sprite_draws);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3991 save_int8(buf, context->slot_counter);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3992 save_int8(buf, context->cur_slot);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3993 for (int i = 0; i < MAX_DRAWS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3994 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3995 sprite_draw *draw = context->sprite_draw_list + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3996 save_int16(buf, draw->address);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3997 save_int16(buf, draw->x_pos);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3998 save_int8(buf, draw->pal_priority);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3999 save_int8(buf, draw->h_flip);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4000 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4001 for (int i = 0; i < MAX_SPRITES_LINE; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4002 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4003 sprite_info *info = context->sprite_info_list + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4004 save_int8(buf, info->size);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4005 save_int8(buf, info->index);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4006 save_int16(buf, info->y);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4007 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4008 save_buffer8(buf, context->linebuf, LINEBUF_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4009
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4010 save_int32(buf, context->cycles);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4011 save_int32(buf, context->pending_vint_start);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4012 save_int32(buf, context->pending_hint_start);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4013 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4014
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4015 void vdp_deserialize(deserialize_buffer *buf, void *vcontext)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4016 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4017 vdp_context *context = vcontext;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4018 uint8_t vramk = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4019 load_buffer8(buf, context->vdpmem, (vramk * 1024) <= VRAM_SIZE ? vramk * 1024 : VRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4020 if ((vramk * 1024) > VRAM_SIZE) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4021 buf->cur_pos += (vramk * 1024) - VRAM_SIZE;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4022 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4023 load_buffer16(buf, context->cram, CRAM_SIZE);
1431
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
4024 for (int i = 0; i < CRAM_SIZE; i++)
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
4025 {
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
4026 update_color_map(context, i, context->cram[i]);
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
4027 }
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4028 load_buffer16(buf, context->vsram, VSRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4029 load_buffer8(buf, context->sat_cache, SAT_CACHE_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4030 for (int i = 0; i <= REG_DMASRC_H; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4031 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4032 context->regs[i] = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4033 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4034 context->address = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4035 context->serial_address = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4036 context->cd = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4037 uint8_t fifo_size = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4038 if (fifo_size > FIFO_SIZE) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4039 fatal_error("Invalid fifo size %d", fifo_size);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4040 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4041 if (fifo_size) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4042 context->fifo_read = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4043 context->fifo_write = fifo_size & (FIFO_SIZE - 1);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4044 for (int i = 0; i < fifo_size; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4045 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4046 fifo_entry *entry = context->fifo + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4047 entry->cycle = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4048 entry->address = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4049 entry->value = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4050 entry->cd = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4051 entry->partial = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4052 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4053 } else {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4054 context->fifo_read = -1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4055 context->fifo_write = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4056 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4057 uint16_t flags = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4058 context->flags2 = flags >> 8;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4059 context->flags = flags;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4060 context->frame = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4061 context->vcounter = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4062 context->hslot = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4063 context->hv_latch = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4064 context->state = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4065 context->hscroll_a = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4066 context->hscroll_b = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4067 context->vscroll_latch[0] = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4068 context->vscroll_latch[1] = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4069 context->col_1 = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4070 context->col_2 = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4071 context->test_port = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4072 load_buffer8(buf, context->tmp_buf_a, SCROLL_BUFFER_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4073 load_buffer8(buf, context->tmp_buf_b, SCROLL_BUFFER_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4074 context->buf_a_off = load_int8(buf) & SCROLL_BUFFER_MASK;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4075 context->buf_b_off = load_int8(buf) & SCROLL_BUFFER_MASK;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4076 context->sprite_index = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4077 context->sprite_draws = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4078 context->slot_counter = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4079 context->cur_slot = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4080 for (int i = 0; i < MAX_DRAWS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4081 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4082 sprite_draw *draw = context->sprite_draw_list + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4083 draw->address = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4084 draw->x_pos = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4085 draw->pal_priority = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4086 draw->h_flip = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4087 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4088 for (int i = 0; i < MAX_SPRITES_LINE; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4089 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4090 sprite_info *info = context->sprite_info_list + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4091 info->size = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4092 info->index = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4093 info->y = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4094 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4095 load_buffer8(buf, context->linebuf, LINEBUF_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4096
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4097 context->cycles = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4098 context->pending_vint_start = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4099 context->pending_hint_start = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4100 update_video_params(context);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4101 }
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4102
1649
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4103 static vdp_context *current_vdp;
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4104 static void vdp_debug_window_close(uint8_t which)
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4105 {
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4106 //TODO: remove need for current_vdp global, and find the VDP via current_system instead
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4107 for (int i = 0; i < VDP_NUM_DEBUG_TYPES; i++)
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4108 {
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4109 if (current_vdp->enabled_debuggers & (1 << i) && which == current_vdp->debug_fb_indices[i]) {
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4110 vdp_toggle_debug_view(current_vdp, i);
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4111 break;
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4112 }
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4113 }
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4114 }
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4115
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4116 void vdp_toggle_debug_view(vdp_context *context, uint8_t debug_type)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4117 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4118 if (context->enabled_debuggers & 1 << debug_type) {
1642
c6b2c0f8cc61 Implemented support for toggling off a debug view
Michael Pavone <pavone@retrodev.com>
parents: 1641
diff changeset
4119 render_destroy_window(context->debug_fb_indices[debug_type]);
c6b2c0f8cc61 Implemented support for toggling off a debug view
Michael Pavone <pavone@retrodev.com>
parents: 1641
diff changeset
4120 context->enabled_debuggers &= ~(1 << debug_type);
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4121 } else {
1634
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4122 uint32_t width,height;
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4123 uint8_t fetch_immediately = 0;
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4124 char *caption;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4125 switch(debug_type)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4126 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4127 case VDP_DEBUG_PLANE:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4128 caption = "BlastEm - VDP Plane Debugger";
1634
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4129 width = height = 1024;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4130 break;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4131 case VDP_DEBUG_VRAM:
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4132 caption = "BlastEm - VDP VRAM Debugger";
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4133 width = 1024;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4134 height = 512;
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4135 break;
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4136 case VDP_DEBUG_CRAM:
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4137 caption = "BlastEm - VDP CRAM Debugger";
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4138 width = 512;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4139 height = 512;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4140 fetch_immediately = 1;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4141 break;
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4142 case VDP_DEBUG_COMPOSITE:
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4143 caption = "BlastEm - VDP Plane Composition Debugger";
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4144 width = LINEBUF_SIZE;
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4145 height = context->inactive_start + context->border_top + context->border_bot;
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4146 fetch_immediately = 1;
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4147 break;
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4148 default:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4149 return;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4150 }
1649
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4151 current_vdp = context;
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4152 context->debug_fb_indices[debug_type] = render_create_window(caption, width, height, vdp_debug_window_close);
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4153 if (context->debug_fb_indices[debug_type]) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4154 context->enabled_debuggers |= 1 << debug_type;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4155 }
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4156 if (fetch_immediately) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4157 context->debug_fbs[debug_type] = render_get_framebuffer(context->debug_fb_indices[debug_type], &context->debug_fb_pitch[debug_type]);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4158 }
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4159 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4160 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4161
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4162 void vdp_inc_debug_mode(vdp_context *context)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4163 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4164 uint8_t active = render_get_active_framebuffer();
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4165 if (active < FRAMEBUFFER_USER_START) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4166 return;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4167 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4168 for (int i = 0; i < VDP_NUM_DEBUG_TYPES; i++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4169 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4170 if (context->enabled_debuggers & (1 << i) && context->debug_fb_indices[i] == active) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4171 context->debug_modes[i]++;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4172 return;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4173 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4174 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4175 }