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annotate vdp.c @ 1821:4f3443ecb6d6

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Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
author Michael Pavone <pavone@retrodev.com>
date Tue, 02 Apr 2019 23:55:21 -0700
parents 8f2e78db0872
children 304d47a5c67f
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1 /*
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2 Copyright 2013 Michael Pavone
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include "vdp.h"
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7 #include "blastem.h"
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8 #include <stdlib.h>
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9 #include <string.h>
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10 #include "render.h"
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11 #include "util.h"
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12
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b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
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13 #define NTSC_INACTIVE_START 224
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14 #define PAL_INACTIVE_START 240
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15 #define MODE4_INACTIVE_START 192
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16 #define BUF_BIT_PRIORITY 0x40
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17 #define MAP_BIT_PRIORITY 0x8000
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18 #define MAP_BIT_H_FLIP 0x800
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19 #define MAP_BIT_V_FLIP 0x1000
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20
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e341fd5aa996 Implement the scroll ring buffer properly without memcpy
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21 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
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22 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
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3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
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23
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24 #define MCLKS_SLOT_H40 16
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25 #define MCLKS_SLOT_H32 20
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26 #define VINT_SLOT_H40 0 //21 slots before HSYNC, 16 during, 10 after
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27 #define VINT_SLOT_H32 0 //old value was 23, but recent tests suggest the actual value is close to the H40 one
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28 #define VINT_SLOT_MODE4 4
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29 #define HSYNC_SLOT_H40 230
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30 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17)
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31 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results
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32 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results
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33 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result
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34 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results
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35 #define LINE_CHANGE_H40 165
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36 #define LINE_CHANGE_H32 133
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37 #define LINE_CHANGE_MODE4 249
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38 #define VBLANK_START_H40 (LINE_CHANGE_H40+2)
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39 #define VBLANK_START_H32 (LINE_CHANGE_H32+2)
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40 #define FIFO_LATENCY 3
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41
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42 #define BORDER_TOP_V24 27
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43 #define BORDER_TOP_V28 11
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44 #define BORDER_TOP_V24_PAL 54
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45 #define BORDER_TOP_V28_PAL 38
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46 #define BORDER_TOP_V30_PAL 30
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47
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48 #define BORDER_BOT_V24 24
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49 #define BORDER_BOT_V28 8
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50 #define BORDER_BOT_V24_PAL 48
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51 #define BORDER_BOT_V28_PAL 32
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52 #define BORDER_BOT_V30_PAL 24
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53
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54 #define INVALID_LINE (PAL_INACTIVE_START+BORDER_TOP_V30_PAL+BORDER_BOT_V30_PAL)
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55
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56 enum {
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57 INACTIVE = 0,
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58 PREPARING, //used for line 0x1FF
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59 ACTIVE
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60 };
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61
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62 static int32_t color_map[1 << 12];
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63 static uint16_t mode4_address_map[0x4000];
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64 static uint32_t planar_to_chunky[256];
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65 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
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66
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67 static uint8_t debug_base[][3] = {
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68 {127, 127, 127}, //BG
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69 {0, 0, 127}, //A
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70 {127, 0, 0}, //Window
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71 {0, 127, 0}, //B
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72 {127, 0, 127} //Sprites
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73 };
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74
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75 static void update_video_params(vdp_context *context)
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76 {
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77 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
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78 if (context->regs[REG_MODE_2] & BIT_PAL) {
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79 if (context->flags2 & FLAG2_REGION_PAL) {
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80 context->inactive_start = PAL_INACTIVE_START;
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81 context->border_top = BORDER_TOP_V30_PAL;
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82 context->border_bot = BORDER_BOT_V30_PAL;
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83 } else {
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84 //the behavior here is rather weird and needs more investigation
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85 context->inactive_start = 0xF0;
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86 context->border_top = 1;
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87 context->border_bot = 3;
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88 }
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89 } else {
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90 context->inactive_start = NTSC_INACTIVE_START;
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91 if (context->flags2 & FLAG2_REGION_PAL) {
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92 context->border_top = BORDER_TOP_V28_PAL;
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93 context->border_bot = BORDER_BOT_V28_PAL;
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94 } else {
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95 context->border_top = BORDER_TOP_V28;
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96 context->border_bot = BORDER_TOP_V28;
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97 }
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98 }
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99 if (context->regs[REG_MODE_4] & BIT_H40) {
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100 context->max_sprites_frame = MAX_SPRITES_FRAME;
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101 context->max_sprites_line = MAX_SPRITES_LINE;
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102 } else {
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103 context->max_sprites_frame = MAX_SPRITES_FRAME_H32;
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104 context->max_sprites_line = MAX_SPRITES_LINE_H32;
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105 }
1325
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106 if (context->state == INACTIVE) {
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107 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active
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108 if (context->vcounter < context->inactive_start) {
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109 context->state = ACTIVE;
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110 } else if (context->vcounter == 0x1FF) {
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111 context->state = PREPARING;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
112 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
113 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
114 } else {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
115 context->inactive_start = MODE4_INACTIVE_START;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
116 if (context->flags2 & FLAG2_REGION_PAL) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
117 context->border_top = BORDER_TOP_V24_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
118 context->border_bot = BORDER_BOT_V24_PAL;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
119 } else {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
120 context->border_top = BORDER_TOP_V24;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
121 context->border_bot = BORDER_BOT_V24;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
122 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
123 if (!(context->regs[REG_MODE_1] & BIT_MODE_4)){
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
124 context->state = INACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
125 } else if (context->state == INACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
126 //Undo forced INACTIVE state due to neither Mode 4 nor Mode 5 being active
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
127 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
128 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
129 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
130 else if (context->vcounter == 0x1FF) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
131 context->state = PREPARING;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
132 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
133 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
134 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
135 }
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
136
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
137 static uint8_t color_map_init_done;
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
138
1640
3602f3b20072 Small cleanup of vdp_context struct layout and removal of separately allocated buffers
Michael Pavone <pavone@retrodev.com>
parents: 1639
diff changeset
139 vdp_context *init_vdp_context(uint8_t region_pal)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
140 {
1640
3602f3b20072 Small cleanup of vdp_context struct layout and removal of separately allocated buffers
Michael Pavone <pavone@retrodev.com>
parents: 1639
diff changeset
141 vdp_context *context = calloc(1, sizeof(vdp_context) + VRAM_SIZE);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
142 if (headless) {
1168
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
143 context->output = malloc(LINEBUF_SIZE * sizeof(uint32_t));
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
144 context->output_pitch = 0;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
145 } else {
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
146 context->cur_buffer = FRAMEBUFFER_ODD;
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
147 context->fb = render_get_framebuffer(FRAMEBUFFER_ODD, &context->output_pitch);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
148 }
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
149 context->sprite_draws = MAX_DRAWS;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
150 context->fifo_write = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
151 context->fifo_read = -1;
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
152 context->regs[REG_HINT] = context->hint_counter = 0xFF;
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
153
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
154 if (!color_map_init_done) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
155 uint8_t b,g,r;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
156 for (uint16_t color = 0; color < (1 << 12); color++) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
157 if (color & FBUF_SHADOW) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
158 b = levels[(color >> 9) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
159 g = levels[(color >> 5) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
160 r = levels[(color >> 1) & 0x7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
161 } else if(color & FBUF_HILIGHT) {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
162 b = levels[((color >> 9) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
163 g = levels[((color >> 5) & 0x7) + 7];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
164 r = levels[((color >> 1) & 0x7) + 7];
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
165 } else if(color & FBUF_MODE4) {
1127
cb4771f4543a Fix Mode 4 color mapping
Michael Pavone <pavone@retrodev.com>
parents: 1125
diff changeset
166 b = levels[(color >> 4 & 0xC) | (color >> 6 & 0x2)];
1125
fba485949723 Brighten up Mode 4 colors
Michael Pavone <pavone@retrodev.com>
parents: 1124
diff changeset
167 g = levels[(color >> 2 & 0x8) | (color >> 1 & 0x4) | (color >> 4 & 0x2)];
fba485949723 Brighten up Mode 4 colors
Michael Pavone <pavone@retrodev.com>
parents: 1124
diff changeset
168 r = levels[(color << 1 & 0xC) | (color >> 1 & 0x2)];
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
169 } else {
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
170 b = levels[(color >> 8) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
171 g = levels[(color >> 4) & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
172 r = levels[color & 0xE];
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
173 }
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
174 color_map[color] = render_map_color(r, g, b);
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
175 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
176 for (uint16_t mode4_addr = 0; mode4_addr < 0x4000; mode4_addr++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
177 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
178 uint16_t mode5_addr = mode4_addr & 0x3DFD;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
179 mode5_addr |= mode4_addr << 8 & 0x200;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
180 mode5_addr |= mode4_addr >> 8 & 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
181 mode4_address_map[mode4_addr] = mode5_addr;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
182 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
183 for (uint32_t planar = 0; planar < 256; planar++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
184 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
185 uint32_t chunky = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
186 for (int bit = 7; bit >= 0; bit--)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
187 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
188 chunky = chunky << 4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
189 chunky |= planar >> bit & 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
190 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
191 planar_to_chunky[planar] = chunky;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
192 }
426
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
193 color_map_init_done = 1;
add9e2f5c0e3 Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
194 }
437
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
195 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++)
afbea09d7fb4 Restore one of the VDP debugging modes
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parents: 436
diff changeset
196 {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
197 uint8_t src = color & DBG_SRC_MASK;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
198 if (src > DBG_SRC_S) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
199 context->debugcolors[color] = 0;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
200 } else {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
201 uint8_t r,g,b;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
202 b = debug_base[src][0];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
203 g = debug_base[src][1];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
204 r = debug_base[src][2];
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
205 if (color & DBG_PRIORITY)
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
206 {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
207 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
208 b += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
209 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
210 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
211 g += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
212 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
213 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
214 r += 48;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
215 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
216 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
217 if (color & DBG_SHADOW) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
218 b /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
219 g /= 2;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
220 r /=2 ;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
221 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
222 if (color & DBG_HILIGHT) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
223 if (b) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
224 b += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
225 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
226 if (g) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
227 g += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
228 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
229 if (r) {
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
230 r += 72;
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
231 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
232 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
233 context->debugcolors[color] = render_map_color(r, g, b);
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
234 }
afbea09d7fb4 Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents: 436
diff changeset
235 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
236 if (region_pal) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
237 context->flags2 |= FLAG2_REGION_PAL;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
238 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
239 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
240 if (!headless) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
241 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * context->border_top);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
242 }
1640
3602f3b20072 Small cleanup of vdp_context struct layout and removal of separately allocated buffers
Michael Pavone <pavone@retrodev.com>
parents: 1639
diff changeset
243 return context;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
245
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
246 void vdp_free(vdp_context *context)
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
247 {
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
248 free(context);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
249 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
250
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
251 static int is_refresh(vdp_context * context, uint32_t slot)
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
252 {
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
253 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
254 return slot == 250 || slot == 26 || slot == 59 || slot == 90 || slot == 122 || slot == 154;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
255 } else {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
256 //TODO: Figure out which slots are refresh when display is off in 32-cell mode
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
257 //These numbers are guesses based on H40 numbers
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
258 return slot == 243 || slot == 19 || slot == 51 || slot == 83 || slot == 115;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
259 //The numbers below are the refresh slots during active display
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
260 //return (slot == 29 || slot == 61 || slot == 93 || slot == 125);
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
261 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
262 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
263
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
264 static void increment_address(vdp_context *context)
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
265 {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
266 context->address += context->regs[REG_AUTOINC];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
267 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
268 context->address++;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
269 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
270 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
271
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
272 static void render_sprite_cells(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
273 {
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
274 sprite_draw * d = context->sprite_draw_list + context->cur_slot;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
275 context->serial_address = d->address;
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
276 if (context->cur_slot >= context->sprite_draws) {
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
277
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
278 uint16_t dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
279 int16_t x;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
280 if (d->h_flip) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
281 x = d->x_pos + 7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
282 dir = -1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
283 } else {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
284 x = d->x_pos;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
285 dir = 1;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
286 }
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
287 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x);
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
288 context->cur_slot--;
143
e5487ef04619 Fix infinite loop bug in sprite rendering
Mike Pavone <pavone@retrodev.com>
parents: 142
diff changeset
289 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) {
1029
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
290 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
291 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
292 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
293 } else if (context->vdpmem[address] >> 4) {
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
294 context->flags2 |= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
295 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
296 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
297 x += dir;
1029
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
298 if (x >= 0 && x < 320) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
299 if (!(context->linebuf[x] & 0xF)) {
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
300 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority;
4263dc9cf86d Fix implementation of sprite collision flag. Old implementation did not make sense.
Michael Pavone <pavone@retrodev.com>
parents: 1019
diff changeset
301 } else if (context->vdpmem[address] & 0xF) {
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
302 context->flags2 |= FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
303 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
305 x += dir;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
306 }
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
307 } else {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
308 context->cur_slot--;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
312 static void fetch_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
313 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
314 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
315 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
316 uint32_t address = mode4_address_map[d->address & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
317 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
318 context->fetch_tmp[1] = context->vdpmem[address + 1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
319 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
320 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
321
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
322 static void render_sprite_cells_mode4(vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
323 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
324 if (context->sprite_index >= context->sprite_draws) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
325 sprite_draw * d = context->sprite_draw_list + context->sprite_index;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
326 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
327 pixels |= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
328 uint32_t address = mode4_address_map[(d->address + 2) & 0x3FFF];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
329 pixels |= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
330 pixels |= planar_to_chunky[context->vdpmem[address + 1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
331 int x = d->x_pos & 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
332 for (int i = 28; i >= 0; i -= 4, x++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
333 {
1155
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
334 if (context->linebuf[x] && (pixels >> i & 0xF)) {
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
335 if (
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
336 ((context->regs[REG_MODE_1] & BIT_SPRITE_8PX) && x > 8)
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
337 || ((!(context->regs[REG_MODE_1] & BIT_SPRITE_8PX)) && x < 256)
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
338 ) {
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
339 context->flags2 |= FLAG2_SPRITE_COLLIDE;
da6a1f156f24 Fix Mode 4 sprite collision flag
Michael Pavone <pavone@retrodev.com>
parents: 1154
diff changeset
340 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
341 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
342 context->linebuf[x] = pixels >> i & 0xF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
343 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
344 }
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
345 context->sprite_index--;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
346 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
347 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
348
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
349 static uint32_t mode5_sat_address(vdp_context *context)
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
350 {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
351 uint32_t addr = context->regs[REG_SAT] << 9;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
352 if (!(context->regs[REG_MODE_2] & BIT_128K_VRAM)) {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
353 addr &= 0xFFFF;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
354 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
355 if (context->regs[REG_MODE_4] & BIT_H40) {
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
356 addr &= 0x1FC00;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
357 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
358 return addr;
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
359 }
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
360
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
361 void vdp_print_sprite_table(vdp_context * context)
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
362 {
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
363 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
364 uint16_t sat_address = mode5_sat_address(context);
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
365 uint16_t current_index = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
366 uint8_t count = 0;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
367 do {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
368 uint16_t address = current_index * 8 + sat_address;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
369 uint16_t cache_address = current_index * 4;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
370 uint8_t height = ((context->sat_cache[cache_address+2] & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
371 uint8_t width = (((context->sat_cache[cache_address+2] >> 2) & 0x3) + 1) * 8;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
372 int16_t y = ((context->sat_cache[cache_address] & 0x3) << 8 | context->sat_cache[cache_address+1]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
373 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
374 uint16_t link = context->sat_cache[cache_address+3] & 0x7F;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
375 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
376 uint8_t pri = context->vdpmem[address + 4] >> 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
377 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
378 printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
379 current_index = link;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
380 count++;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
381 } while (current_index != 0 && count < 80);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
382 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
383 uint16_t sat_address = (context->regs[REG_SAT] & 0x7E) << 7;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
384 for (int i = 0; i < 64; i++)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
385 {
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
386 uint8_t y = context->vdpmem[mode4_address_map[sat_address + (i ^ 1)]];
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
387 if (y == 0xD0) {
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
388 break;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
389 }
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
390 uint8_t x = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2 + 1]];
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
391 uint16_t tile_address = context->vdpmem[mode4_address_map[sat_address + 0x80 + i*2]] * 32
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
392 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
393 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
394 tile_address &= ~32;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
395 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
396 printf("Sprite %d: X=%d, Y=%d, Pat=%X\n", i, x, y, tile_address);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
397 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
398 }
322
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
399 }
8e2fa485c0f2 Remove z80_ram reference in SDL renderer to get stateview compiling again. Print out the sprite list in stateview.
Mike Pavone <pavone@retrodev.com>
parents: 318
diff changeset
400
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
401 #define VRAM_READ 0 //0000
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
402 #define VRAM_WRITE 1 //0001
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
403 //2 would trigger register write 0010
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
404 #define CRAM_WRITE 3 //0011
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
405 #define VSRAM_READ 4 //0100
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
406 #define VSRAM_WRITE 5//0101
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
407 //6 would trigger regsiter write 0110
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
408 //7 is a mystery //0111
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
409 #define CRAM_READ 8 //1000
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
410 //9 is also a mystery //1001
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
411 //A would trigger register write 1010
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
412 //B is a mystery 1011
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
413 #define VRAM_READ8 0xC //1100
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
414 //D is a mystery 1101
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
415 //E would trigger register write 1110
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
416 //F is a mystery 1111
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
417
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
418 //Possible theory on how bits work
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
419 //CD0 = Read/Write flag
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
420 //CD2,(CD1|CD3) = RAM type
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
421 // 00 = VRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
422 // 01 = CRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
423 // 10 = VSRAM
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
424 // 11 = VRAM8
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
425 //Would result in
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
426 // 7 = VRAM8 write
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
427 // 9 = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
428 // B = CRAM write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
429 // D = VRAM8 write alias
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
430 // F = VRAM8 write alais
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
431
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
432 #define DMA_START 0x20
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
433
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
434 static const char * cd_name(uint8_t cd)
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
435 {
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
436 switch (cd & 0xF)
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
437 {
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
438 case VRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
439 return "VRAM read";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
440 case VRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
441 return "VRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
442 case CRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
443 return "CRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
444 case VSRAM_READ:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
445 return "VSRAM read";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
446 case VSRAM_WRITE:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
447 return "VSRAM write";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
448 case VRAM_READ8:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
449 return "VRAM read (undocumented 8-bit mode)";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
450 default:
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
451 return "invalid";
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
452 }
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
453 }
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
454
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
455 void vdp_print_reg_explain(vdp_context * context)
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
456 {
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
457 char * hscroll[] = {"full", "7-line", "cell", "line"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
458 printf("**Mode Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
459 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n"
1331
9bba5ff5beb8 Add 128K VRAM bit to VDP register print in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1325
diff changeset
460 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d, %dK VRAM\n"
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
461 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
462 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n",
757
483f7e7926a6 More clang warning cleanup
Michael Pavone <pavone@retrodev.com>
parents: 748
diff changeset
463 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", (context->regs[REG_MODE_1] & BIT_PAL_SEL) != 0,
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
464 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled",
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
465 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled",
1331
9bba5ff5beb8 Add 128K VRAM bit to VDP register print in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1325
diff changeset
466 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, context->regs[REG_MODE_1] & BIT_128K_VRAM ? 128 : 64,
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
467 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full",
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
468 hscroll[context->regs[REG_MODE_3] & 0x3],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
469 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled");
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
470 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
471 printf("\n**Table Group**\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
472 "02: %.2X | Scroll A Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
473 "03: %.2X | Window Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
474 "04: %.2X | Scroll B Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
475 "05: %.2X | Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
476 "0D: %.2X | HScroll Data Table: $%.4X\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
477 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
478 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
479 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13,
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
480 context->regs[REG_SAT], mode5_sat_address(context),
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
481 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x3F) << 10);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
482 } else {
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
483 printf("\n**Table Group**\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
484 "02: %.2X | Background Name Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
485 "05: %.2X | Sprite Attribute Table: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
486 "06: %.2X | Sprite Tile Base: $%.4X\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
487 "08: %.2X | Background X Scroll: %d\n"
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
488 "09: %.2X | Background Y Scroll: %d\n",
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
489 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0xE) << 10,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
490 context->regs[REG_SAT], (context->regs[REG_SAT] & 0x7E) << 7,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
491 context->regs[REG_STILE_BASE], (context->regs[REG_STILE_BASE] & 2) << 11,
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
492 context->regs[REG_X_SCROLL], context->regs[REG_X_SCROLL],
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
493 context->regs[REG_Y_SCROLL], context->regs[REG_Y_SCROLL]);
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
494
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
495 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
496 char * sizes[] = {"32", "64", "invalid", "128"};
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
497 printf("\n**Misc Group**\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
498 "07: %.2X | Backdrop Color: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
499 "0A: %.2X | H-Int Counter: %u\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
500 "0F: %.2X | Auto-increment: $%X\n"
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
501 "10: %.2X | Scroll A/B Size: %sx%s\n",
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
502 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR],
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
503 context->regs[REG_HINT], context->regs[REG_HINT],
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
504 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC],
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
505 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]);
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
506 char * src_types[] = {"68K", "68K", "Copy", "Fill"};
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
507 printf("\n**DMA Group**\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
508 "13: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
509 "14: %.2X | DMA Length: $%.4X words\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
510 "15: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
511 "16: %.2X |\n"
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
512 "17: %.2X | DMA Source Address: $%.6X, Type: %s\n",
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
513 context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
514 context->regs[REG_DMALEN_H], context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
515 context->regs[REG_DMASRC_L],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
516 context->regs[REG_DMASRC_M],
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
517 context->regs[REG_DMASRC_H],
629
9089951a1994 Small fix to display of DMA source address in vr debug command
Michael Pavone <pavone@retrodev.com>
parents: 624
diff changeset
518 context->regs[REG_DMASRC_H] << 17 | context->regs[REG_DMASRC_M] << 9 | context->regs[REG_DMASRC_L] << 1,
621
5196333b37a6 Fix a few values reported by the vr debugger command. Add DMA registers to vr debugger command. Fix horizontal interrupt bug. Slightly more accurate (but still broken) handling of switches between H32 and H40 modes.
Michael Pavone <pavone@retrodev.com>
parents: 515
diff changeset
519 src_types[context->regs[REG_DMASRC_H] >> 6 & 3]);
1628
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
520 uint8_t old_flags = context->flags;
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
521 uint8_t old_flags2 = context->flags2;
438
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
522 printf("\n**Internal Group**\n"
b3cee2fe690b Add address/cd registers to VDP debug message
Mike Pavone <pavone@retrodev.com>
parents: 437
diff changeset
523 "Address: %X\n"
705
ce4046476abc Add description of cd register value to vr debugger command
Michael Pavone <pavone@retrodev.com>
parents: 699
diff changeset
524 "CD: %X - %s\n"
647
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
525 "Pending: %s\n"
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
526 "VCounter: %d\n"
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
527 "HCounter: %d\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
528 "VINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
529 "HINT Pending: %s\n"
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
530 "Status: %X\n",
1150
322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1149
diff changeset
531 context->address, context->cd, cd_name(context->cd),
322d28e6f13c Display both byte and word pending values to better reflect VDP pending state in PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1149
diff changeset
532 (context->flags & FLAG_PENDING) ? "word" : (context->flags2 & FLAG2_BYTE_PENDING) ? "byte" : "none",
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
533 context->vcounter, context->hslot*2, (context->flags2 & FLAG2_VINT_PENDING) ? "true" : "false",
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
534 (context->flags2 & FLAG2_HINT_PENDING) ? "true" : "false", vdp_control_port_read(context));
1628
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
535 //restore flags as calling vdp_control_port_read can change them
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
536 context->flags = old_flags;
3c1661305219 Avoid changing VDP status flags when executing debugger commands
Michael Pavone <pavone@retrodev.com>
parents: 1454
diff changeset
537 context->flags2 = old_flags2;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
538 }
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
539
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
540 static uint8_t is_active(vdp_context *context)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
541 {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
542 return context->state != INACTIVE && (context->regs[REG_MODE_2] & BIT_DISP_EN) != 0;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
543 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
544
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
545 static void scan_sprite_table(uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
547 if (context->sprite_index && ((uint8_t)context->slot_counter) < context->max_sprites_line) {
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
548 line += 1;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
549 uint16_t ymask, ymin;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
550 uint8_t height_mult;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
551 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
552 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
553 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
554 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
555 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
556 ymask = 0x3FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
557 ymin = 256;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
558 height_mult = 16;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
559 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
560 ymask = 0x1FF;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
561 ymin = 128;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
562 height_mult = 8;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
563 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
564 context->sprite_index &= 0x7F;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
565 //TODO: Implement squirelly behavior documented by Kabuto
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
566 if (context->sprite_index >= context->max_sprites_frame) {
38
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
567 context->sprite_index = 0;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
568 return;
898e3d035f42 Implement sprite index >= sprite limit triggers sprite limit behavior
Mike Pavone <pavone@retrodev.com>
parents: 37
diff changeset
569 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
570 uint16_t address = context->sprite_index * 4;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
571 line += ymin;
1346
f7ca42e020fd Fix sprite rendering in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1344
diff changeset
572 line &= ymask;
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
573 uint16_t y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
574 uint8_t height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
575 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
576 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
577 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
578 context->sprite_info_list[context->slot_counter].size = context->sat_cache[address+2];
1358
3716b90d3470 Fix regression in Mode 4 sprite rendering
Michael Pavone <pavone@retrodev.com>
parents: 1357
diff changeset
579 context->sprite_info_list[context->slot_counter++].index = context->sprite_index;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
580 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
581 context->sprite_index = context->sat_cache[address+3] & 0x7F;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
582 if (context->sprite_index && ((uint8_t)context->slot_counter) < context->max_sprites_line)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
583 {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
584 //TODO: Implement squirelly behavior documented by Kabuto
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
585 if (context->sprite_index >= context->max_sprites_frame) {
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
586 context->sprite_index = 0;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
587 return;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
588 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
589 address = context->sprite_index * 4;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
590 y = ((context->sat_cache[address] & 0x3) << 8 | context->sat_cache[address+1]) & ymask;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
591 height = ((context->sat_cache[address+2] & 0x3) + 1) * height_mult;
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
592 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height);
21
72ce60cb1711 Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents: 20
diff changeset
593 if (y <= line && line < (y + height)) {
27
aa1c47fab3f1 Fix sprite transparency for overlapping sprites
Mike Pavone <pavone@retrodev.com>
parents: 26
diff changeset
594 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line);
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
595 context->sprite_info_list[context->slot_counter].size = context->sat_cache[address+2];
1358
3716b90d3470 Fix regression in Mode 4 sprite rendering
Michael Pavone <pavone@retrodev.com>
parents: 1357
diff changeset
596 context->sprite_info_list[context->slot_counter++].index = context->sprite_index;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
597 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
598 context->sprite_index = context->sat_cache[address+3] & 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
599 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
600 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
601 //TODO: Seems like the overflow flag should be set here if we run out of sprite info slots without hitting the end of the list
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
602 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
603
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
604 static void scan_sprite_table_mode4(vdp_context * context)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
605 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
606 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
607 uint32_t line = context->vcounter;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
608 line &= 0xFF;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
609
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
610 uint32_t sat_address = mode4_address_map[(context->regs[REG_SAT] << 7 & 0x3F00) + context->sprite_index];
1138
25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping
Michael Pavone <pavone@retrodev.com>
parents: 1137
diff changeset
611 uint32_t y = context->vdpmem[sat_address+1];
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
612 uint32_t size = (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) ? 16 : 8;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
613
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
614 if (y == 0xd0) {
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
615 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
616 return;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
617 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
618 if (y <= line && line < (y + size)) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
619 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
620 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
621 context->flags |= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
622 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
623 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
624 context->sprite_info_list[--(context->slot_counter)].size = size;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
625 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
1358
3716b90d3470 Fix regression in Mode 4 sprite rendering
Michael Pavone <pavone@retrodev.com>
parents: 1357
diff changeset
626 context->sprite_info_list[context->slot_counter].y = y;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
627 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
628 context->sprite_index++;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
629 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
630
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
631 if (context->sprite_index < MAX_SPRITES_FRAME_H32) {
1138
25268334a24c Fix Mode 4 sprite table Y scan to account for VRAM byte swapping
Michael Pavone <pavone@retrodev.com>
parents: 1137
diff changeset
632 y = context->vdpmem[sat_address];
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
633 if (y == 0xd0) {
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
634 context->sprite_index = MAX_SPRITES_FRAME_H32;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
635 return;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
636 } else {
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
637 if (y <= line && line < (y + size)) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
638 if (!context->slot_counter) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
639 context->sprite_index = MAX_SPRITES_FRAME_H32;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
640 context->flags |= FLAG_DOT_OFLOW;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
641 return;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
642 }
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
643 context->sprite_info_list[--(context->slot_counter)].size = size;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
644 context->sprite_info_list[context->slot_counter].index = context->sprite_index;
1358
3716b90d3470 Fix regression in Mode 4 sprite rendering
Michael Pavone <pavone@retrodev.com>
parents: 1357
diff changeset
645 context->sprite_info_list[context->slot_counter].y = y;
1122
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
646 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
647 context->sprite_index++;
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
648 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
649 }
d4bef26d0977 Implemented Mode 4 sprite list termination
Michael Pavone <pavone@retrodev.com>
parents: 1121
diff changeset
650
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
651 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
652 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
653
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
654 static void read_sprite_x(uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
655 {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
656 if (context->cur_slot == context->max_sprites_line) {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
657 context->cur_slot = 0;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
658 }
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
659 if (context->cur_slot < context->slot_counter) {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
660 if (context->sprite_draws) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
661 line += 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
662 //in tiles
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
663 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
664 //in pixels
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
665 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
666 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
667 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
668 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
669 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
670 }
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
671 height *= 2;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
672 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
673 uint16_t ymask, ymin;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
674 if (context->double_res) {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
675 ymask = 0x3FF;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
676 ymin = 256;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
677 } else {
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
678 ymask = 0x1FF;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
679 ymin = 128;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
680 }
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
681 uint16_t att_addr = mode5_sat_address(context) + context->sprite_info_list[context->cur_slot].index * 8 + 4;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
682 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1];
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
683 uint8_t pal_priority = (tileinfo >> 9) & 0x70;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
684 uint8_t row;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
685 uint16_t cache_addr = context->sprite_info_list[context->cur_slot].index * 4;
1346
f7ca42e020fd Fix sprite rendering in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1344
diff changeset
686 line = (line + ymin) & ymask;
1338
3706b683cd48 Fix sprite rendering for negative line. Fixes remaining visual glitch in the Titancade scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1337
diff changeset
687 int16_t y = ((context->sat_cache[cache_addr] << 8 | context->sat_cache[cache_addr+1]) & ymask)/* - ymin*/;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
688 if (tileinfo & MAP_BIT_V_FLIP) {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
689 row = (y + height - 1) - line;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
690 } else {
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
691 row = line-y;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
692 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
693 row &= ymask >> 4;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
694 uint16_t address;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
695 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
696 address = ((tileinfo & 0x3FF) << 6) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
697 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
698 address = ((tileinfo & 0x7FF) << 5) + row * 4;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
699 }
323
8c01b4154480 Properly mask sprite X and Y coordinates
Mike Pavone <pavone@retrodev.com>
parents: 322
diff changeset
700 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
701 if (x) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
702 context->flags |= FLAG_CAN_MASK;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
703 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
704 context->flags |= FLAG_MASKED;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
705 }
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
706
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
707 context->flags &= ~FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
708 int16_t i;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
709 if (context->flags & FLAG_MASKED) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
710 for (i=0; i < width && context->sprite_draws; i++) {
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
711 --context->sprite_draws;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
712 context->sprite_draw_list[context->sprite_draws].x_pos = -128;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
713 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
714 }
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
715 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
716 x -= 128;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
717 int16_t base_x = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
718 int16_t dir;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
719 if (tileinfo & MAP_BIT_H_FLIP) {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
720 x += (width-1) * 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
721 dir = -8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
722 } else {
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
723 dir = 8;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
724 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
725 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address);
35
233c7737c152 Small fix to overflow flag
Mike Pavone <pavone@retrodev.com>
parents: 34
diff changeset
726 for (i=0; i < width && context->sprite_draws; i++, x += dir) {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
727 --context->sprite_draws;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
728 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
729 context->sprite_draw_list[context->sprite_draws].x_pos = x;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
730 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
731 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0;
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
732 }
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
733 }
1000
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
734 //Used to be i < width
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
735 //TODO: Confirm this is the right condition on hardware
1a797fcbb35f Added TODO for hardware checking
Michael Pavone <pavone@retrodev.com>
parents: 999
diff changeset
736 if (!context->sprite_draws) {
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
737 context->flags |= FLAG_DOT_OFLOW;
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
738 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
739 } else {
34
0e7df84158b1 Improve sprite masking to almost completely pass Nemesis' sprite masking test
Mike Pavone <pavone@retrodev.com>
parents: 32
diff changeset
740 context->flags |= FLAG_DOT_OFLOW;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
741 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
742 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
743 context->cur_slot++;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
744 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
745
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
746 static void read_sprite_x_mode4(vdp_context * context)
427
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
747 {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
748 if (context->cur_slot >= context->slot_counter) {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
749 uint32_t address = (context->regs[REG_SAT] << 7 & 0x3F00) + 0x80 + context->sprite_info_list[context->cur_slot].index * 2;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
750 address = mode4_address_map[address];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
751 --context->sprite_draws;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
752 uint32_t tile_address = context->vdpmem[address] * 32 + (context->regs[REG_STILE_BASE] << 11 & 0x2000);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
753 if (context->regs[REG_MODE_2] & BIT_SPRITE_SZ) {
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
754 tile_address &= ~32;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
755 }
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
756 tile_address += (context->vcounter - context->sprite_info_list[context->cur_slot].y)* 4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
757 context->sprite_draw_list[context->sprite_draws].x_pos = context->vdpmem[address + 1];
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
758 context->sprite_draw_list[context->sprite_draws].address = tile_address;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
759 context->cur_slot--;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
760 }
427
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
761 }
2802318c14e1 Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents: 426
diff changeset
762
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
763 #define CRAM_BITS 0xEEE
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
764 #define VSRAM_BITS 0x7FF
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
765 #define VSRAM_DIRTY_BITS 0xF800
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
766
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
767 //rough estimate of slot number at which border display starts
1270
687d3969416b Adjust correspondance between slot number and actual video output to better match video signal measurements and analysis of Outrunners behavior on hardware. Partially fixes ticket:13
Michael Pavone <pavone@retrodev.com>
parents: 1269
diff changeset
768 #define BG_START_SLOT 6
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
769
1431
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
770 static void update_color_map(vdp_context *context, uint16_t index, uint16_t value)
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
771 {
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
772 context->colors[index] = color_map[value & CRAM_BITS];
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
773 context->colors[index + SHADOW_OFFSET] = color_map[(value & CRAM_BITS) | FBUF_SHADOW];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
774 context->colors[index + HIGHLIGHT_OFFSET] = color_map[(value & CRAM_BITS) | FBUF_HILIGHT];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
775 context->colors[index + MODE4_OFFSET] = color_map[(value & CRAM_BITS) | FBUF_MODE4];
1431
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
776 }
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
777
1428
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
778 void write_cram_internal(vdp_context * context, uint16_t addr, uint16_t value)
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
779 {
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
780 context->cram[addr] = value;
1431
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
781 update_color_map(context, addr, value);
1428
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
782 }
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
783
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
784 static void write_cram(vdp_context * context, uint16_t address, uint16_t value)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
785 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
786 uint16_t addr;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
787 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
788 addr = (address/2) & (CRAM_SIZE-1);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
789 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
790 addr = address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
791 value = (value << 1 & 0xE) | (value << 2 & 0xE0) | (value & 0xE00);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
792 }
1428
2540c05520f2 New savestates are working. New config file option for selecting format states will be saved in. Mostly complete, needs a little more work before release
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
793 write_cram_internal(context, addr, value);
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
794
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
795 if (context->hslot >= BG_START_SLOT && (
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
796 context->vcounter < context->inactive_start + context->border_bot
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
797 || context->vcounter > 0x200 - context->border_top
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
798 )) {
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
799 uint8_t bg_end_slot = BG_START_SLOT + (context->regs[REG_MODE_4] & BIT_H40) ? LINEBUF_SIZE/2 : (256+HORIZ_BORDER)/2;
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
800 if (context->hslot < bg_end_slot) {
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
801 uint32_t color = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->colors[addr] : context->colors[addr + MODE4_OFFSET];
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
802 context->output[(context->hslot - BG_START_SLOT)*2 + 1] = color;
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
803 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
804 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
805 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
806
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
807 static void vdp_advance_dma(vdp_context * context)
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
808 {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
809 context->regs[REG_DMASRC_L] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
810 if (!context->regs[REG_DMASRC_L]) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
811 context->regs[REG_DMASRC_M] += 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
812 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
813 context->address += context->regs[REG_AUTOINC];
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
814 uint16_t dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
815 context->regs[REG_DMALEN_H] = dma_len >> 8;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
816 context->regs[REG_DMALEN_L] = dma_len;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
817 if (!dma_len) {
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
818 context->flags &= ~FLAG_DMA_RUN;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
819 context->cd &= 0xF;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
820 }
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
821 }
1019
e34334e6c682 Fix GST savestate loading to deal with SAT cache to fix sprite corruption on savestate load. Clear out Z80 native_pc so the Z80 state does not get hosed when loading a savestate while the emulator is already running
Michael Pavone <pavone@retrodev.com>
parents: 1001
diff changeset
822
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
823 static void vdp_check_update_sat(vdp_context *context, uint32_t address, uint16_t value)
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
824 {
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
825 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
826 if (!(address & 4)) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
827 uint32_t sat_address = mode5_sat_address(context);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
828 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
829 uint16_t cache_address = address - sat_address;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
830 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
831 context->sat_cache[cache_address] = value >> 8;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
832 context->sat_cache[cache_address^1] = value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
833 }
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
834 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
835 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
836 }
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
837
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
838 void vdp_check_update_sat_byte(vdp_context *context, uint32_t address, uint8_t value)
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
839 {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
840 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
841 if (!(address & 4)) {
1320
df3d690cb2c3 SAT table register bit 0 is not used in H40 mode. Fixes corrupt sprites in ship crash landing scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1319
diff changeset
842 uint32_t sat_address = mode5_sat_address(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
843 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
844 uint16_t cache_address = address - sat_address;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
845 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
846 context->sat_cache[cache_address] = value;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
847 }
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
848 }
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
849 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
850 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
851
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
852 static void write_vram_word(vdp_context *context, uint32_t address, uint16_t value)
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
853 {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
854 address = (address & 0x3FC) | (address >> 1 & 0xFC01) | (address >> 9 & 0x2);
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
855 address ^= 1;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
856 //TODO: Support an option to actually have 128KB of VRAM
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
857 context->vdpmem[address] = value;
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
858 }
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
859
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
860 static void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value)
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
861 {
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
862 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
863 address &= 0xFFFF;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
864 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
865 address = mode4_address_map[address & 0x3FFF];
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
866 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
867 context->vdpmem[address] = value;
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
868 }
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
869
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
870 #define DMA_FILL 0x80
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
871 #define DMA_COPY 0xC0
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
872 #define DMA_TYPE_MASK 0xC0
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
873 static void external_slot(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
874 {
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
875 if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL && context->fifo_read < 0) {
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
876 context->fifo_read = (context->fifo_write-1) & (FIFO_SIZE-1);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
877 fifo_entry * cur = context->fifo + context->fifo_read;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
878 cur->cycle = context->cycles;
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
879 cur->address = context->address;
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
880 cur->partial = 1;
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
881 vdp_advance_dma(context);
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
882 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
883 fifo_entry * start = context->fifo + context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
884 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
885 switch (start->cd & 0xF)
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
886 {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
887 case VRAM_WRITE:
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
888 if ((context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) == (BIT_128K_VRAM|BIT_MODE_5)) {
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
889 vdp_check_update_sat(context, start->address, start->value);
1319
b6796d63977f Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
Michael Pavone <pavone@retrodev.com>
parents: 1318
diff changeset
890 write_vram_word(context, start->address, start->value);
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
891 } else {
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
892 uint8_t byte = start->partial == 1 ? start->value >> 8 : start->value;
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
893 vdp_check_update_sat_byte(context, start->address ^ 1, byte);
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
894 write_vram_byte(context, start->address ^ 1, byte);
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
895 if (!start->partial) {
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
896 start->address = start->address ^ 1;
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
897 start->partial = 1;
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
898 //skip auto-increment and removal of entry from fifo
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
899 return;
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
900 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
901 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
902 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
903 case CRAM_WRITE: {
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
904 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
905 if (start->partial == 3) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
906 uint16_t val;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
907 if ((start->address & 1) && (context->regs[REG_MODE_2] & BIT_MODE_5)) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
908 val = (context->cram[start->address >> 1 & (CRAM_SIZE-1)] & 0xFF) | start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
909 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
910 uint16_t address = (context->regs[REG_MODE_2] & BIT_MODE_5) ? start->address >> 1 & (CRAM_SIZE-1) : start->address & 0x1F;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
911 val = (context->cram[address] & 0xFF00) | start->value;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
912 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
913 write_cram(context, start->address, val);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
914 } else {
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
915 write_cram(context, start->address, start->partial ? context->fifo[context->fifo_write].value : start->value);
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
916 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
917 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
918 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
919 case VSRAM_WRITE:
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
920 if (((start->address/2) & 63) < VSRAM_SIZE) {
1432
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
921 //printf("VSRAM Write: %X to %X @ frame: %d, vcounter: %d, hslot: %d, cycle: %d\n", start->value, start->address, context->frame, context->vcounter, context->hslot, context->cycles);
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
922 if (start->partial == 3) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
923 if (start->address & 1) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
924 context->vsram[(start->address/2) & 63] &= 0xFF;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
925 context->vsram[(start->address/2) & 63] |= start->value << 8;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
926 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
927 context->vsram[(start->address/2) & 63] &= 0xFF00;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
928 context->vsram[(start->address/2) & 63] |= start->value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
929 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
930 } else {
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
931 context->vsram[(start->address/2) & 63] = start->partial ? context->fifo[context->fifo_write].value : start->value;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
932 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
933 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
934
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
935 break;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
936 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
937 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
938 if (context->fifo_read == context->fifo_write) {
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
939 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) {
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
940 context->flags |= FLAG_DMA_RUN;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
941 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
942 context->fifo_read = -1;
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
943 }
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
944 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_COPY) {
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
945 if (context->flags & FLAG_READ_FETCHED) {
998
bf63cbf1d7bb Implement SAT cache. Causes some graphical corruption in Overdrive due to an unrelated bug.
Michael Pavone <pavone@retrodev.com>
parents: 995
diff changeset
946 write_vram_byte(context, context->address ^ 1, context->prefetch);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
947
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
948 //Update DMA state
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
949 vdp_advance_dma(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
950
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
951 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
952 } else {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
953 context->prefetch = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L] ^ 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
954
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
955 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
956 }
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
957 } else if (!(context->cd & 1) && !(context->flags & (FLAG_READ_FETCHED|FLAG_PENDING))) {
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
958 switch(context->cd & 0xF)
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
959 {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
960 case VRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
961 if (context->flags2 & FLAG2_READ_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
962 context->prefetch |= context->vdpmem[context->address | 1];
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
963 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
964 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
965 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
966 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
967 } else {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
968 //TODO: 128K VRAM Mode
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
969 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
970 context->flags2 |= FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
971 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
972 break;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
973 case VRAM_READ8: {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
974 uint32_t address = context->address ^ 1;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
975 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
976 address = mode4_address_map[address & 0x3FFF];
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
977 }
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
978 context->prefetch = context->vdpmem[address];
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
979 context->prefetch |= context->fifo[context->fifo_write].value & 0xFF00;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
980 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
981 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
982 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
983 break;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
984 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
985 case CRAM_READ:
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
986 context->prefetch = context->cram[(context->address/2) & (CRAM_SIZE-1)] & CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
987 context->prefetch |= context->fifo[context->fifo_write].value & ~CRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
988 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
989 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
990 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
991 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
992 case VSRAM_READ: {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
993 uint16_t address = (context->address /2) & 63;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
994 if (address >= VSRAM_SIZE) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
995 address = 0;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
996 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
997 context->prefetch = context->vsram[address] & VSRAM_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
998 context->prefetch |= context->fifo[context->fifo_write].value & VSRAM_DIRTY_BITS;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
999 context->flags |= FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
1000 //Should this happen after the prefetch or after the read?
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
1001 increment_address(context);
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
1002 break;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
1003 }
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
1004 }
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1005 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1006 }
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1007
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1008 static void run_dma_src(vdp_context * context, int32_t slot)
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1009 {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1010 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1011 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
1012 if (context->fifo_write == context->fifo_read) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1013 return;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1014 }
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1015 fifo_entry * cur = NULL;
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1016 if (!(context->regs[REG_DMASRC_H] & 0x80))
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
1017 {
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1018 //68K -> VDP
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
1019 if (slot == -1 || !is_refresh(context, slot-1)) {
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1020 cur = context->fifo + context->fifo_write;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
1021 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
478
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1022 cur->address = context->address;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1023 cur->value = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1024 cur->cd = context->cd;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1025 cur->partial = 0;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1026 if (context->fifo_read < 0) {
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1027 context->fifo_read = context->fifo_write;
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1028 }
2e4a4188cfb0 Fix DMA fill so that it does not cause observable changes to the FIFO. Get DMA copy mostly correct from an observable ffect perspective. DMA copy probably does not reflect internal implementation still given that evidence seems to suggest no FIFO usage at all.
Mike Pavone <pavone@retrodev.com>
parents: 477
diff changeset
1029 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
984
bd4d698d995b FIFO should show as empty during a DMA fill after the initial write is done. BlastEm now gets a perfect score in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 983
diff changeset
1030 vdp_advance_dma(context);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
1031 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1032 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1033 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1034
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1035 #define WINDOW_RIGHT 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1036 #define WINDOW_DOWN 0x80
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1037
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1038 static void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1039 {
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1040 uint16_t window_line_shift, v_offset_mask, vscroll_shift;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1041 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1042 line *= 2;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
1043 if (context->flags2 & FLAG2_EVEN_FIELD) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1044 line++;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1045 }
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1046 window_line_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1047 v_offset_mask = 0xF;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1048 vscroll_shift = 4;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1049 } else {
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1050 window_line_shift = 3;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1051 v_offset_mask = 0x7;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1052 vscroll_shift = 3;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1053 }
1344
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1054 //TODO: Further research on vscroll latch behavior and the "first column bug"
1422
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
1055 if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
1056 if (!column) {
1344
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1057 if (context->regs[REG_MODE_4] & BIT_H40) {
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1058 //Based on observed behavior documented by Eke-Eke, I'm guessing the VDP
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1059 //ends up fetching the last value on the VSRAM bus in the H40 case
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1060 //getting the last latched value should be close enough for now
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1061 if (!vsram_off) {
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1062 context->vscroll_latch[0] = context->vscroll_latch[1];
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1063 }
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1064 } else {
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1065 //supposedly it's always forced to 0 in the H32 case
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1066 context->vscroll_latch[0] = context->vscroll_latch[1] = 0;
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1067 }
1422
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
1068 } else if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
1069 context->vscroll_latch[vsram_off] = context->vsram[column - 2 + vsram_off];
1344
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1070 }
6372de4da179 Fix vscroll latching when full screen vscroll is used in combination with the window plane on the left side of the screen
Michael Pavone <pavone@retrodev.com>
parents: 1343
diff changeset
1071 }
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1072 if (!vsram_off) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1073 uint16_t left_col, right_col;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1074 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) {
920
e64168bb2b25 Fix calculation of window start column when it's on the right side. This removes graphical glitches in Afterburner 2, Fireshark and Dungeons and Dragons: Warriors of the Eternal Sun and probably others
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
1075 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2 + 2;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1076 right_col = 42;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1077 } else {
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1078 left_col = 0;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1079 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1080 if (right_col) {
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1081 right_col += 2;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1082 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1083 }
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1084 uint16_t top_line, bottom_line;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1085 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) {
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1086 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1087 bottom_line = context->double_res ? 481 : 241;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1088 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1089 top_line = 0;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1090 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1091 }
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1092 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1093 uint16_t address = context->regs[REG_WINDOW] << 10;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1094 uint16_t line_offset, offset, mask;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
1095 if (context->regs[REG_MODE_4] & BIT_H40) {
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1096 address &= 0xF000;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1097 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1098 mask = 0x7F;
450
3758bcdae5de Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents: 438
diff changeset
1099
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1100 } else {
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1101 address &= 0xF800;
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1102 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1103 mask = 0x3F;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1104 }
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1105 if (context->double_res) {
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1106 mask <<= 1;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1107 mask |= 1;
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1108 }
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
1109 offset = address + line_offset + (((column - 2) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1110 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
1111 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]);
42
6653e67a6811 Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents: 41
diff changeset
1112 offset = address + line_offset + (((column - 1) * 2) & mask);
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1113 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
417
acdd6c5240fe Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 415
diff changeset
1114 context->v_offset = (line) & v_offset_mask;
41
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1115 context->flags |= FLAG_WINDOW;
e591004487bc More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents: 40
diff changeset
1116 return;
40
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1117 }
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1118 context->flags &= ~FLAG_WINDOW;
7368a7071908 Broken window support
Mike Pavone <pavone@retrodev.com>
parents: 39
diff changeset
1119 }
1290
aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk
Michael Pavone <pavone@retrodev.com>
parents: 1289
diff changeset
1120 //TODO: Verify behavior for 0x20 case
aa1a8eb5bb2b Change handling of invalid scroll plane sizes. Fixes title and high score screens in The Incredible Hulk
Michael Pavone <pavone@retrodev.com>
parents: 1289
diff changeset
1121 uint16_t vscroll = 0xFF | (context->regs[REG_SCROLL] & 0x30) << 4;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1122 if (context->double_res) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1123 vscroll <<= 1;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1124 vscroll |= 1;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1125 }
710
4cd8823f79e3 First pass at emulating a vscroll latch. Titan's Overdrive demo seems to depend on the scroll value being latched early in the line before the HINT gets a chance to change it
Michael Pavone <pavone@retrodev.com>
parents: 708
diff changeset
1126 vscroll &= context->vscroll_latch[vsram_off] + line;
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1127 context->v_offset = vscroll & v_offset_mask;
26
a7c2b92d8056 Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents: 25
diff changeset
1128 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset);
414
51ee0f117365 Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents: 413
diff changeset
1129 vscroll >>= vscroll_shift;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1130 uint16_t hscroll_mask;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1131 uint16_t v_mul;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1132 switch(context->regs[REG_SCROLL] & 0x3)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1133 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1134 case 0:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1135 hscroll_mask = 0x1F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1136 v_mul = 64;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1137 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1138 case 0x1:
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1139 hscroll_mask = 0x3F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1140 v_mul = 128;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1141 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1142 case 0x2:
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1143 //TODO: Verify this behavior
1334
7757d605e365 Adjust how the invalid size is handled for the horizontal dimmension of a plane. Fixes some garbage on the spinning cube scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1333
diff changeset
1144 hscroll_mask = 0x1F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1145 v_mul = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1146 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1147 case 0x3:
108
1a551a85cb06 Fix horizontal mask values for scroll plane map address calculation
Mike Pavone <pavone@retrodev.com>
parents: 87
diff changeset
1148 hscroll_mask = 0x7F;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1149 v_mul = 256;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1150 break;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1151 }
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1152 uint16_t hscroll, offset;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1153 for (int i = 0; i < 2; i++) {
39
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1154 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask;
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1155 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF);
3c69319269ef Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents: 38
diff changeset
1156 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset);
28
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1157 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1];
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1158 if (i) {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1159 context->col_2 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1160 } else {
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1161 context->col_1 = col_val;
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1162 }
037963b4c92d Fix BG plane B render bug
Mike Pavone <pavone@retrodev.com>
parents: 27
diff changeset
1163 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1164 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1165
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1166 static void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1167 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
1168 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1169 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1170
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1171 static void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1172 {
25
4d0c20ad815a Fix vertical scroll value for plane B
Mike Pavone <pavone@retrodev.com>
parents: 24
diff changeset
1173 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1174 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1175
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1176 static void read_map_mode4(uint16_t column, uint32_t line, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1177 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1178 uint32_t address = (context->regs[REG_SCROLL_A] & 0xE) << 10;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1179 //add row
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1180 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1181 if (column < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1182 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1183 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1184 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1185 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1186 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1187 address += (vscroll >> 3) * 2 * 32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1188 //add column
1136
52f25c41abdd Fix horizontal scrolling in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1135
diff changeset
1189 address += ((column - (context->hscroll_a >> 3)) & 31) * 2;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1190 //adjust for weird VRAM mapping in Mode 4
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1191 address = mode4_address_map[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1192 context->col_1 = (context->vdpmem[address] << 8) | context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1193 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1194
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1195 static void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1196 {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1197 uint16_t address;
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1198 uint16_t vflip_base;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1199 if (context->double_res) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1200 address = ((col & 0x3FF) << 6);
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1201 vflip_base = 60;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1202 } else {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1203 address = ((col & 0x7FF) << 5);
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1204 vflip_base = 28;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
1205 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1206 if (col & MAP_BIT_V_FLIP) {
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1207 address += vflip_base - 4 * context->v_offset;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1208 } else {
1032
679137a0e78e Fix bug in vflip implementation when in double resolution interlace mode
Michael Pavone <pavone@retrodev.com>
parents: 1029
diff changeset
1209 address += 4 * context->v_offset;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1210 }
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1211 uint8_t pal_priority = (col >> 9) & 0x70;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1212 uint32_t bits = *((uint32_t *)(&context->vdpmem[address]));
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1213 if (col & MAP_BIT_H_FLIP) {
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1214 uint32_t shift = 28;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1215 for (int i = 0; i < 4; i++)
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1216 {
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1217 uint8_t right = pal_priority | ((bits >> shift) & 0xF);
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1218 shift -= 4;
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1219 tmp_buf[offset++] = pal_priority | ((bits >> shift) & 0xF);
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1220 shift -= 4;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1221 offset &= SCROLL_BUFFER_MASK;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1222 tmp_buf[offset++] = right;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1223 offset &= SCROLL_BUFFER_MASK;
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1224 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1225 } else {
1653
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1226 for (int i = 0; i < 4; i++)
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1227 {
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1228 uint8_t right = pal_priority | (bits & 0xF);
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1229 bits >>= 4;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1230 tmp_buf[offset++] = pal_priority | (bits & 0xF);
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1231 offset &= SCROLL_BUFFER_MASK;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1232 bits >>= 4;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1233 tmp_buf[offset++] = right;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1234 offset &= SCROLL_BUFFER_MASK;
858d52140375 Small optimization to render_map
Michael Pavone <pavone@retrodev.com>
parents: 1652
diff changeset
1235 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1236 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1237 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1238
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1239 static void render_map_1(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1240 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1241 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1242 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1243
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1244 static void render_map_2(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1245 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1246 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1247 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1248
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1249 static void render_map_3(vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1250 {
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1251 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context);
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1252 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1253
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1254 static void fetch_map_mode4(uint16_t col, uint32_t line, vdp_context *context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1255 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1256 //calculate pixel row to fetch
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1257 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1258 if (col < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1259 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1260 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1261 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1262 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1263 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1264 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1265 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1266 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1267 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1268
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1269 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1270 context->fetch_tmp[0] = context->vdpmem[address];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1271 context->fetch_tmp[1] = context->vdpmem[address+1];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1272 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1273
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1274 static uint8_t composite_normal(vdp_context *context, uint8_t *debug_dst, uint8_t sprite, uint8_t plane_a, uint8_t plane_b, uint8_t bg_index)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1275 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1276 uint8_t pixel = bg_index;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1277 uint8_t src = DBG_SRC_BG;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1278 if (plane_b & 0xF) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1279 pixel = plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1280 src = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1281 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1282 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1283 pixel = plane_a;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1284 src = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1285 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1286 if (sprite & 0xF && (sprite & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1287 pixel = sprite;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1288 src = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1289 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1290 *debug_dst = src;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1291 return pixel;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1292 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1293 typedef struct {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1294 uint8_t index, intensity;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1295 } sh_pixel;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1296
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1297 static sh_pixel composite_highlight(vdp_context *context, uint8_t *debug_dst, uint8_t sprite, uint8_t plane_a, uint8_t plane_b, uint8_t bg_index)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1298 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1299 uint8_t pixel = bg_index;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1300 uint8_t src = DBG_SRC_BG;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1301 uint8_t intensity = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1302 if (plane_b & 0xF) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1303 pixel = plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1304 src = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1305 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1306 intensity = plane_b & BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1307 if (plane_a & 0xF && (plane_a & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1308 pixel = plane_a;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1309 src = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1310 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1311 intensity |= plane_a & BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1312 if (sprite & 0xF && (sprite & BUF_BIT_PRIORITY) >= (pixel & BUF_BIT_PRIORITY)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1313 if ((sprite & 0x3F) == 0x3E) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1314 intensity += BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1315 } else if ((sprite & 0x3F) == 0x3F) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1316 intensity = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1317 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1318 pixel = sprite;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1319 src = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1320 if ((pixel & 0xF) == 0xE) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1321 intensity = BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1322 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1323 intensity |= pixel & BUF_BIT_PRIORITY;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1324 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1325 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1326 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1327 *debug_dst = src;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1328 return (sh_pixel){.index = pixel, .intensity = intensity};
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1329 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1330
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1331 static void render_normal(vdp_context *context, int32_t col, uint8_t *dst, uint8_t *debug_dst, int plane_a_off, int plane_b_off)
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1332 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1333 int start = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1334 if (!col && (context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1335 memset(dst, 0, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1336 memset(debug_dst, DBG_SRC_BG, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1337 dst += 8;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1338 debug_dst += 8;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1339 start = 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1340 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1341 uint8_t *sprite_buf = context->linebuf + col * 8 + start;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1342 for (int i = start; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1343 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1344 uint8_t sprite, plane_a, plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1345 plane_a = context->tmp_buf_a[plane_a_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1346 plane_b = context->tmp_buf_b[plane_b_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1347 sprite = *sprite_buf;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1348 *(dst++) = composite_normal(context, debug_dst, sprite, plane_a, plane_b, context->regs[REG_BG_COLOR]) & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1349 debug_dst++;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1350 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1351 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1352
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1353 static void render_highlight(vdp_context *context, int32_t col, uint8_t *dst, uint8_t *debug_dst, int plane_a_off, int plane_b_off)
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1354 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1355 int start = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1356 if (!col && (context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1357 memset(dst, SHADOW_OFFSET + (context->regs[REG_BG_COLOR] & 0x3F), 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1358 memset(debug_dst, DBG_SRC_BG | DBG_SHADOW, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1359 dst += 8;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1360 debug_dst += 8;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1361 start = 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1362 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1363 uint8_t *sprite_buf = context->linebuf + col * 8 + start;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1364 for (int i = start; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1365 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1366 uint8_t sprite, plane_a, plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1367 plane_a = context->tmp_buf_a[plane_a_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1368 plane_b = context->tmp_buf_b[plane_b_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1369 sprite = *sprite_buf;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1370 sh_pixel pixel = composite_highlight(context, debug_dst, sprite, plane_a, plane_b, context->regs[REG_BG_COLOR]);
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1371 uint8_t final_pixel;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1372 if (pixel.intensity == BUF_BIT_PRIORITY << 1) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1373 final_pixel = (pixel.index & 0x3F) + HIGHLIGHT_OFFSET;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1374 } else if (pixel.intensity) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1375 final_pixel = pixel.index & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1376 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1377 final_pixel = (pixel.index & 0x3F) + SHADOW_OFFSET;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1378 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1379 debug_dst++;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1380 *(dst++) = final_pixel;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1381 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1382 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1383
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1384 static void render_testreg(vdp_context *context, int32_t col, uint8_t *dst, uint8_t *debug_dst, int plane_a_off, int plane_b_off, uint8_t output_disabled, uint8_t test_layer)
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1385 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1386 if (output_disabled) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1387 switch (test_layer)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1388 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1389 case 0:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1390 for (int i = 0; i < 16; i++)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1391 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1392 *(dst++) = 0x3F; //TODO: confirm this on hardware
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1393 *(debug_dst++) = DBG_SRC_BG;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1394 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1395 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1396 case 1: {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1397 uint8_t *sprite_buf = context->linebuf + col * 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1398 for (int i = 0; i < 16; i++)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1399 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1400 *(dst++) = *(sprite_buf++) & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1401 *(debug_dst++) = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1402 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1403 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1404 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1405 case 2:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1406 for (int i = 0; i < 16; i++)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1407 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1408 *(dst++) = context->tmp_buf_a[(plane_a_off++) & SCROLL_BUFFER_MASK] & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1409 *(debug_dst++) = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1410 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1411 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1412 case 3:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1413 for (int i = 0; i < 16; i++)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1414 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1415 *(dst++) = context->tmp_buf_b[(plane_b_off++) & SCROLL_BUFFER_MASK] & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1416 *(debug_dst++) = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1417 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1418 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1419 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1420 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1421 int start = 0;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1422 uint8_t *sprite_buf = context->linebuf + col * 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1423 if (!col && (context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1424 //TODO: Confirm how test register interacts with column 0 blanking
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1425 uint8_t pixel = 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1426 uint8_t src = DBG_SRC_BG;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1427 for (int i = 0; i < 8; ++i)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1428 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1429 switch (test_layer)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1430 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1431 case 1:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1432 pixel &= sprite_buf[i];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1433 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1434 src = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1435 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1436 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1437 case 2:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1438 pixel &= context->tmp_buf_a[(plane_a_off + i) & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1439 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1440 src = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1441 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1442 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1443 case 3:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1444 pixel &= context->tmp_buf_b[(plane_b_off + i) & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1445 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1446 src = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1447 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1448 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1449 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1450
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1451 *(dst++) = pixel;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1452 *(debug_dst++) = src;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1453 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1454 plane_a_off += 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1455 plane_b_off += 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1456 sprite_buf += 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1457 start = 8;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1458 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1459 for (int i = start; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1460 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1461 uint8_t sprite, plane_a, plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1462 plane_a = context->tmp_buf_a[plane_a_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1463 plane_b = context->tmp_buf_b[plane_b_off & SCROLL_BUFFER_MASK];
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1464 sprite = *sprite_buf;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1465 uint8_t pixel = composite_normal(context, debug_dst, sprite, plane_a, plane_b, 0x3F) & 0x3F;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1466 switch (test_layer)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1467 {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1468 case 1:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1469 pixel &= sprite;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1470 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1471 *debug_dst = DBG_SRC_S;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1472 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1473 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1474 case 2:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1475 pixel &= plane_a;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1476 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1477 *debug_dst = DBG_SRC_A;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1478 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1479 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1480 case 3:
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1481 pixel &= plane_b;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1482 if (pixel) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1483 *debug_dst = DBG_SRC_B;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1484 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1485 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1486 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1487 debug_dst++;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1488 *(dst++) = pixel;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1489 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1490 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1491 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1492
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1493 static void render_testreg_highlight(vdp_context *context, int32_t col, uint8_t *dst, uint8_t *debug_dst, int plane_a_off, int plane_b_off, uint8_t output_disabled, uint8_t test_layer)
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1494 {
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1495 int start = 0;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1496 uint8_t *sprite_buf = context->linebuf + col * 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1497 if (!col && (context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1498 //TODO: Confirm how test register interacts with column 0 blanking
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1499 uint8_t pixel = 0x3F;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1500 uint8_t src = DBG_SRC_BG | DBG_SHADOW;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1501 for (int i = 0; i < 8; ++i)
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1502 {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1503 switch (test_layer)
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1504 {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1505 case 1:
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1506 pixel &= sprite_buf[i];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1507 if (pixel) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1508 src = DBG_SRC_S | DBG_SHADOW;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1509 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1510 break;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1511 case 2:
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1512 pixel &= context->tmp_buf_a[(plane_a_off + i) & SCROLL_BUFFER_MASK];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1513 if (pixel) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1514 src = DBG_SRC_A | DBG_SHADOW;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1515 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1516 break;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1517 case 3:
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1518 pixel &= context->tmp_buf_b[(plane_b_off + i) & SCROLL_BUFFER_MASK];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1519 if (pixel) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1520 src = DBG_SRC_B | DBG_SHADOW;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1521 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1522 break;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1523 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1524
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1525 *(dst++) = SHADOW_OFFSET + pixel;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1526 *(debug_dst++) = src;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1527 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1528 plane_a_off += 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1529 plane_b_off += 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1530 sprite_buf += 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1531 start = 8;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1532 }
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1533 for (int i = start; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i)
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1534 {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1535 uint8_t sprite, plane_a, plane_b;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1536 plane_a = context->tmp_buf_a[plane_a_off & SCROLL_BUFFER_MASK];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1537 plane_b = context->tmp_buf_b[plane_b_off & SCROLL_BUFFER_MASK];
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1538 sprite = *sprite_buf;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1539 sh_pixel pixel = composite_highlight(context, debug_dst, sprite, plane_a, plane_b, 0x3F);
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1540 if (output_disabled) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1541 pixel.index = 0x3F;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1542 } else {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1543 pixel.index &= 0x3F;
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1544 }
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1545 switch (test_layer)
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1546 {
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1547 case 1:
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1548 pixel.index &= sprite;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1549 if (pixel.index) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1550 *debug_dst = DBG_SRC_S;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1551 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1552 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1553 case 2:
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1554 pixel.index &= plane_a;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1555 if (pixel.index) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1556 *debug_dst = DBG_SRC_A;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1557 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1558 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1559 case 3:
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1560 pixel.index &= plane_b;
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1561 if (pixel.index) {
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1562 *debug_dst = DBG_SRC_B;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1563 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1564 break;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1565 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1566 if (pixel.intensity == BUF_BIT_PRIORITY << 1) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1567 pixel.index += HIGHLIGHT_OFFSET;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1568 } else if (!pixel.intensity) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1569 pixel.index += SHADOW_OFFSET;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1570 }
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1571 debug_dst++;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1572 *(dst++) = pixel.index;
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1573 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1574 }
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1575
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1576 static void render_map_output(uint32_t line, int32_t col, vdp_context * context)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1577 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1578 uint8_t *dst;
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1579 uint8_t *debug_dst;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1580 uint8_t output_disabled = (context->test_port & TEST_BIT_DISABLE) != 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1581 uint8_t test_layer = context->test_port >> 7 & 3;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
1582 if (context->state == PREPARING && !test_layer) {
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1583 if (col) {
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1584 col -= 2;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1585 dst = context->compositebuf + BORDER_LEFT + col * 8;
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1586 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1587 dst = context->compositebuf;
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1588 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1589 memset(dst, 0, BORDER_LEFT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1590 context->done_composite = dst + BORDER_LEFT;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1591 return;
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1592 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1593 memset(dst, 0, 16);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1594 context->done_composite = dst + 16;
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1595 return;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
1596 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1597 line &= 0xFF;
1180
e2b81a0f8fd8 Undo poorly thought out minor optimization that screwed up rendering
Michael Pavone <pavone@retrodev.com>
parents: 1179
diff changeset
1598 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context);
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1599 uint8_t *sprite_buf;
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1600 uint8_t sprite, plane_a, plane_b;
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1601 int plane_a_off, plane_b_off;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1602 if (col)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1603 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1604 col-=2;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1605 dst = context->compositebuf + BORDER_LEFT + col * 8;
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1606 debug_dst = context->layer_debug_buf + BORDER_LEFT + col * 8;
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1607
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1608
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1609 uint8_t a_src, src;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1610 if (context->flags & FLAG_WINDOW) {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1611 plane_a_off = context->buf_a_off;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1612 a_src = DBG_SRC_W;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1613 } else {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1614 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF);
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1615 a_src = DBG_SRC_A;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1616 }
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1617 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF);
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1618 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7));
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1619
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1620 if (context->regs[REG_MODE_4] & BIT_HILIGHT) {
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1621 if (output_disabled || test_layer) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1622 render_testreg_highlight(context, col, dst, debug_dst, plane_a_off, plane_b_off, output_disabled, test_layer);
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1623 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1624 render_highlight(context, col, dst, debug_dst, plane_a_off, plane_b_off);
722
8f5339961903 Restore the other 2 debug display modes
Michael Pavone <pavone@retrodev.com>
parents: 720
diff changeset
1625 }
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1626 } else {
1652
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1627 if (output_disabled || test_layer) {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1628 render_testreg(context, col, dst, debug_dst, plane_a_off, plane_b_off, output_disabled, test_layer);
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1629 } else {
d0a69348add8 Optimized render_map_output a bit
Michael Pavone <pavone@retrodev.com>
parents: 1649
diff changeset
1630 render_normal(context, col, dst, debug_dst, plane_a_off, plane_b_off);
230
d3266cee02c9 Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents: 191
diff changeset
1631 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1632 }
1655
3128d4e0bc68 Fix some rendering bugs introduced in previous VDP optimizations
Michael Pavone <pavone@retrodev.com>
parents: 1653
diff changeset
1633 dst += 16;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1634 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1635 dst = context->compositebuf;
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1636 debug_dst = context->layer_debug_buf;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1637 uint8_t pixel = 0;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1638 if (output_disabled) {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1639 pixel = 0x3F;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1640 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1641 if (test_layer) {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1642 switch(test_layer)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1643 {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1644 case 1:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1645 memset(dst, 0, BORDER_LEFT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1646 memset(debug_dst, DBG_SRC_BG, BORDER_LEFT);
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1647 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1648 case 2: {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1649 //plane A
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1650 //TODO: Deal with Window layer
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1651 int i;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1652 i = 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1653 uint8_t buf_off = context->buf_a_off - (context->hscroll_a & 0xF) + (16 - BORDER_LEFT);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1654 //uint8_t *src = context->tmp_buf_a + ((context->buf_a_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_a & 0xF))) & SCROLL_BUFFER_MASK);
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1655 for (; i < BORDER_LEFT; buf_off++, i++, dst++, debug_dst++)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1656 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1657 *dst = context->tmp_buf_a[buf_off & SCROLL_BUFFER_MASK];
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1658 *debug_dst = DBG_SRC_A;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1659 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1660 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1661 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1662 case 3: {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1663 //plane B
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1664 int i;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1665 i = 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1666 uint8_t buf_off = context->buf_b_off - (context->hscroll_b & 0xF) + (16 - BORDER_LEFT);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1667 //uint8_t *src = context->tmp_buf_b + ((context->buf_b_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_b & 0xF))) & SCROLL_BUFFER_MASK);
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1668 for (; i < BORDER_LEFT; buf_off++, i++, dst++, debug_dst++)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1669 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1670 *dst = context->tmp_buf_b[buf_off & SCROLL_BUFFER_MASK];
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1671 *debug_dst = DBG_SRC_B;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1672 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1673 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1674 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1675 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1676 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1677 memset(dst, pixel, BORDER_LEFT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1678 memset(debug_dst, DBG_SRC_BG, BORDER_LEFT);
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
1679 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1680 dst += BORDER_LEFT;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1681 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1682 context->done_composite = dst;
436
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1683 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
e341fd5aa996 Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents: 427
diff changeset
1684 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1685 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1686
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1687 static void render_map_mode4(uint32_t line, int32_t col, vdp_context * context)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1688 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1689 uint32_t vscroll = line;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1690 if (col < 24 || !(context->regs[REG_MODE_1] & BIT_VSCRL_LOCK)) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1691 vscroll += context->regs[REG_Y_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1692 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1693 if (vscroll > 223) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1694 vscroll -= 224;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1695 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1696 vscroll &= 7;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1697 if (context->col_1 & 0x400) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1698 //vflip
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1699 vscroll = 7 - vscroll;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1700 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1701
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1702 uint32_t pixels = planar_to_chunky[context->fetch_tmp[0]] << 1;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1703 pixels |= planar_to_chunky[context->fetch_tmp[1]];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1704
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1705 uint32_t address = mode4_address_map[((context->col_1 & 0x1FF) * 32) + vscroll * 4 + 2];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1706 pixels |= planar_to_chunky[context->vdpmem[address]] << 3;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1707 pixels |= planar_to_chunky[context->vdpmem[address+1]] << 2;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1708
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1709 int i, i_inc, i_limit;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1710 if (context->col_1 & 0x200) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1711 //hflip
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1712 i = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1713 i_inc = 4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1714 i_limit = 32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1715 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1716 i = 28;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1717 i_inc = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1718 i_limit = -4;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1719 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1720 uint8_t pal_priority = (context->col_1 >> 7 & 0x10) | (context->col_1 >> 6 & 0x40);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1721 for (uint8_t *dst = context->tmp_buf_a + context->buf_a_off; i != i_limit; i += i_inc, dst++)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1722 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1723 *dst = (pixels >> i & 0xF) | pal_priority;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1724 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1725 context->buf_a_off = (context->buf_a_off + 8) & 15;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1726
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1727 uint8_t *dst = context->compositebuf + col * 8 + BORDER_LEFT;
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1728 uint8_t *debug_dst = context->layer_debug_buf + col * 8 + BORDER_LEFT;
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
1729 if (context->state == PREPARING) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1730 memset(dst, 0, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1731 memset(debug_dst, DBG_SRC_BG, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1732 context->done_composite = dst + 8;
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
1733 return;
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
1734 }
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1735
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1736 if (col || !(context->regs[REG_MODE_1] & BIT_COL0_MASK)) {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1737 uint8_t *sprite_src = context->linebuf + col * 8;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1738 if (context->regs[REG_MODE_1] & BIT_SPRITE_8PX) {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1739 sprite_src += 8;
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1740 }
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1741 for (int i = 0; i < 8; i++, sprite_src++)
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1742 {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1743 uint8_t *bg_src = context->tmp_buf_a + ((8 + i + col * 8 - (context->hscroll_a & 0x7)) & 15);
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1744 if ((*bg_src & 0x4F) > 0x40 || !*sprite_src) {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1745 //background plane has priority and is opaque or sprite layer is transparent
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1746 uint8_t pixel = *bg_src & 0x1F;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1747 *(dst++) = pixel + MODE4_OFFSET;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1748 *(debug_dst++) = pixel ? DBG_SRC_A : DBG_SRC_BG;
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1749 } else {
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1750 //sprite layer is opaque and not covered by high priority BG pixels
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1751 *(dst++) = (*sprite_src | 0x10) + MODE4_OFFSET;
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1752 *(debug_dst++) = DBG_SRC_S;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1753 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1754 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1755 context->done_composite = dst;
1643
6909c5d0bbb5 Removed old VDP debug functionality
Michael Pavone <pavone@retrodev.com>
parents: 1642
diff changeset
1756 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1757 memset(dst, 0, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1758 memset(dst, DBG_SRC_BG, 8);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
1759 context->done_composite = dst + 8;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1760 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1761 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
1762
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1763 static uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19};
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1764
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
1765 static void vdp_advance_line(vdp_context *context)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1766 {
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1767 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1768 static uint32_t last_line = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1769 if (last_line != 0xFFFFFFFF) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1770 uint32_t diff = context->cycles - last_line;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1771 if (diff != MCLKS_LINE) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1772 printf("Line %d took %d cycles\n", context->vcounter, diff);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1773 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1774 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1775 last_line = context->cycles;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
1776 #endif
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1777 uint16_t jump_start, jump_end;
1156
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1778 uint8_t is_mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1779 if (is_mode_5) {
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
1780 if (context->flags2 & FLAG2_REGION_PAL) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1781 if (context->regs[REG_MODE_2] & BIT_PAL) {
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1782 jump_start = 0x10B;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1783 jump_end = 0x1D2;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1784 } else {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1785 jump_start = 0x103;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1786 jump_end = 0x1CA;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1787 }
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1788 } else if (context->regs[REG_MODE_2] & BIT_PAL) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1789 jump_start = 0x100;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1790 jump_end = 0x1FA;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1791 } else {
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1792 jump_start = 0xEB;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1793 jump_end = 0x1E5;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1794 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1795 } else {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1796 jump_start = 0xDB;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1797 jump_end = 0x1D5;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1798 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1799
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1800 if (context->enabled_debuggers & (1 << VDP_DEBUG_CRAM | 1 << VDP_DEBUG_COMPOSITE)) {
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1801 uint32_t line = context->vcounter;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1802 if (line >= jump_end) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1803 line -= jump_end - jump_start;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1804 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1805 uint32_t total_lines = (context->flags2 & FLAG2_REGION_PAL) ? 313 : 262;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1806
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1807 if (total_lines - line <= context->border_top) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1808 line -= total_lines - context->border_top;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1809 } else {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1810 line += context->border_top;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1811 }
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1812 if (context->enabled_debuggers & (1 << VDP_DEBUG_CRAM)) {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1813 uint32_t *fb = context->debug_fbs[VDP_DEBUG_CRAM] + context->debug_fb_pitch[VDP_DEBUG_CRAM] * line / sizeof(uint32_t);
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1814 for (int i = 0; i < 64; i++)
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1815 {
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1816 for (int x = 0; x < 8; x++)
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1817 {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1818 *(fb++) = context->colors[i];
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1819 }
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1820 }
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1821 }
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1822 if (
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1823 context->enabled_debuggers & (1 << VDP_DEBUG_COMPOSITE)
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1824 && line < (context->inactive_start + context->border_bot + context->border_top)
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1825 ) {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1826 uint32_t *fb = context->debug_fbs[VDP_DEBUG_COMPOSITE] + context->debug_fb_pitch[VDP_DEBUG_COMPOSITE] * line / sizeof(uint32_t);
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1827 for (int i = 0; i < LINEBUF_SIZE; i++)
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1828 {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1829 *(fb++) = context->debugcolors[context->layer_debug_buf[i]];
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1830 }
1299
da1ffc4026c4 Fix latching of V32 mode bit
Michael Pavone <pavone@retrodev.com>
parents: 1290
diff changeset
1831 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
1832 }
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
1833
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1834 context->vcounter++;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1835 if (context->vcounter == jump_start) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1836 context->vcounter = jump_end;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1837 } else {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1838 context->vcounter &= 0x1FF;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1839 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1840 if (context->state == PREPARING) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1841 context->state = ACTIVE;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1842 }
1377
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
1843 if (context->vcounter == 0x1FF) {
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
1844 context->flags2 &= ~FLAG2_PAUSE;
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
1845 }
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1846
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
1847 if (context->state != ACTIVE) {
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1848 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1849 } else if (context->hint_counter) {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1850 context->hint_counter--;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1851 } else {
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1852 context->flags2 |= FLAG2_HINT_PENDING;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1853 context->pending_hint_start = context->cycles;
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1854 context->hint_counter = context->regs[REG_HINT];
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1855 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1856 }
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
1857
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1858 static void vdp_update_per_frame_debug(vdp_context *context)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1859 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1860 if (context->enabled_debuggers & (1 << VDP_DEBUG_PLANE)) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1861 uint32_t pitch;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1862 uint32_t *fb = render_get_framebuffer(context->debug_fb_indices[VDP_DEBUG_PLANE], &pitch);
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1863 uint16_t hscroll_mask;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1864 uint16_t v_mul;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1865 uint16_t vscroll_mask = 0x1F | (context->regs[REG_SCROLL] & 0x30) << 1;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1866 switch(context->regs[REG_SCROLL] & 0x3)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1867 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1868 case 0:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1869 hscroll_mask = 0x1F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1870 v_mul = 64;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1871 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1872 case 0x1:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1873 hscroll_mask = 0x3F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1874 v_mul = 128;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1875 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1876 case 0x2:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1877 //TODO: Verify this behavior
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1878 hscroll_mask = 0x1F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1879 v_mul = 0;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1880 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1881 case 0x3:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1882 hscroll_mask = 0x7F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1883 v_mul = 256;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1884 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1885 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1886 uint16_t table_address;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1887 switch(context->debug_modes[VDP_DEBUG_PLANE] % 3)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1888 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1889 case 0:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1890 table_address = context->regs[REG_SCROLL_A] << 10 & 0xE000;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1891 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1892 case 1:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1893 table_address = context->regs[REG_SCROLL_B] << 13 & 0xE000;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1894 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1895 case 2:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1896 table_address = context->regs[REG_WINDOW] << 10;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1897 if (context->regs[REG_MODE_4] & BIT_H40) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1898 table_address &= 0xF000;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1899 v_mul = 128;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1900 hscroll_mask = 0x3F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1901 } else {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1902 table_address &= 0xF800;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1903 v_mul = 64;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1904 hscroll_mask = 0x1F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1905 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1906 vscroll_mask = 0x1F;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1907 break;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1908 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1909 uint32_t bg_color = context->colors[context->regs[REG_BG_COLOR & 0x3F]];
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1910 for (uint16_t row = 0; row < 128; row++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1911 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1912 uint16_t row_address = table_address + (row & vscroll_mask) * v_mul;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1913 for (uint16_t col = 0; col < 128; col++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1914 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1915 uint16_t address = row_address + (col & hscroll_mask) * 2;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1916 //pccv hnnn nnnn nnnn
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1917 //
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1918 uint16_t entry = context->vdpmem[address] << 8 | context->vdpmem[address + 1];
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1919 uint8_t pal = entry >> 9 & 0x30;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1920
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1921 uint32_t *dst = fb + (row * pitch * 8 / sizeof(uint32_t)) + col * 8;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1922 address = (entry & 0x7FF) * 32;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1923 int y_diff = 4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1924 if (entry & 0x1000) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1925 y_diff = -4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1926 address += 7 * 4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1927 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1928 int x_diff = 1;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1929 if (entry & 0x800) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1930 x_diff = -1;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1931 address += 3;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1932 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1933 for (int y = 0; y < 8; y++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1934 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1935 uint16_t trow_address = address;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1936 uint32_t *row_dst = dst;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1937 for (int x = 0; x < 4; x++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1938 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1939 uint8_t byte = context->vdpmem[trow_address];
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1940 trow_address += x_diff;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1941 uint8_t left, right;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1942 if (x_diff > 0) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1943 left = byte >> 4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1944 right = byte & 0xF;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1945 } else {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1946 left = byte & 0xF;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1947 right = byte >> 4;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1948 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1949 *(row_dst++) = left ? context->colors[left|pal] : bg_color;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1950 *(row_dst++) = right ? context->colors[right|pal] : bg_color;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1951 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1952 address += y_diff;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1953 dst += pitch / sizeof(uint32_t);
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1954 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1955 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1956 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1957 render_framebuffer_updated(context->debug_fb_indices[VDP_DEBUG_PLANE], 1024);
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
1958 }
1634
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1959
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1960 if (context->enabled_debuggers & (1 << VDP_DEBUG_VRAM)) {
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1961 uint32_t pitch;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1962 uint32_t *fb = render_get_framebuffer(context->debug_fb_indices[VDP_DEBUG_VRAM], &pitch);
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1963
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1964 uint8_t pal = (context->debug_modes[VDP_DEBUG_VRAM] % 4) << 4;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1965 for (int y = 0; y < 512; y++)
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1966 {
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1967 uint32_t *line = fb + y * pitch / sizeof(uint32_t);
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1968 int row = y >> 4;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1969 int yoff = y >> 1 & 7;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1970 for (int col = 0; col < 64; col++)
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1971 {
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1972 uint16_t address = (row * 64 + col) * 32 + yoff * 4;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1973 for (int x = 0; x < 4; x++)
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1974 {
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1975 uint8_t byte = context->vdpmem[address++];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1976 uint8_t left = byte >> 4 | pal;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1977 uint8_t right = byte & 0xF | pal;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1978 *(line++) = context->colors[left];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1979 *(line++) = context->colors[left];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1980 *(line++) = context->colors[right];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1981 *(line++) = context->colors[right];
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1982 }
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1983 }
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1984 }
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1985
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1986 render_framebuffer_updated(context->debug_fb_indices[VDP_DEBUG_VRAM], 1024);
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
1987 }
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1988
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1989 if (context->enabled_debuggers & (1 << VDP_DEBUG_CRAM)) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1990 uint32_t starting_line = 512 - 32*4;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1991 uint32_t *line = context->debug_fbs[VDP_DEBUG_CRAM]
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1992 + context->debug_fb_pitch[VDP_DEBUG_CRAM] * starting_line / sizeof(uint32_t);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1993 for (int pal = 0; pal < 4; pal ++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1994 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1995 uint32_t *cur;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1996 for (int y = 0; y < 31; y++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1997 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1998 cur = line;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
1999 for (int offset = 0; offset < 16; offset++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2000 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2001 for (int x = 0; x < 31; x++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2002 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2003 *(cur++) = context->colors[pal * 16 + offset];
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2004 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2005 *(cur++) = 0xFF000000;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2006 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2007 line += context->debug_fb_pitch[VDP_DEBUG_CRAM] / sizeof(uint32_t);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2008 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2009 cur = line;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2010 for (int x = 0; x < 512; x++)
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2011 {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2012 *(cur++) = 0xFF000000;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2013 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2014 line += context->debug_fb_pitch[VDP_DEBUG_CRAM] / sizeof(uint32_t);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2015 }
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2016 render_framebuffer_updated(context->debug_fb_indices[VDP_DEBUG_CRAM], 512);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2017 context->debug_fbs[VDP_DEBUG_CRAM] = render_get_framebuffer(context->debug_fb_indices[VDP_DEBUG_CRAM], &context->debug_fb_pitch[VDP_DEBUG_CRAM]);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
2018 }
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
2019 if (context->enabled_debuggers & (1 << VDP_DEBUG_COMPOSITE)) {
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
2020 render_framebuffer_updated(context->debug_fb_indices[VDP_DEBUG_COMPOSITE], LINEBUF_SIZE);
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
2021 context->debug_fbs[VDP_DEBUG_COMPOSITE] = render_get_framebuffer(context->debug_fb_indices[VDP_DEBUG_COMPOSITE], &context->debug_fb_pitch[VDP_DEBUG_COMPOSITE]);
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
2022 }
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
2023 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
2024
1629
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2025 void vdp_force_update_framebuffer(vdp_context *context)
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2026 {
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2027 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL)
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2028 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2029 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28;
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2030
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2031 uint16_t to_fill = lines_max - context->output_lines;
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2032 memset(
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2033 ((char *)context->fb) + context->output_pitch * context->output_lines,
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2034 0,
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2035 to_fill * context->output_pitch
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2036 );
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2037 render_framebuffer_updated(context->cur_buffer, context->h40_lines > context->output_lines / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2038 context->fb = render_get_framebuffer(context->cur_buffer, &context->output_pitch);
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
2039 vdp_update_per_frame_debug(context);
1629
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2040 }
079e5b9d59ce Forcefully update the display when entering the 68K debugger so you can see it update in realtime as you step through the code
Michael Pavone <pavone@retrodev.com>
parents: 1628
diff changeset
2041
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2042 static void advance_output_line(vdp_context *context)
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2043 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2044 if (headless) {
1168
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
2045 if (context->vcounter == context->inactive_start) {
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
2046 context->frame++;
fa73a77ddf92 Fix benchmark mode
Michael Pavone <pavone@retrodev.com>
parents: 1167
diff changeset
2047 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2048 context->vcounter &= 0x1FF;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2049 } else {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2050 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2051 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2052 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2053
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2054 if (context->output_lines == lines_max) {
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2055 render_framebuffer_updated(context->cur_buffer, context->h40_lines > (context->inactive_start + context->border_top) / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2056 context->cur_buffer = context->flags2 & FLAG2_EVEN_FIELD ? FRAMEBUFFER_EVEN : FRAMEBUFFER_ODD;
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2057 context->fb = render_get_framebuffer(context->cur_buffer, &context->output_pitch);
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
2058 vdp_update_per_frame_debug(context);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2059 context->h40_lines = 0;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2060 context->frame++;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2061 context->output_lines = 0;
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2062 }
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2063 uint32_t output_line = context->vcounter;
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2064 if (!(context->regs[REG_MODE_2] & BIT_MODE_5)) {
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2065 //vcounter increment occurs much later in Mode 4
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2066 output_line++;
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2067 }
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2068 if (output_line < context->inactive_start + context->border_bot && context->output_lines > 0) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2069 output_line = context->output_lines++;//context->border_top + context->vcounter;
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2070 } else if (output_line >= 0x200 - context->border_top) {
1385
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2071 if (output_line == 0x200 - context->border_top) {
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2072 //We're at the top of the display, force context->output_lines to be zero to avoid
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2073 //potential screen rolling if the mode is changed at an inopportune time
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2074 context->output_lines = 0;
1eded4f19910 Prevent emulated screen from "rolling" when the vertical resolution is changed at an inopportune time
Michael Pavone <pavone@retrodev.com>
parents: 1380
diff changeset
2075 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2076 output_line = context->output_lines++;//context->vcounter - (0x200 - context->border_top);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2077 } else {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2078 output_line = INVALID_LINE;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2079 }
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2080 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * output_line);
1271
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2081 #ifdef DEBUG_FB_FILL
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2082 for (int i = 0; i < LINEBUF_SIZE; i++)
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2083 {
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2084 context->output[i] = 0xFFFF00FF;
c865ee5478bc Fix some of the framebuffer fill holes introduced by horizontal border changes
Michael Pavone <pavone@retrodev.com>
parents: 1270
diff changeset
2085 }
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2086 #endif
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2087 if (output_line != INVALID_LINE && (context->regs[REG_MODE_4] & BIT_H40)) {
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
2088 context->h40_lines++;
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
2089 }
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
2090 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2091 }
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2092
1401
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2093 void vdp_release_framebuffer(vdp_context *context)
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2094 {
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2095 render_framebuffer_updated(context->cur_buffer, context->h40_lines > (context->inactive_start + context->border_top) / 2 ? LINEBUF_SIZE : (256+HORIZ_BORDER));
1401
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2096 context->output = context->fb = NULL;
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2097 }
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2098
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2099 void vdp_reacquire_framebuffer(vdp_context *context)
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2100 {
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
2101 context->fb = render_get_framebuffer(context->cur_buffer, &context->output_pitch);
1401
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2102 uint16_t lines_max = (context->flags2 & FLAG2_REGION_PAL)
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2103 ? 240 + BORDER_TOP_V30_PAL + BORDER_BOT_V30_PAL
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2104 : 224 + BORDER_TOP_V28 + BORDER_BOT_V28;
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2105 if (context->output_lines <= lines_max && context->output_lines > 0) {
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2106 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * (context->output_lines - 1));
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2107 } else {
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2108 context->output = (uint32_t *)(((char *)context->fb) + context->output_pitch * INVALID_LINE);
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2109 }
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2110 }
b56c8c51ca5d Properly release and reacquire framebuffer pointer when switching contexts. Hopefully fixes the LOCKRECT issue some people are seeing with the SDL 2 fallback renderer
Michael Pavone <pavone@retrodev.com>
parents: 1385
diff changeset
2111
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2112 static void render_border_garbage(vdp_context *context, uint32_t address, uint8_t *buf, uint8_t buf_off, uint16_t col)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2113 {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2114 uint8_t base = col >> 9 & 0x30;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2115 for (int i = 0; i < 4; i++, address++)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2116 {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2117 uint8_t byte = context->vdpmem[address & 0xFFFF];
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2118 buf[(buf_off++) & SCROLL_BUFFER_MASK] = base | byte >> 4;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2119 buf[(buf_off++) & SCROLL_BUFFER_MASK] = base | byte & 0xF;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2120 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2121 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2122
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2123 static void draw_right_border(vdp_context *context)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2124 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2125 uint8_t *dst = context->compositebuf + BORDER_LEFT + ((context->regs[REG_MODE_4] & BIT_H40) ? 320 : 256);
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2126 uint8_t pixel = context->regs[REG_BG_COLOR] & 0x3F;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2127 if ((context->test_port & TEST_BIT_DISABLE) != 0) {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2128 pixel = 0x3F;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2129 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2130 uint8_t test_layer = context->test_port >> 7 & 3;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2131 if (test_layer) {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2132 switch(test_layer)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2133 {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2134 case 1:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2135 memset(dst, 0, BORDER_RIGHT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2136 dst += BORDER_RIGHT;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2137 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2138 case 2: {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2139 //plane A
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2140 //TODO: Deal with Window layer
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2141 int i;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2142 i = 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2143 uint8_t buf_off = context->buf_a_off - (context->hscroll_a & 0xF);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2144 //uint8_t *src = context->tmp_buf_a + ((context->buf_a_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_a & 0xF))) & SCROLL_BUFFER_MASK);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2145 for (; i < BORDER_RIGHT; buf_off++, i++, dst++)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2146 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2147 *dst = context->tmp_buf_a[buf_off & SCROLL_BUFFER_MASK] & 0x3F;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2148 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2149 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2150 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2151 case 3: {
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2152 //plane B
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2153 int i;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2154 i = 0;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2155 uint8_t buf_off = context->buf_b_off - (context->hscroll_b & 0xF);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2156 //uint8_t *src = context->tmp_buf_b + ((context->buf_b_off + (i ? 0 : (16 - BORDER_LEFT) - (context->hscroll_b & 0xF))) & SCROLL_BUFFER_MASK);
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2157 for (; i < BORDER_RIGHT; buf_off++, i++, dst++)
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2158 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2159 *dst = context->tmp_buf_b[buf_off & SCROLL_BUFFER_MASK] & 0x3F;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2160 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2161 break;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2162 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2163 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2164 } else {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2165 memset(dst, 0, BORDER_RIGHT);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2166 dst += BORDER_RIGHT;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2167 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2168 context->done_composite = dst;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2169 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2170 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2171 }
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2172
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2173 #define CHECK_ONLY if (context->cycles >= target_cycles) { return; }
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
2174 #define CHECK_LIMIT if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } context->hslot++; context->cycles += slot_cycles; CHECK_ONLY
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2175 #define OUTPUT_PIXEL(slot) if ((slot) >= BG_START_SLOT) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2176 uint8_t *src = context->compositebuf + ((slot) - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2177 uint32_t *dst = context->output + ((slot) - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2178 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2179 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2180 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2181 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2182 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2183 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2184 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2185 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2186 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2187 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2188 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2189
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2190 #define OUTPUT_PIXEL_H40(slot) if (slot <= (BG_START_SLOT + LINEBUF_SIZE/2)) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2191 uint8_t *src = context->compositebuf + (slot - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2192 uint32_t *dst = context->output + (slot - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2193 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2194 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2195 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2196 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2197 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2198 if (slot != (BG_START_SLOT + LINEBUF_SIZE/2)) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2199 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2200 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2201 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2202 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2203 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2204 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2205 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2206
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2207 #define OUTPUT_PIXEL_H32(slot) if (slot <= (BG_START_SLOT + (256+HORIZ_BORDER)/2)) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2208 uint8_t *src = context->compositebuf + (slot - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2209 uint32_t *dst = context->output + (slot - BG_START_SLOT) *2;\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2210 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2211 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2212 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2213 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2214 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2215 if (slot != (BG_START_SLOT + (256+HORIZ_BORDER)/2)) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2216 if ((*src & 0x3F) | test_layer) {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2217 *(dst++) = context->colors[*(src++)];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2218 } else {\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2219 *(dst++) = context->colors[(*(src++) & 0xC0) | bgindex];\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2220 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2221 }\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2222 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2223
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2224 #define COLUMN_RENDER_BLOCK(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2225 case startcyc:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2226 OUTPUT_PIXEL(startcyc)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2227 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2228 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2229 case ((startcyc+1)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2230 OUTPUT_PIXEL((startcyc+1)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2231 external_slot(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2232 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2233 case ((startcyc+2)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2234 OUTPUT_PIXEL((startcyc+2)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2235 render_map_1(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2236 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2237 case ((startcyc+3)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2238 OUTPUT_PIXEL((startcyc+3)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2239 render_map_2(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2240 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2241 case ((startcyc+4)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2242 OUTPUT_PIXEL((startcyc+4)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2243 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2244 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2245 case ((startcyc+5)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2246 OUTPUT_PIXEL((startcyc+5)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2247 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2248 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2249 case ((startcyc+6)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2250 OUTPUT_PIXEL((startcyc+6)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2251 render_map_3(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2252 CHECK_LIMIT\
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2253 case ((startcyc+7)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2254 OUTPUT_PIXEL((startcyc+7)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2255 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2256 CHECK_LIMIT
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2257
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2258 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2259 case startcyc:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2260 OUTPUT_PIXEL(startcyc)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2261 read_map_scroll_a(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2262 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2263 case (startcyc+1):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2264 /* refresh, so don't run dma src */\
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2265 OUTPUT_PIXEL((startcyc+1)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2266 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2267 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2268 CHECK_ONLY\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2269 case (startcyc+2):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2270 OUTPUT_PIXEL((startcyc+2)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2271 render_map_1(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2272 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2273 case (startcyc+3):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2274 OUTPUT_PIXEL((startcyc+3)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2275 render_map_2(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2276 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2277 case (startcyc+4):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2278 OUTPUT_PIXEL((startcyc+4)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2279 read_map_scroll_b(column, context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2280 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2281 case (startcyc+5):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2282 OUTPUT_PIXEL((startcyc+5)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2283 read_sprite_x(context->vcounter, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2284 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2285 case (startcyc+6):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2286 OUTPUT_PIXEL((startcyc+6)&0xFF)\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2287 render_map_3(context);\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2288 CHECK_LIMIT\
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2289 case (startcyc+7):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2290 OUTPUT_PIXEL((startcyc+7)&0xFF)\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2291 render_map_output(context->vcounter, column, context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2292 CHECK_LIMIT
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2293
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2294 #define COLUMN_RENDER_BLOCK_MODE4(column, startcyc) \
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2295 case startcyc:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2296 OUTPUT_PIXEL(startcyc)\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2297 read_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2298 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2299 case ((startcyc+1)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2300 OUTPUT_PIXEL((startcyc+1)&0xFF)\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2301 if (column & 3) {\
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2302 scan_sprite_table_mode4(context);\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2303 } else {\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2304 external_slot(context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2305 }\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2306 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2307 case ((startcyc+2)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2308 OUTPUT_PIXEL((startcyc+2)&0xFF)\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2309 fetch_map_mode4(column, context->vcounter, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2310 CHECK_LIMIT\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2311 case ((startcyc+3)&0xFF):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2312 OUTPUT_PIXEL((startcyc+3)&0xFF)\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2313 render_map_mode4(context->vcounter, column, context);\
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2314 CHECK_LIMIT
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2315
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2316 #define CHECK_LIMIT_HSYNC(slot) \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2317 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2318 if (slot >= HSYNC_SLOT_H40 && slot < HSYNC_END_H40) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2319 context->cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2320 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2321 context->cycles += slot_cycles;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2322 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2323 if (slot == 182) {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2324 context->hslot = 229;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2325 } else {\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2326 context->hslot++;\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2327 }\
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2328 CHECK_ONLY
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
2329
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2330 #define SPRITE_RENDER_H40(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2331 case slot:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2332 OUTPUT_PIXEL_H40(slot)\
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2333 if ((slot) == BG_START_SLOT + LINEBUF_SIZE/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2334 advance_output_line(context);\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2335 }\
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2336 if (slot == 168 || slot == 247 || slot == 248) {\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2337 render_border_garbage(\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2338 context,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2339 context->sprite_draw_list[context->cur_slot].address,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2340 context->tmp_buf_b,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2341 context->buf_b_off + (slot == 247 ? 0 : 8),\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2342 slot == 247 ? context->col_1 : context->col_2\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2343 );\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2344 if (slot == 248) {\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2345 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2346 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2347 }\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2348 } else if (slot == 243) {\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2349 render_border_garbage(\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2350 context,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2351 context->sprite_draw_list[context->cur_slot].address,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2352 context->tmp_buf_a,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2353 context->buf_a_off,\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2354 context->col_1\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2355 );\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2356 } else if (slot == 169) {\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2357 draw_right_border(context);\
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2358 }\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2359 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2360 scan_sprite_table(context->vcounter, context);\
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2361 CHECK_LIMIT_HSYNC(slot)
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 822
diff changeset
2362
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2363 //Note that the line advancement check will fail if BG_START_SLOT is > 6
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2364 //as we're bumping up against the hcounter jump
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2365 #define SPRITE_RENDER_H32(slot) \
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2366 case slot:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2367 OUTPUT_PIXEL_H32(slot)\
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2368 if ((slot) == BG_START_SLOT + (256+HORIZ_BORDER)/2) {\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2369 advance_output_line(context);\
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
2370 }\
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2371 if (slot == 136 || slot == 247 || slot == 248) {\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2372 render_border_garbage(\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2373 context,\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2374 context->sprite_draw_list[context->cur_slot].address,\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2375 context->tmp_buf_b,\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2376 context->buf_b_off + (slot == 247 ? 0 : 8),\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2377 slot == 247 ? context->col_1 : context->col_2\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2378 );\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2379 if (slot == 248) {\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2380 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2381 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK;\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2382 }\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2383 } else if (slot == 137) {\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2384 draw_right_border(context);\
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2385 }\
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2386 render_sprite_cells( context);\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2387 scan_sprite_table(context->vcounter, context);\
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
2388 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2389 if (slot == 147) {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2390 context->hslot = 233;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2391 } else {\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2392 context->hslot++;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2393 }\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2394 context->cycles += slot_cycles;\
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2395 CHECK_ONLY
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2396
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2397 #define MODE4_CHECK_SLOT_LINE(slot) \
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2398 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); } \
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2399 if ((slot) == BG_START_SLOT + (256+HORIZ_BORDER)/2) {\
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2400 advance_output_line(context);\
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2401 }\
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2402 if ((slot) == 147) {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2403 context->hslot = 233;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2404 } else {\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2405 context->hslot++;\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2406 }\
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2407 context->cycles += slot_cycles;\
1163
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2408 if ((slot+1) == LINE_CHANGE_MODE4) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2409 vdp_advance_line(context);\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2410 if (context->vcounter == 192) {\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2411 return;\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2412 }\
b251899f2b97 Fix disagreement on line change location between vdp_h32_mode4 and vdp_run_context that was causing the first line to be garbage in some cases
Michael Pavone <pavone@retrodev.com>
parents: 1161
diff changeset
2413 }\
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2414 CHECK_ONLY
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2415
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2416 #define CALC_SLOT(slot, increment) ((slot+increment) > 147 && (slot+increment) < 233 ? (slot+increment-148+233): (slot+increment))
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2417
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2418 #define SPRITE_RENDER_H32_MODE4(slot) \
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2419 case slot:\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2420 OUTPUT_PIXEL_H32(slot)\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2421 read_sprite_x_mode4(context);\
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2422 MODE4_CHECK_SLOT_LINE(slot)\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2423 case CALC_SLOT(slot, 1):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2424 OUTPUT_PIXEL(CALC_SLOT(slot, 1))\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2425 read_sprite_x_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2426 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot,1))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2427 case CALC_SLOT(slot, 2):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2428 OUTPUT_PIXEL(CALC_SLOT(slot, 2))\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2429 fetch_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2430 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 2))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2431 case CALC_SLOT(slot, 3):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2432 OUTPUT_PIXEL(CALC_SLOT(slot, 3))\
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2433 render_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2434 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 3))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2435 case CALC_SLOT(slot, 4):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2436 OUTPUT_PIXEL(CALC_SLOT(slot, 4))\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2437 fetch_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2438 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 4))\
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2439 case CALC_SLOT(slot, 5):\
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2440 OUTPUT_PIXEL(CALC_SLOT(slot, 5))\
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2441 render_sprite_cells_mode4(context);\
1161
c2210d586950 A bunch of Mode 4 fixes
Michael Pavone <pavone@retrodev.com>
parents: 1160
diff changeset
2442 MODE4_CHECK_SLOT_LINE(CALC_SLOT(slot, 5))
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2443
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
2444 static void vdp_h40(vdp_context * context, uint32_t target_cycles)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2445 {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2446 uint16_t address;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2447 uint32_t mask;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2448 uint32_t const slot_cycles = MCLKS_SLOT_H40;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2449 uint8_t bgindex = context->regs[REG_BG_COLOR] & 0x3F;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2450 uint8_t test_layer = context->test_port >> 7 & 3;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2451 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2452 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2453 for (;;)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2454 {
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2455 case 165:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2456 OUTPUT_PIXEL(165)
1432
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2457 if (!(context->regs[REG_MODE_3] & BIT_VSCROLL)) {
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2458 //TODO: Develop some tests on hardware to see when vscroll latch actually happens for full plane mode
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2459 //See note in vdp_h32 for why this was originally moved out of read_map_scroll
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2460 //Skitchin' has a similar problem, but uses H40 mode. It seems to be able to hit the extern slot at 232
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2461 //pretty consistently
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2462 context->vscroll_latch[0] = context->vsram[0];
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2463 context->vscroll_latch[1] = context->vsram[1];
5e7e6d9b79ff Move vscroll latch further forward in H40 mode. Fixes a minor graphical glitch in Skitchin. Needs a proper test ROM to verify exact latch position
Michael Pavone <pavone@retrodev.com>
parents: 1431
diff changeset
2464 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2465 if (context->state == PREPARING) {
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2466 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2467 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2468 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2469 }
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2470 CHECK_LIMIT
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2471 case 166:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2472 OUTPUT_PIXEL(166)
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2473 if (context->state == PREPARING) {
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2474 external_slot(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2475 } else {
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2476 render_sprite_cells(context);
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2477 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2478 if (context->vcounter == context->inactive_start) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2479 context->hslot++;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2480 context->cycles += slot_cycles;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2481 return;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2482 }
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2483 CHECK_LIMIT
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2484 //sprite attribute table scan starts
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2485 case 167:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2486 OUTPUT_PIXEL(167)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2487 context->sprite_index = 0x80;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2488 context->slot_counter = 0;
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2489 render_border_garbage(
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2490 context,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2491 context->sprite_draw_list[context->cur_slot].address,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2492 context->tmp_buf_b, context->buf_b_off,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2493 context->col_1
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2494 );
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2495 render_sprite_cells(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2496 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2497 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2498 SPRITE_RENDER_H40(168)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2499 SPRITE_RENDER_H40(169)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2500 SPRITE_RENDER_H40(170)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2501 SPRITE_RENDER_H40(171)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2502 SPRITE_RENDER_H40(172)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2503 SPRITE_RENDER_H40(173)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2504 SPRITE_RENDER_H40(174)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2505 SPRITE_RENDER_H40(175)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2506 SPRITE_RENDER_H40(176)
1365
6dd2c3edd0b5 Add a bit of a hack to HINT start cycle to give correct values in my test ROM and further improve prevelance of CRAM dot noise in Outrunners and OD2
Michael Pavone <pavone@retrodev.com>
parents: 1362
diff changeset
2507 SPRITE_RENDER_H40(177)//End of border?
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2508 SPRITE_RENDER_H40(178)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2509 SPRITE_RENDER_H40(179)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2510 SPRITE_RENDER_H40(180)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2511 SPRITE_RENDER_H40(181)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2512 SPRITE_RENDER_H40(182)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2513 SPRITE_RENDER_H40(229)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2514 //!HSYNC asserted
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2515 SPRITE_RENDER_H40(230)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2516 SPRITE_RENDER_H40(231)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2517 case 232:
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2518 external_slot(context);
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2519 CHECK_LIMIT_HSYNC(232)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2520 SPRITE_RENDER_H40(233)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2521 SPRITE_RENDER_H40(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2522 SPRITE_RENDER_H40(235)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2523 SPRITE_RENDER_H40(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2524 SPRITE_RENDER_H40(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2525 SPRITE_RENDER_H40(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2526 SPRITE_RENDER_H40(239)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2527 SPRITE_RENDER_H40(240)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2528 SPRITE_RENDER_H40(241)
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2529 SPRITE_RENDER_H40(242)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2530 SPRITE_RENDER_H40(243) //provides "garbage" for border when plane A selected
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2531 case 244:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2532 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2533 mask = 0;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2534 if (context->regs[REG_MODE_3] & 0x2) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2535 mask |= 0xF8;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2536 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2537 if (context->regs[REG_MODE_3] & 0x1) {
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2538 mask |= 0x7;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2539 }
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2540 render_border_garbage(context, address, context->tmp_buf_a, context->buf_a_off+8, context->col_2);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2541 address += (context->vcounter & mask) * 4;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2542 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2543 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2544 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
924
1b86268a4cb3 Change the sentinel value for the hslot parameter of run_dma_src to something that is not a valid slot number and actually use it for calls during the active display period
Michael Pavone <pavone@retrodev.com>
parents: 923
diff changeset
2545 if (context->flags & FLAG_DMA_RUN) { run_dma_src(context, -1); }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2546 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2547 context->cycles += h40_hsync_cycles[14];
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2548 CHECK_ONLY //provides "garbage" for border when plane A selected
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2549 //!HSYNC high
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2550 SPRITE_RENDER_H40(245)
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2551 SPRITE_RENDER_H40(246)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2552 SPRITE_RENDER_H40(247) //provides "garbage" for border when plane B selected
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2553 SPRITE_RENDER_H40(248) //provides "garbage" for border when plane B selected
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2554 case 249:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2555 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2556 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2557 SPRITE_RENDER_H40(250)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2558 case 251:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2559 render_map_1(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2560 scan_sprite_table(context->vcounter, context);//Just a guess
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2561 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2562 case 252:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2563 render_map_2(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2564 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2565 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2566 case 253:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2567 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2568 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2569 SPRITE_RENDER_H40(254)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2570 case 255:
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2571 render_map_3(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2572 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2573 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2574 case 0:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2575 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2576 scan_sprite_table(context->vcounter, context);//Just a guess
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2577 //seems like the sprite table scan fills a shift register
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2578 //values are FIFO, but unused slots precede used slots
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2579 //so we set cur_slot to slot_counter and let it wrap around to
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2580 //the beginning of the list
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2581 context->cur_slot = context->slot_counter;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2582 context->sprite_draws = MAX_DRAWS;
36
04672c060062 Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents: 35
diff changeset
2583 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2584 CHECK_LIMIT
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2585 COLUMN_RENDER_BLOCK(2, 1)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2586 COLUMN_RENDER_BLOCK(4, 9)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2587 COLUMN_RENDER_BLOCK(6, 17)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2588 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2589 COLUMN_RENDER_BLOCK(10, 33)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2590 COLUMN_RENDER_BLOCK(12, 41)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2591 COLUMN_RENDER_BLOCK(14, 49)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2592 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2593 COLUMN_RENDER_BLOCK(18, 65)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2594 COLUMN_RENDER_BLOCK(20, 73)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2595 COLUMN_RENDER_BLOCK(22, 81)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2596 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2597 COLUMN_RENDER_BLOCK(26, 97)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2598 COLUMN_RENDER_BLOCK(28, 105)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2599 COLUMN_RENDER_BLOCK(30, 113)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2600 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2601 COLUMN_RENDER_BLOCK(34, 129)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2602 COLUMN_RENDER_BLOCK(36, 137)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2603 COLUMN_RENDER_BLOCK(38, 145)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2604 COLUMN_RENDER_BLOCK_REFRESH(40, 153)
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2605 case 161:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2606 OUTPUT_PIXEL(161)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2607 external_slot(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2608 CHECK_LIMIT
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2609 case 162:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2610 OUTPUT_PIXEL(162)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2611 external_slot(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2612 CHECK_LIMIT
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2613 //sprite render to line buffer starts
1157
d5dda22ae6b4 Fix H40 slot mapping to better match old VRAM bus captures and adjust for recent VCounter measurements
Michael Pavone <pavone@retrodev.com>
parents: 1156
diff changeset
2614 case 163:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2615 OUTPUT_PIXEL(163)
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2616 context->cur_slot = MAX_DRAWS-1;
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2617 memset(context->linebuf, 0, LINEBUF_SIZE);
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2618 render_border_garbage(
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2619 context,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2620 context->sprite_draw_list[context->cur_slot].address,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2621 context->tmp_buf_a, context->buf_a_off,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2622 context->col_1
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2623 );
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2624 render_sprite_cells(context);
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2625 CHECK_LIMIT
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2626 case 164:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2627 OUTPUT_PIXEL(164)
1337
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2628 render_border_garbage(
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2629 context,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2630 context->sprite_draw_list[context->cur_slot].address,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2631 context->tmp_buf_a, context->buf_a_off + 8,
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2632 context->col_2
d092c15246a3 Initial stab at horizontal border when VDP test register layer selection is in effect for H40. Extended horizontal borders in Titancade scene and ninja escape scene mostly correct now
Michael Pavone <pavone@retrodev.com>
parents: 1335
diff changeset
2633 );
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2634 render_sprite_cells(context);
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2635 if (context->flags & FLAG_DMA_RUN) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2636 run_dma_src(context, -1);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2637 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2638 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2639 context->cycles += slot_cycles;
922
913a6336ce20 Shift slot number to slot behavior mapping by six slots in H40 mode. This makes the line change slot align with the point at which the display turns on and off at the end of the active display area. Also fixed a regression in which an external slot got accidentally changed into a sprite draw slot
Michael Pavone <pavone@retrodev.com>
parents: 921
diff changeset
2640 vdp_advance_line(context);
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
2641 CHECK_ONLY
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2642 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2643 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2644 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2645 context->cycles += slot_cycles;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2646 return;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2647 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2648 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2649
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
2650 static void vdp_h32(vdp_context * context, uint32_t target_cycles)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2651 {
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2652 uint16_t address;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2653 uint32_t mask;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2654 uint32_t const slot_cycles = MCLKS_SLOT_H32;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2655 uint8_t bgindex = context->regs[REG_BG_COLOR] & 0x3F;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2656 uint8_t test_layer = context->test_port >> 7 & 3;
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2657 switch(context->hslot)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2658 {
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2659 for (;;)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2660 {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2661 case 133:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2662 OUTPUT_PIXEL(133)
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2663 if (context->state == PREPARING) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2664 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2665 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2666 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2667 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2668 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2669 case 134:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2670 OUTPUT_PIXEL(134)
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
2671 if (context->state == PREPARING) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2672 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2673 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2674 render_sprite_cells(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2675 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2676 if (context->vcounter == context->inactive_start) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2677 context->hslot++;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2678 context->cycles += slot_cycles;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2679 return;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2680 }
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2681 CHECK_LIMIT
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2682 //sprite attribute table scan starts
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2683 case 135:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2684 OUTPUT_PIXEL(135)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2685 context->sprite_index = 0x80;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2686 context->slot_counter = 0;
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2687 render_border_garbage(
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2688 context,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2689 context->sprite_draw_list[context->cur_slot].address,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2690 context->tmp_buf_b, context->buf_b_off,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2691 context->col_1
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2692 );
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2693 render_sprite_cells(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2694 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2695 CHECK_LIMIT
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2696 SPRITE_RENDER_H32(136)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2697 SPRITE_RENDER_H32(137)
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2698 SPRITE_RENDER_H32(138)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2699 SPRITE_RENDER_H32(139)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2700 SPRITE_RENDER_H32(140)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2701 SPRITE_RENDER_H32(141)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2702 SPRITE_RENDER_H32(142)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2703 SPRITE_RENDER_H32(143)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2704 SPRITE_RENDER_H32(144)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2705 case 145:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2706 OUTPUT_PIXEL(145)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2707 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2708 CHECK_LIMIT
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2709 SPRITE_RENDER_H32(146)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2710 SPRITE_RENDER_H32(147)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2711 SPRITE_RENDER_H32(233)
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2712 SPRITE_RENDER_H32(234)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2713 SPRITE_RENDER_H32(235)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2714 //HSYNC start
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2715 SPRITE_RENDER_H32(236)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2716 SPRITE_RENDER_H32(237)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2717 SPRITE_RENDER_H32(238)
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2718 SPRITE_RENDER_H32(239)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2719 SPRITE_RENDER_H32(240)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2720 SPRITE_RENDER_H32(241)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2721 SPRITE_RENDER_H32(242)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2722 case 243:
1422
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2723 if (!(context->regs[REG_MODE_3] & BIT_VSCROLL)) {
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2724 //TODO: Develop some tests on hardware to see when vscroll latch actually happens for full plane mode
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2725 //Top Gear 2 has a very efficient HINT routine that can occassionally hit this slot with a VSRAM write
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2726 //Since CRAM-updatnig HINT routines seem to indicate that my HINT latency is perhaps slightly too high
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2727 //the most reasonable explanation is that vscroll is latched before this slot, but tests are needed
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2728 //to confirm that one way or another
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2729 context->vscroll_latch[0] = context->vsram[0];
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2730 context->vscroll_latch[1] = context->vsram[1];
2b34469e3f81 Change where vscroll is latched in full plane mode. Fixes Top Gear 2
Michael Pavone <pavone@retrodev.com>
parents: 1401
diff changeset
2731 }
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2732 external_slot(context);
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2733 //provides "garbage" for border when plane A selected
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2734 render_border_garbage(
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2735 context,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2736 context->sprite_draw_list[context->cur_slot].address,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2737 context->tmp_buf_a,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2738 context->buf_a_off,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2739 context->col_1
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2740 );
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2741 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2742 case 244:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2743 address = (context->regs[REG_HSCROLL] & 0x3F) << 10;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2744 mask = 0;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2745 if (context->regs[REG_MODE_3] & 0x2) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2746 mask |= 0xF8;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2747 }
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2748 if (context->regs[REG_MODE_3] & 0x1) {
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2749 mask |= 0x7;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2750 }
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2751 render_border_garbage(context, address, context->tmp_buf_a, context->buf_a_off+8, context->col_2);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2752 address += (context->vcounter & mask) * 4;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2753 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1];
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2754 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3];
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2755 //printf("%d: HScroll A: %d, HScroll B: %d\n", context->vcounter, context->hscroll_a, context->hscroll_b);
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2756 CHECK_LIMIT //provides "garbage" for border when plane A selected
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2757 SPRITE_RENDER_H32(245)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2758 SPRITE_RENDER_H32(246)
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2759 SPRITE_RENDER_H32(247) //provides "garbage" for border when plane B selected
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2760 SPRITE_RENDER_H32(248) //provides "garbage" for border when plane B selected
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2761 //!HSYNC high
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2762 case 249:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2763 read_map_scroll_a(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2764 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2765 SPRITE_RENDER_H32(250)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2766 case 251:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2767 render_map_1(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2768 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2769 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2770 case 252:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2771 render_map_2(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2772 scan_sprite_table(context->vcounter, context);//Just a guess
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2773 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2774 case 253:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2775 read_map_scroll_b(0, context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2776 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2777 case 254:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2778 render_sprite_cells(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2779 scan_sprite_table(context->vcounter, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2780 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2781 case 255:
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2782 render_map_3(context);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2783 scan_sprite_table(context->vcounter, context);//Just a guess
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2784 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2785 case 0:
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2786 render_map_output(context->vcounter, 0, context);
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2787 scan_sprite_table(context->vcounter, context);//Just a guess
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2788 //reverse context slot counter so it counts the number of sprite slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2789 //filled rather than the number of available slots
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2790 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
2791 context->cur_slot = context->slot_counter;
37
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2792 context->sprite_draws = MAX_DRAWS_H32;
cd59519b26d9 Initial H32 mode support
Mike Pavone <pavone@retrodev.com>
parents: 36
diff changeset
2793 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED);
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2794 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2795 COLUMN_RENDER_BLOCK(2, 1)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2796 COLUMN_RENDER_BLOCK(4, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2797 COLUMN_RENDER_BLOCK(6, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2798 COLUMN_RENDER_BLOCK_REFRESH(8, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2799 COLUMN_RENDER_BLOCK(10, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2800 COLUMN_RENDER_BLOCK(12, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2801 COLUMN_RENDER_BLOCK(14, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2802 COLUMN_RENDER_BLOCK_REFRESH(16, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2803 COLUMN_RENDER_BLOCK(18, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2804 COLUMN_RENDER_BLOCK(20, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2805 COLUMN_RENDER_BLOCK(22, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2806 COLUMN_RENDER_BLOCK_REFRESH(24, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2807 COLUMN_RENDER_BLOCK(26, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2808 COLUMN_RENDER_BLOCK(28, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2809 COLUMN_RENDER_BLOCK(30, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2810 COLUMN_RENDER_BLOCK_REFRESH(32, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2811 case 129:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2812 OUTPUT_PIXEL(129)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2813 external_slot(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2814 CHECK_LIMIT
1269
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2815 case 130: {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2816 OUTPUT_PIXEL(130)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2817 external_slot(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2818 CHECK_LIMIT
1269
ff8e29eeb1ec Render horizontal border in H32 mode as well. Both modes still need some minor work to deal with inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1267
diff changeset
2819 }
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2820 //sprite render to line buffer starts
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2821 case 131:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2822 OUTPUT_PIXEL(131)
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2823 context->cur_slot = MAX_DRAWS_H32-1;
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2824 memset(context->linebuf, 0, LINEBUF_SIZE);
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2825 render_border_garbage(
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2826 context,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2827 context->sprite_draw_list[context->cur_slot].address,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2828 context->tmp_buf_a, context->buf_a_off,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2829 context->col_1
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2830 );
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2831 render_sprite_cells(context);
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2832 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2833 case 132:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2834 OUTPUT_PIXEL(132)
1378
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2835 render_border_garbage(
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2836 context,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2837 context->sprite_draw_list[context->cur_slot].address,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2838 context->tmp_buf_a, context->buf_a_off + 8,
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2839 context->col_2
71c8b97eb962 Get H32 in sync with H40 with regards to borders and test register support. Minor cleanup to H40 border rendering
Michael Pavone <pavone@retrodev.com>
parents: 1377
diff changeset
2840 );
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2841 render_sprite_cells(context);
1173
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2842 if (context->flags & FLAG_DMA_RUN) {
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2843 run_dma_src(context, -1);
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2844 }
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2845 context->hslot++;
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2846 context->cycles += slot_cycles;
923
8e012ece95c1 Perform the same slot mapping shift for H32 mode as I did for H40
Michael Pavone <pavone@retrodev.com>
parents: 922
diff changeset
2847 vdp_advance_line(context);
1173
d0f67c59b756 Fix H32 inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1172
diff changeset
2848 CHECK_ONLY
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2849 }
822
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2850 default:
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2851 context->hslot++;
ac65086c031e Pretty decent optimization of vdp_h40 and vdp_h32. Gets reasonably close to the speed of 0.2.0 in the worst case and is faster than 0.2.0 in others
Michael Pavone <pavone@retrodev.com>
parents: 771
diff changeset
2852 context->cycles += MCLKS_SLOT_H32;
503
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2853 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2854 }
eee6be465c47 Small optimization for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 499
diff changeset
2855
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2856 static void vdp_h32_mode4(vdp_context * context, uint32_t target_cycles)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2857 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2858 uint16_t address;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2859 uint32_t mask;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2860 uint32_t const slot_cycles = MCLKS_SLOT_H32;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2861 uint8_t bgindex = 0x10 | (context->regs[REG_BG_COLOR] & 0xF) + MODE4_OFFSET;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2862 uint8_t test_layer = context->test_port >> 7 & 3;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2863 switch(context->hslot)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2864 {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2865 for (;;)
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2866 {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2867 //sprite rendering starts
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2868 SPRITE_RENDER_H32_MODE4(137)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2869 SPRITE_RENDER_H32_MODE4(143)
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2870 case 234:
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2871 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2872 CHECK_LIMIT
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2873 case 235:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2874 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2875 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2876 //!HSYNC low
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2877 case 236:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2878 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2879 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2880 case 237:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2881 external_slot(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2882 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2883 case 238:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2884 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2885 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2886 SPRITE_RENDER_H32_MODE4(239)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2887 SPRITE_RENDER_H32_MODE4(245)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2888 case 251:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2889 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2890 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2891 case 252:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2892 external_slot(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2893 if (context->regs[REG_MODE_1] & BIT_HSCRL_LOCK && context->vcounter < 16) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2894 context->hscroll_a = 0;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2895 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2896 context->hscroll_a = context->regs[REG_X_SCROLL];
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2897 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2898 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2899 case 253:
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2900 context->sprite_index = 0;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2901 context->slot_counter = MAX_DRAWS_H32_MODE4;
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2902 scan_sprite_table_mode4(context);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2903 CHECK_LIMIT
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2904 case 254:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2905 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2906 CHECK_LIMIT
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2907 case 255:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2908 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2909 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2910 case 0: {
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2911 scan_sprite_table_mode4(context);
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2912 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2913 }
1135
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2914 case 1:
8506b305e0e8 Update Mode 4 rendering to match logic analyzer captures
Michael Pavone <pavone@retrodev.com>
parents: 1134
diff changeset
2915 scan_sprite_table_mode4(context);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2916 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2917 case 2:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2918 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2919 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2920 case 3:
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2921 scan_sprite_table_mode4(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2922 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2923 case 4: {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2924 scan_sprite_table_mode4(context);
1121
1913f9c28003 Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents: 1120
diff changeset
2925 context->buf_a_off = 8;
1913f9c28003 Less broken Mode 4 implementation
Michael Pavone <pavone@retrodev.com>
parents: 1120
diff changeset
2926 memset(context->tmp_buf_a, 0, 8);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2927 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2928 }
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2929 COLUMN_RENDER_BLOCK_MODE4(0, 5)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2930 COLUMN_RENDER_BLOCK_MODE4(1, 9)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2931 COLUMN_RENDER_BLOCK_MODE4(2, 13)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2932 COLUMN_RENDER_BLOCK_MODE4(3, 17)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2933 COLUMN_RENDER_BLOCK_MODE4(4, 21)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2934 COLUMN_RENDER_BLOCK_MODE4(5, 25)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2935 COLUMN_RENDER_BLOCK_MODE4(6, 29)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2936 COLUMN_RENDER_BLOCK_MODE4(7, 33)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2937 COLUMN_RENDER_BLOCK_MODE4(8, 37)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2938 COLUMN_RENDER_BLOCK_MODE4(9, 41)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2939 COLUMN_RENDER_BLOCK_MODE4(10, 45)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2940 COLUMN_RENDER_BLOCK_MODE4(11, 49)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2941 COLUMN_RENDER_BLOCK_MODE4(12, 53)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2942 COLUMN_RENDER_BLOCK_MODE4(13, 57)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2943 COLUMN_RENDER_BLOCK_MODE4(14, 61)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2944 COLUMN_RENDER_BLOCK_MODE4(15, 65)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2945 COLUMN_RENDER_BLOCK_MODE4(16, 69)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2946 COLUMN_RENDER_BLOCK_MODE4(17, 73)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2947 COLUMN_RENDER_BLOCK_MODE4(18, 77)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2948 COLUMN_RENDER_BLOCK_MODE4(19, 81)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2949 COLUMN_RENDER_BLOCK_MODE4(20, 85)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2950 COLUMN_RENDER_BLOCK_MODE4(21, 89)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2951 COLUMN_RENDER_BLOCK_MODE4(22, 93)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2952 COLUMN_RENDER_BLOCK_MODE4(23, 97)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2953 COLUMN_RENDER_BLOCK_MODE4(24, 101)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2954 COLUMN_RENDER_BLOCK_MODE4(25, 105)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2955 COLUMN_RENDER_BLOCK_MODE4(26, 109)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2956 COLUMN_RENDER_BLOCK_MODE4(27, 113)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2957 COLUMN_RENDER_BLOCK_MODE4(28, 117)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2958 COLUMN_RENDER_BLOCK_MODE4(29, 121)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2959 COLUMN_RENDER_BLOCK_MODE4(30, 125)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2960 COLUMN_RENDER_BLOCK_MODE4(31, 129)
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2961 case 133:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2962 OUTPUT_PIXEL(133)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2963 external_slot(context);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2964 CHECK_LIMIT
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2965 case 134:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2966 OUTPUT_PIXEL(134)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2967 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2968 CHECK_LIMIT
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2969 case 135:
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2970 OUTPUT_PIXEL(135)
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2971 external_slot(context);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2972 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2973 case 136: {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2974 OUTPUT_PIXEL(136)
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2975 external_slot(context);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2976 //set things up for sprite rendering in the next slot
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2977 memset(context->linebuf, 0, LINEBUF_SIZE);
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2978 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
2979 context->sprite_draws = MAX_DRAWS_H32_MODE4;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2980 CHECK_LIMIT
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
2981 }}
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2982 default:
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2983 context->hslot++;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2984 context->cycles += MCLKS_SLOT_H32;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2985 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2986 }
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
2987
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2988 static void inactive_test_output(vdp_context *context, uint8_t is_h40, uint8_t test_layer)
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2989 {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2990 uint8_t max_slot = is_h40 ? 169 : 136;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2991 if (context->hslot > max_slot) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2992 return;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2993 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
2994 uint8_t *dst = context->compositebuf + (context->hslot >> 3) * SCROLL_BUFFER_DRAW;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2995 int32_t len;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2996 uint32_t src_off;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2997 if (context->hslot) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2998 dst -= SCROLL_BUFFER_DRAW - BORDER_LEFT;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
2999 src_off = 0;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3000 len = context->hslot == max_slot ? BORDER_RIGHT : SCROLL_BUFFER_DRAW;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3001 } else {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3002 src_off = SCROLL_BUFFER_DRAW - BORDER_LEFT;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3003 len = BORDER_LEFT;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3004 }
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3005 uint8_t *src;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3006 if (test_layer == 2) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3007 //plane A
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3008 src_off += context->buf_a_off + context->hscroll_a;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3009 src = context->tmp_buf_a;
1369
3e7a921718de Fix handling of test register selected sprite layer in border area. Gets rid of the border garbage in the "disco floor/ceiling" scene of OD2
Michael Pavone <pavone@retrodev.com>
parents: 1368
diff changeset
3010 } else if (test_layer == 3){
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3011 //plane B
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3012 src_off += context->buf_b_off + context->hscroll_b;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3013 src = context->tmp_buf_b;
1369
3e7a921718de Fix handling of test register selected sprite layer in border area. Gets rid of the border garbage in the "disco floor/ceiling" scene of OD2
Michael Pavone <pavone@retrodev.com>
parents: 1368
diff changeset
3014 } else {
3e7a921718de Fix handling of test register selected sprite layer in border area. Gets rid of the border garbage in the "disco floor/ceiling" scene of OD2
Michael Pavone <pavone@retrodev.com>
parents: 1368
diff changeset
3015 //sprite layer
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3016 memset(dst, 0, len);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3017 dst += len;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3018 len = 0;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3019 }
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3020 for (; len >=0; len--, dst++, src_off++)
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3021 {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3022 *dst = src[src_off & SCROLL_BUFFER_MASK] & 0x3F;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3023 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3024 context->done_composite = dst;
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3025 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_DRAW;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3026 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_DRAW;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3027 }
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3028
1362
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3029 static void check_switch_inactive(vdp_context *context, uint8_t is_h40)
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3030 {
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3031 //technically the second hcounter check should be different for H40, but this is probably close enough for now
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3032 if (context->state == ACTIVE && context->vcounter == context->inactive_start && (context->hslot >= (is_h40 ? 167 : 135) || context->hslot < 133)) {
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3033 context->state = INACTIVE;
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3034 }
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3035 }
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3036
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3037 static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3038 {
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3039 uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest, latch_slot;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3040 uint8_t index_reset_value, max_draws, max_sprites;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3041 uint16_t vint_line, active_line;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3042 uint32_t bg_color;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3043
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3044 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3045 if (is_h40) {
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3046 latch_slot = 165;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
3047 buf_clear_slot = 163;
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
3048 index_reset_slot = 167;
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3049 bg_end_slot = BG_START_SLOT + LINEBUF_SIZE/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3050 max_draws = MAX_DRAWS-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3051 max_sprites = MAX_SPRITES_LINE;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3052 index_reset_value = 0x80;
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3053 vint_slot = VINT_SLOT_H40;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3054 line_change = LINE_CHANGE_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3055 jump_start = 182;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3056 jump_dest = 229;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3057 } else {
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3058 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3059 max_draws = MAX_DRAWS_H32-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3060 max_sprites = MAX_SPRITES_LINE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3061 buf_clear_slot = 128;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3062 index_reset_slot = 132;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3063 index_reset_value = 0x80;
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3064 vint_slot = VINT_SLOT_H32;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3065 line_change = LINE_CHANGE_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3066 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3067 jump_dest = 233;
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3068 latch_slot = 243;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3069 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3070 vint_line = context->inactive_start;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3071 active_line = 0x1FF;
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3072 if (context->regs[REG_MODE_3] & BIT_VSCROLL) {
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3073 latch_slot = 220;
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3074 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3075 } else {
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3076 latch_slot = 220;
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3077 bg_end_slot = BG_START_SLOT + (256+HORIZ_BORDER)/2;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3078 max_draws = MAX_DRAWS_H32_MODE4;
1278
34d3cb05014d Fix VDP buffer overrun that was causing sprite flickering in some games
Michael Pavone <pavone@retrodev.com>
parents: 1273
diff changeset
3079 max_sprites = 8;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3080 buf_clear_slot = 136;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3081 index_reset_slot = 253;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3082 index_reset_value = 0;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3083 vint_line = context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3084 vint_slot = VINT_SLOT_MODE4;
1177
67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency
Michael Pavone <pavone@retrodev.com>
parents: 1175
diff changeset
3085 line_change = LINE_CHANGE_MODE4;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3086 bg_color = render_map_color(0, 0, 0);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3087 jump_start = 147;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3088 jump_dest = 233;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3089 if (context->regs[REG_MODE_1] & BIT_MODE_4) {
1380
9a5352a2f57a Implement horizontal border in Mode 4 and make a minor fix to advance_output_line to handle the later vcounter increment in that mode
Michael Pavone <pavone@retrodev.com>
parents: 1378
diff changeset
3090 active_line = 0x1FF;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3091 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3092 //never active unless either mode 4 or mode 5 is turned on
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3093 active_line = 0x200;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3094 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3095 }
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3096 uint32_t *dst;
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3097 uint8_t *debug_dst;
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3098 if (
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3099 (
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3100 context->vcounter < context->inactive_start + context->border_bot
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3101 || context->vcounter >= 0x200 - context->border_top
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3102 ) && context->hslot >= BG_START_SLOT && context->hslot < bg_end_slot
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3103 ) {
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3104 dst = context->output + 2 * (context->hslot - BG_START_SLOT);
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3105 debug_dst = context->layer_debug_buf + 2 * (context->hslot - BG_START_SLOT);
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3106 } else {
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3107 dst = NULL;
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3108 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3109
1342
4ea094d15cce Fix border rendering so that the first and last line of display are consistently drawn
Michael Pavone <pavone@retrodev.com>
parents: 1339
diff changeset
3110 if (
4ea094d15cce Fix border rendering so that the first and last line of display are consistently drawn
Michael Pavone <pavone@retrodev.com>
parents: 1339
diff changeset
3111 !dst && context->vcounter == context->inactive_start + context->border_bot
4ea094d15cce Fix border rendering so that the first and last line of display are consistently drawn
Michael Pavone <pavone@retrodev.com>
parents: 1339
diff changeset
3112 && context->hslot >= line_change && context->hslot < bg_end_slot
4ea094d15cce Fix border rendering so that the first and last line of display are consistently drawn
Michael Pavone <pavone@retrodev.com>
parents: 1339
diff changeset
3113 ) {
4ea094d15cce Fix border rendering so that the first and last line of display are consistently drawn
Michael Pavone <pavone@retrodev.com>
parents: 1339
diff changeset
3114 dst = context->output + 2 * (context->hslot - BG_START_SLOT);
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3115 debug_dst = context->layer_debug_buf + 2 * (context->hslot - BG_START_SLOT);
1342
4ea094d15cce Fix border rendering so that the first and last line of display are consistently drawn
Michael Pavone <pavone@retrodev.com>
parents: 1339
diff changeset
3116 }
4ea094d15cce Fix border rendering so that the first and last line of display are consistently drawn
Michael Pavone <pavone@retrodev.com>
parents: 1339
diff changeset
3117
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3118 uint8_t test_layer = context->test_port >> 7 & 3;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3119
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3120 while(context->cycles < target_cycles)
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3121 {
1362
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3122 check_switch_inactive(context, is_h40);
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3123 if (context->hslot == BG_START_SLOT && (
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3124 context->vcounter < context->inactive_start + context->border_bot
1342
4ea094d15cce Fix border rendering so that the first and last line of display are consistently drawn
Michael Pavone <pavone@retrodev.com>
parents: 1339
diff changeset
3125 || context->vcounter >= 0x200 - context->border_top
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3126 )) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3127 dst = context->output + (context->hslot - BG_START_SLOT) * 2;
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3128 debug_dst = context->layer_debug_buf + 2 * (context->hslot - BG_START_SLOT);
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3129 } else if (context->hslot == bg_end_slot) {
1272
be509813b2f2 Fill in the rest of the framebuffer holes created by horizontal border. Work remains for things to be seemless when display gets turned on and off mid frame
Michael Pavone <pavone@retrodev.com>
parents: 1271
diff changeset
3130 advance_output_line(context);
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3131 dst = NULL;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3132 }
1339
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3133 //this will need some tweaking to properly interact with 128K mode,
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3134 //but this should be good enough for now
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3135 context->serial_address += 1024;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3136 if (test_layer) {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3137 switch (context->hslot & 7)
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3138 {
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3139 case 3:
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3140 render_border_garbage(context, context->serial_address, context->tmp_buf_a, context->buf_a_off, context->col_1);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3141 break;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3142 case 4:
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3143 render_border_garbage(context, context->serial_address, context->tmp_buf_a, context->buf_a_off+8, context->col_2);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3144 break;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3145 case 7:
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3146 render_border_garbage(context, context->serial_address, context->tmp_buf_b, context->buf_b_off, context->col_1);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3147 break;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3148 case 0:
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3149 render_border_garbage(context, context->serial_address, context->tmp_buf_b, context->buf_b_off+8, context->col_2);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3150 inactive_test_output(context, is_h40, test_layer);
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3151 break;
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3152 }
35e6a93b4586 Implement the effect of VDP test register usage on the top and bottom borders. Fixes the remaning issue with the border dissolve in the "Ninja Escape" scene of Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1338
diff changeset
3153 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3154
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3155 if (context->hslot == buf_clear_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3156 if (mode_5) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3157 context->cur_slot = max_draws;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3158 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3159 context->cur_slot = context->sprite_index = MAX_DRAWS_H32_MODE4-1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3160 context->sprite_draws = MAX_DRAWS_H32_MODE4;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3161 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3162 memset(context->linebuf, 0, LINEBUF_SIZE);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3163 } else if (context->hslot == index_reset_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3164 context->sprite_index = index_reset_value;
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
3165 context->slot_counter = mode_5 ? 0 : max_sprites;
1454
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3166 } else if (context->hslot == latch_slot) {
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3167 //it seems unlikely to me that vscroll actually gets latched when the display is off
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3168 //but it's the only straightforward way to reconcile what I'm seeing between Skitchin
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3169 //(which seems to expect vscroll to be latched early) and the intro of Gunstar Heroes
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3170 //(which disables the display and ends up with garbage if vscroll is latched during that period)
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3171 //without it. Some more tests are definitely needed
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3172 context->vscroll_latch[0] = context->vsram[0];
a664bade4b29 Fix minor graphical regression in Gunstar Heroes
Michael Pavone <pavone@retrodev.com>
parents: 1437
diff changeset
3173 context->vscroll_latch[1] = context->vsram[1];
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3174 } else if (context->vcounter == vint_line && context->hslot == vint_slot) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3175 context->flags2 |= FLAG2_VINT_PENDING;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3176 context->pending_vint_start = context->cycles;
1436
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
3177 } else if (context->vcounter == context->inactive_start && context->hslot == 1 && (context->regs[REG_MODE_4] & BIT_INTERLACE)) {
40c3be9f1af7 Fix timing of VDP ODD flag toggle
Michael Pavone <pavone@retrodev.com>
parents: 1432
diff changeset
3178 context->flags2 ^= FLAG2_EVEN_FIELD;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3179 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3180
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3181 if (dst) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3182 uint8_t bg_index;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3183 if (mode_5) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3184 bg_index = context->regs[REG_BG_COLOR] & 0x3F;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3185 bg_color = context->colors[bg_index];
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3186 } else if (context->regs[REG_MODE_1] & BIT_MODE_4) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3187 bg_index = 0x10 + (context->regs[REG_BG_COLOR] & 0xF);
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3188 bg_color = context->colors[MODE4_OFFSET + bg_index];
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3189 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3190 if (context->done_composite) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3191 uint8_t pixel = context->compositebuf[dst-context->output];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3192 if (!(pixel & 0x3F | test_layer)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3193 pixel = pixel & 0xC0 | bg_index;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3194 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3195 *(dst++) = context->colors[pixel];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3196 if ((dst - context->output) == (context->done_composite - context->compositebuf)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3197 context->done_composite = NULL;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3198 memset(context->compositebuf, 0, sizeof(context->compositebuf));
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3199 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3200 } else {
1343
033dda2d4598 Fix transition from active to inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1342
diff changeset
3201 *(dst++) = bg_color;
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3202 *(debug_dst++) = DBG_SRC_BG;
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3203 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3204 if (context->done_composite) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3205 uint8_t pixel = context->compositebuf[dst-context->output];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3206 if (!(pixel & 0x3F | test_layer)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3207 pixel = pixel & 0xC0 | bg_index;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3208 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3209 *(dst++) = context->colors[pixel];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3210 if ((dst - context->output) == (context->done_composite - context->compositebuf)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3211 context->done_composite = NULL;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3212 memset(context->compositebuf, 0, sizeof(context->compositebuf));
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3213 }
1343
033dda2d4598 Fix transition from active to inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1342
diff changeset
3214 } else {
033dda2d4598 Fix transition from active to inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1342
diff changeset
3215 *(dst++) = bg_color;
1644
cf4e387a8db6 Populate layer debug buffer during inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1643
diff changeset
3216 *(debug_dst++) = DBG_SRC_BG;
1343
033dda2d4598 Fix transition from active to inactive display
Michael Pavone <pavone@retrodev.com>
parents: 1342
diff changeset
3217 }
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3218
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3219 if (context->hslot == (bg_end_slot-1)) {
1821
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3220 if (context->done_composite) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3221 uint8_t pixel = context->compositebuf[dst-context->output];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3222 if (!(pixel & 0x3F | test_layer)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3223 pixel = pixel & 0xC0 | bg_index;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3224 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3225 *(dst++) = context->colors[pixel];
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3226 if ((dst - context->output) == (context->done_composite - context->compositebuf)) {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3227 context->done_composite = NULL;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3228 memset(context->compositebuf, 0, sizeof(context->compositebuf));
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3229 }
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3230 } else {
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3231 *(dst++) = bg_color;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3232 *(debug_dst++) = DBG_SRC_BG;
4f3443ecb6d6 Separate compositing from final output. Fixes some minor accuracy issues with regards to when background color reg/CRAM changes take effect. Fixes minor glitch in DF Retro Direct Color DMA demo at inactive/active transition
Michael Pavone <pavone@retrodev.com>
parents: 1785
diff changeset
3233 }
1267
3772bb926be5 Initial stab at horizontal border emulation. Only works for H40 and still has a few minor holes to fill
Michael Pavone <pavone@retrodev.com>
parents: 1191
diff changeset
3234 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3235 }
1183
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3236
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3237 if (!is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3238 external_slot(context);
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3239 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) {
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3240 run_dma_src(context, context->hslot);
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3241 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3242 }
8d8c71ebbbce CRAM contention artifact emulation
Michael Pavone <pavone@retrodev.com>
parents: 1180
diff changeset
3243
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3244 if (is_h40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3245 if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3246 context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40];
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3247 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3248 context->cycles += MCLKS_SLOT_H40;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3249 }
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3250 } else {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3251 context->cycles += MCLKS_SLOT_H32;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3252 }
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3253 if (context->hslot == jump_start) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3254 context->hslot = jump_dest;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3255 } else {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3256 context->hslot++;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3257 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3258 if (context->hslot == line_change) {
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3259 vdp_advance_line(context);
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3260 if (context->vcounter == active_line) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3261 context->state = PREPARING;
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3262 return;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3263 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3264 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3265 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3266 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3267
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3268 void vdp_run_context_full(vdp_context * context, uint32_t target_cycles)
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3269 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3270 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3271 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3272 while(context->cycles < target_cycles)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3273 {
1362
83bdd358f3a7 Fix regression in games that disable the display early like F1 World Championship. Remove debug printf
Michael Pavone <pavone@retrodev.com>
parents: 1361
diff changeset
3274 check_switch_inactive(context, is_h40);
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3275
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3276 if (is_active(context)) {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3277 if (mode_5) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3278 if (is_h40) {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3279 vdp_h40(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3280 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3281 vdp_h32(context, target_cycles);
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3282 }
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
3283 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3284 vdp_h32_mode4(context, target_cycles);
330
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
3285 }
57453d3d8be4 Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents: 329
diff changeset
3286 } else {
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3287 vdp_inactive(context, target_cycles, is_h40, mode_5);
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3288 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3289 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3290 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3291
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3292 void vdp_run_context(vdp_context *context, uint32_t target_cycles)
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3293 {
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3294 //TODO: Deal with H40 hsync shenanigans
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3295 uint32_t slot_cyc = context->regs[REG_MODE_4] & BIT_H40 ? 15 : 19;
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3296 if (target_cycles < slot_cyc) {
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3297 //avoid overflow
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3298 return;
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3299 }
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3300 vdp_run_context_full(context, target_cycles - slot_cyc);
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3301 }
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3302
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3303 uint32_t vdp_run_to_vblank(vdp_context * context)
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3304 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3305 uint32_t old_frame = context->frame;
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3306 while (context->frame == old_frame) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3307 vdp_run_context_full(context, context->cycles + MCLKS_LINE);
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3308 }
20
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3309 return context->cycles;
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3310 }
f664eeb55cb4 Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3311
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3312 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles)
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3313 {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3314 for(;;) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3315 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L];
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3316 if (!dmalen) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3317 dmalen = 0x10000;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3318 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3319 uint32_t min_dma_complete = dmalen * (context->regs[REG_MODE_4] & BIT_H40 ? 16 : 20);
1321
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
3320 if (
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3321 (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_COPY
1321
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
3322 || (((context->cd & 0xF) == VRAM_WRITE) && !(context->regs[REG_MODE_2] & BIT_128K_VRAM))) {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3323 //DMA copies take twice as long to complete since they require a read and a write
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3324 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word
1321
0849e9356bfe Fix time 68K is locked out of bus when doing a 128KB VRAM mode DMA transfer. Fixes a number of problems in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1320
diff changeset
3325 //unless 128KB mode is enabled
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3326 min_dma_complete *= 2;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3327 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3328 min_dma_complete += context->cycles;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3329 if (target_cycles < min_dma_complete) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3330 vdp_run_context_full(context, target_cycles);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3331 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3332 } else {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3333 vdp_run_context_full(context, min_dma_complete);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3334 if (!(context->flags & FLAG_DMA_RUN)) {
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3335 return;
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3336 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3337 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3338 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3339 }
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3340
1154
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3341 static uint16_t get_ext_vcounter(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3342 {
1437
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3343 uint16_t line= context->vcounter;
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3344 if (context->regs[REG_MODE_4] & BIT_INTERLACE) {
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3345 if (context->double_res) {
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3346 line <<= 1;
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3347 } else {
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3348 line &= 0x1FE;
da72344af3ff Fix external v counter when normal resolution interlace mode is active
Michael Pavone <pavone@retrodev.com>
parents: 1436
diff changeset
3349 }
1154
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3350 if (line & 0x100) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3351 line |= 1;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3352 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3353 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3354 return line << 8;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3355 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3356
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3357 void vdp_latch_hv(vdp_context *context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3358 {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3359 context->hv_latch = context->hslot | get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3360 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3361
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3362 uint16_t vdp_hv_counter_read(vdp_context * context)
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3363 {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3364 if ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_1] & BIT_HVC_LATCH)) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3365 return context->hv_latch;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3366 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3367 uint16_t hv;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3368 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3369 hv = context->hslot;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3370 } else {
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3371 hv = context->hv_latch & 0xFF;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3372 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3373 hv |= get_ext_vcounter(context);
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3374
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3375 return hv;
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3376 }
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3377
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3378 int vdp_control_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3379 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3380 //printf("control port write: %X at %d\n", value, context->cycles);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3381 if (context->flags & FLAG_DMA_RUN) {
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3382 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3383 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3384 if (context->flags & FLAG_PENDING) {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
3385 context->address = (context->address & 0x3FFF) | (value << 14 & 0x1C000);
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3386 //It seems like the DMA enable bit doesn't so much enable DMA so much
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3387 //as it enables changing CD5 from control port writes
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3388 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23;
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3389 context->cd = (context->cd & preserve) | ((value >> 2) & ~preserve & 0xFF);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3390 context->flags &= ~FLAG_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3391 //Should these be taken care of here or after the first write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3392 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3393 context->flags2 &= ~FLAG2_READ_PENDING;
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
3394 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3395 if (context->cd & 0x20) {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3396 //
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3397 if((context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) != DMA_FILL) {
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3398 //DMA copy or 68K -> VDP, transfer starts immediately
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3399 //printf("DMA start (length: %X) at cycle %d, frame: %d, vcounter: %d, hslot: %d\n", (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L], context->cycles, context->frame, context->vcounter, context->hslot);
1191
8dc50e50ced6 Remove accidentally committed debug logging
Michael Pavone <pavone@retrodev.com>
parents: 1189
diff changeset
3400 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
8dc50e50ced6 Remove accidentally committed debug logging
Michael Pavone <pavone@retrodev.com>
parents: 1189
diff changeset
3401 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]);
1289
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
3402 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
3403 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
3404 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible
6ad59a62e656 Adjust DMA start delay to not break the FIFO Wait State test in the VDP FIFO Testing ROM
Michael Pavone <pavone@retrodev.com>
parents: 1285
diff changeset
3405 //sticking with 3 slots for now until I can do some more captures
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3406 vdp_run_context_full(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5));
1285
76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation
Michael Pavone <pavone@retrodev.com>
parents: 1278
diff changeset
3407 context->flags |= FLAG_DMA_RUN;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3408 return 1;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3409 } else {
1285
76e47254596b Remove hacky post-DMA delay add proper pre-DMA delay based on logic analyzer capture. 512 color screen is a bit messed up but mostly works. Needs investigation
Michael Pavone <pavone@retrodev.com>
parents: 1278
diff changeset
3410 context->flags |= FLAG_DMA_RUN;
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3411 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3412 }
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3413 } else {
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
3414 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3415 }
63
a6dd5b7a971b Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents: 58
diff changeset
3416 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3417 } else {
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3418 uint8_t mode_5 = context->regs[REG_MODE_2] & BIT_MODE_5;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3419 context->address = (context->address &0xC000) | (value & 0x3FFF);
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3420 context->cd = (context->cd & 0x3C) | (value >> 14);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3421 if ((value & 0xC000) == 0x8000) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3422 //Register write
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3423 uint8_t reg = (value >> 8) & 0x1F;
1123
d5412f76accc Fix inactive start line for Mode 4 in vdp_next_hint. Fix an off by one error in the range of registers allowed to be written in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1122
diff changeset
3424 if (reg < (mode_5 ? VDP_REGS : 0xB)) {
453
b491df8bdbc0 Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents: 452
diff changeset
3425 //printf("register %d set to %X\n", reg, value & 0xFF);
480
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
3426 if (reg == REG_MODE_1 && (value & BIT_HVC_LATCH) && !(context->regs[reg] & BIT_HVC_LATCH)) {
1154
c83ec07ddbac Implemented Mode 4 H conter latching
Michael Pavone <pavone@retrodev.com>
parents: 1153
diff changeset
3427 vdp_latch_hv(context);
480
0737953132ad Implement HV counter latch
Mike Pavone <pavone@retrodev.com>
parents: 479
diff changeset
3428 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
3429 if (reg == REG_BG_COLOR) {
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
3430 value &= 0x3F;
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 503
diff changeset
3431 }
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
3432 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3433 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame);
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
3434 }*/
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3435 context->regs[reg] = value;
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3436 if (reg == REG_MODE_4) {
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3437 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES);
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
3438 if (!context->double_res) {
1106
cacbd3f18f03 Fix field flag handling bug introduced with VDP/render interface cleanup
Michael Pavone <pavone@retrodev.com>
parents: 1103
diff changeset
3439 context->flags2 &= ~FLAG2_EVEN_FIELD;
415
8c60c8c09a0f Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents: 414
diff changeset
3440 }
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3441 }
1335
26e72126f9d1 Fixes to sprite phase 2 so that sprite X reads use the exact same slot as on hardware in the case that there are fewer than the max number of sprites on each line. Re-read sprite Y from SAT cache during phase 2 and properly mask the calculated row. Fixes remaining issues with spinning cube scene in Overdrive 2.
Michael Pavone <pavone@retrodev.com>
parents: 1334
diff changeset
3442 if (reg == REG_MODE_1 || reg == REG_MODE_2 || reg == REG_MODE_4) {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3443 update_video_params(context);
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3444 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3445 }
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3446 } else if (mode_5) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3447 context->flags |= FLAG_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3448 //Should these be taken care of here or after the second write?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3449 //context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3450 //context->flags2 &= ~FLAG2_READ_PENDING;
1120
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3451 } else {
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3452 context->flags &= ~FLAG_READ_FETCHED;
e9369d6f0101 Somewhat broken implementation of Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1117
diff changeset
3453 context->flags2 &= ~FLAG2_READ_PENDING;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3454 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3455 }
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3456 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3457 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3458
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3459 void vdp_control_port_write_pbc(vdp_context *context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3460 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3461 if (context->flags2 & FLAG2_BYTE_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3462 uint16_t full_val = value << 8 | context->pending_byte;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3463 context->flags2 &= ~FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3464 //TODO: Deal with fact that Vbus->VDP DMA doesn't do anything in PBC mode
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3465 vdp_control_port_write(context, full_val);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3466 if (context->cd == VRAM_READ) {
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3467 context->cd = VRAM_READ8;
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3468 }
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3469 } else {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3470 context->pending_byte = value;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3471 context->flags2 |= FLAG2_BYTE_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3472 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3473 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3474
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3475 int vdp_data_port_write(vdp_context * context, uint16_t value)
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3476 {
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3477 //printf("data port write: %X at %d\n", value, context->cycles);
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3478 if (context->flags & FLAG_DMA_RUN && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) != DMA_FILL) {
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3479 return -1;
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3480 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3481 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3482 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3483 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3484 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3485 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3486 }
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
3487 /*if (context->fifo_cur == context->fifo_end) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3488 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
109
004dd46e0a97 COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents: 108
diff changeset
3489 }*/
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3490 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) {
460
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
3491 context->flags &= ~FLAG_DMA_RUN;
788ba843a731 Implement FIFO latency and improve DMA accuracy
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
3492 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3493 while (context->fifo_write == context->fifo_read) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3494 vdp_run_context_full(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3495 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3496 fifo_entry * cur = context->fifo + context->fifo_write;
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3497 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3498 cur->address = context->address;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3499 cur->value = value;
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3500 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3501 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3502 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3503 cur->cd = (context->cd & 2) | 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3504 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3505 cur->partial = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3506 if (context->fifo_read < 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3507 context->fifo_read = context->fifo_write;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3508 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3509 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3510 increment_address(context);
149
139e5dcd6aa3 Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents: 143
diff changeset
3511 return 0;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3512 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3513
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3514 void vdp_data_port_write_pbc(vdp_context * context, uint8_t value)
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3515 {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3516 if (context->flags & FLAG_PENDING) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3517 context->flags &= ~FLAG_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3518 //Should these be cleared here?
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3519 context->flags &= ~FLAG_READ_FETCHED;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3520 context->flags2 &= ~FLAG2_READ_PENDING;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3521 }
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3522 context->flags2 &= ~FLAG2_BYTE_PENDING;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3523 /*if (context->fifo_cur == context->fifo_end) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3524 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3525 }*/
1637
95880d947257 Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
Michael Pavone <pavone@retrodev.com>
parents: 1634
diff changeset
3526 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) {
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3527 context->flags &= ~FLAG_DMA_RUN;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3528 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3529 while (context->fifo_write == context->fifo_read) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3530 vdp_run_context_full(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3531 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3532 fifo_entry * cur = context->fifo + context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3533 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3534 cur->address = context->address;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3535 cur->value = value;
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3536 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3537 cur->cd = context->cd;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3538 } else {
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3539 cur->cd = (context->cd & 2) | 1;
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3540 }
1333
69c25e1188e5 Small tweak to how SAT cache updates are done. Mostly fixes the rotating cube scene in Overdrive 2
Michael Pavone <pavone@retrodev.com>
parents: 1331
diff changeset
3541 cur->partial = 3;
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3542 if (context->fifo_read < 0) {
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3543 context->fifo_read = context->fifo_write;
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3544 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3545 context->fifo_write = (context->fifo_write + 1) & (FIFO_SIZE-1);
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3546 increment_address(context);
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3547 }
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3548
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3549 void vdp_test_port_write(vdp_context * context, uint16_t value)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3550 {
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
3551 context->test_port = value;
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3552 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3553
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3554 uint16_t vdp_control_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3555 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3556 context->flags &= ~FLAG_PENDING;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3557 context->flags2 &= ~FLAG2_BYTE_PENDING;
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3558 //Bits 15-10 are not fixed like Charles MacDonald's doc suggests, but instead open bus values that reflect 68K prefetch
1117
928a65750345 Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
Michael Pavone <pavone@retrodev.com>
parents: 1106
diff changeset
3559 uint16_t value = context->system->get_open_bus_value(context->system) & 0xFC00;
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3560 if (context->fifo_read < 0) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3561 value |= 0x200;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3562 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3563 if (context->fifo_read == context->fifo_write) {
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3564 value |= 0x100;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3565 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3566 if (context->flags2 & FLAG2_VINT_PENDING) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3567 value |= 0x80;
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3568 }
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3569 if (context->flags & FLAG_DOT_OFLOW) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3570 value |= 0x40;
1156
b519965f6394 Clear sprite overflow flag when control port read. Fix vcounter progression in Mode 4
Michael Pavone <pavone@retrodev.com>
parents: 1155
diff changeset
3571 context->flags &= ~FLAG_DOT_OFLOW;
494
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3572 }
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3573 if (context->flags2 & FLAG2_SPRITE_COLLIDE) {
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3574 value |= 0x20;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3575 context->flags2 &= ~FLAG2_SPRITE_COLLIDE;
8ac0eb05642c Initial implementation of sprite overflow and sprite collision status register flags
Mike Pavone <pavone@retrodev.com>
parents: 481
diff changeset
3576 }
1077
1a66d5165ea7 Cleanup the separation of render backend and VDP code in preparation for having extra debug windows. Make determination of H40/H32 based on number of lines in each mode.
Michael Pavone <pavone@retrodev.com>
parents: 1076
diff changeset
3577 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && !(context->flags2 & FLAG2_EVEN_FIELD)) {
413
36fbbced25c2 Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents: 337
diff changeset
3578 value |= 0x10;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3579 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3580 uint32_t slot = context->hslot;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3581 if (!is_active(context)) {
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
3582 value |= 0x8;
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
3583 }
622
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3584 if (context->regs[REG_MODE_4] & BIT_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3585 if (slot < HBLANK_END_H40 || slot > HBLANK_START_H40) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3586 value |= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3587 }
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3588 } else {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3589 if (slot < HBLANK_END_H32 || slot > HBLANK_START_H32) {
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3590 value |= 0x4;
b76d2a628ab9 Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
Michael Pavone <pavone@retrodev.com>
parents: 621
diff changeset
3591 }
318
789f2f5f2277 Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents: 317
diff changeset
3592 }
983
14d2f3b0e45d Fixes to the DMA busy flag and DMA fill. Now up to 120/122 on VDP FIFO Testing.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
3593 if (context->cd & 0x20) {
141
576f55711d8d Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents: 138
diff changeset
3594 value |= 0x2;
75
108e587165c0 Implement DMA (untested)
Mike Pavone <pavone@retrodev.com>
parents: 65
diff changeset
3595 }
714
e29bc2918f69 Fix VDP status register PAL bit based on observations of the Titan Overdrive demo
Michael Pavone <pavone@retrodev.com>
parents: 711
diff changeset
3596 if (context->flags2 & FLAG2_REGION_PAL) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3597 value |= 0x1;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3598 }
459
c49ecf575784 Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents: 454
diff changeset
3599 //printf("status read at cycle %d returned %X\n", context->cycles, value);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3600 return value;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3601 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3602
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3603 uint16_t vdp_data_port_read(vdp_context * context)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3604 {
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3605 if (context->flags & FLAG_PENDING) {
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3606 context->flags &= ~FLAG_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3607 //Should these be cleared here?
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3608 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3609 context->flags2 &= ~FLAG2_READ_PENDING;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3610 }
138
aa3e1bb338c9 Fix VDP reads
Mike Pavone <pavone@retrodev.com>
parents: 137
diff changeset
3611 if (context->cd & 1) {
991
f9ee6f746cb4 Properly emulate machine freeze when reading from VDP while configured for writes
Michael Pavone <pavone@retrodev.com>
parents: 984
diff changeset
3612 warning("Read from VDP data port while writes are configured, CPU is now frozen. VDP Address: %X, CD: %X\n", context->address, context->cd);
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3613 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3614 while (!(context->flags & FLAG_READ_FETCHED)) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3615 vdp_run_context_full(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3616 }
980
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3617 context->flags &= ~FLAG_READ_FETCHED;
928442068afe Implemented VDP read prefetch and made DMA copy not use the FIFO any more. Now up to 114 out of 122 passing on VDP FIFO Test ROM
Michael Pavone <pavone@retrodev.com>
parents: 953
diff changeset
3618 return context->prefetch;
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3619 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 43
diff changeset
3620
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3621 uint8_t vdp_data_port_read_pbc(vdp_context * context)
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3622 {
1153
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3623 context->flags &= ~(FLAG_PENDING | FLAG_READ_FETCHED);
2e3ad914bad3 BlastEm now passes all of the tests on the first page of "Megadrive VDP Test" in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1152
diff changeset
3624 context->flags2 &= ~FLAG2_BYTE_PENDING;
1151
681e8a13b261 Fix some issues with VDP interface in Mode 4/PBC mode
Michael Pavone <pavone@retrodev.com>
parents: 1150
diff changeset
3625
1152
ddbb61be6119 Fix to pass a couple more tests in VDPTEST.sms
Michael Pavone <pavone@retrodev.com>
parents: 1151
diff changeset
3626 context->cd = VRAM_READ8;
1149
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3627 return context->prefetch;
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3628 }
6b0da6021544 Don't lock up CPU if performing a read with writes configured when in PBC mode. Allow access to VDP debug commands from Z80 debugger in PBC mode. Handle Mode 4 in VDP debug print functions
Michael Pavone <pavone@retrodev.com>
parents: 1138
diff changeset
3629
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3630 uint16_t vdp_test_port_read(vdp_context * context)
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3631 {
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3632 //TODO: Find out what actually gets returned here
1318
bfdd450e7dea Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
Michael Pavone <pavone@retrodev.com>
parents: 1315
diff changeset
3633 return context->test_port;
470
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3634 }
541c1ae8abf3 Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3635
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3636 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3637 {
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3638 context->cycles -= deduction;
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3639 if (context->pending_vint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3640 context->pending_vint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3641 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3642 context->pending_vint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3643 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3644 if (context->pending_hint_start >= deduction) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3645 context->pending_hint_start -= deduction;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3646 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3647 context->pending_hint_start = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3648 }
471
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3649 if (context->fifo_read >= 0) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3650 int32_t idx = context->fifo_read;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3651 do {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3652 if (context->fifo[idx].cycle >= deduction) {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3653 context->fifo[idx].cycle -= deduction;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3654 } else {
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3655 context->fifo[idx].cycle = 0;
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3656 }
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3657 idx = (idx+1) & (FIFO_SIZE-1);
f065769836e8 Implement FIFO as a ring buffer so the behavior of reads from invalid CRAM and VSRAM bits can be implemented properly
Mike Pavone <pavone@retrodev.com>
parents: 470
diff changeset
3658 } while(idx != context->fifo_write);
65
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3659 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3660 }
aef6302770c2 Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents: 63
diff changeset
3661
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
3662 static uint32_t vdp_cycles_hslot_wrap_h40(vdp_context * context)
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3663 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3664 if (context->hslot < 183) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3665 return MCLKS_LINE - context->hslot * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3666 } else if (context->hslot < HSYNC_END_H40) {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3667 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3668 uint32_t hsync = 0;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3669 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++)
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3670 {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3671 hsync += h40_hsync_cycles[i];
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3672 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3673 uint32_t after_hsync = (256- HSYNC_END_H40) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3674 return before_hsync + hsync + after_hsync;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3675 } else {
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3676 return (256-context->hslot) * MCLKS_SLOT_H40;
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3677 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3678 }
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3679
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
3680 static uint32_t vdp_cycles_next_line(vdp_context * context)
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3681 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3682 if (context->regs[REG_MODE_4] & BIT_H40) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3683 //TODO: Handle "illegal" Mode 4/H40 combo
647
5d58dcd94733 Fix the HV counter and adjust the slots of certain VDP events
Michael Pavone <pavone@retrodev.com>
parents: 629
diff changeset
3684 if (context->hslot < LINE_CHANGE_H40) {
697
7f96bd1cb1be Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents: 680
diff changeset
3685 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3686 } else {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3687 return vdp_cycles_hslot_wrap_h40(context) + LINE_CHANGE_H40 * MCLKS_SLOT_H40;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3688 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3689 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3690 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3691 if (context->hslot < LINE_CHANGE_H32) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3692 return (LINE_CHANGE_H32 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3693 } else if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3694 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3695 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3696 return (256-context->hslot + LINE_CHANGE_H32) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3697 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3698 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3699 if (context->hslot < 148) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3700 return (148 - context->hslot + LINE_CHANGE_MODE4 - 233) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3701 } else if (context->hslot < LINE_CHANGE_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3702 return (LINE_CHANGE_MODE4 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3703 } else {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3704 return MCLKS_LINE - (context->hslot - LINE_CHANGE_MODE4) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3705 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3706 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3707 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3708 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3709
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3710 static void get_jump_params(vdp_context *context, uint32_t *jump_start, uint32_t *jump_dst)
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3711 {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3712 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3713 if (context->flags2 & FLAG2_REGION_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3714 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3715 *jump_start = 0x10B;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3716 *jump_dst = 0x1D2;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3717 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3718 *jump_start = 0x103;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3719 *jump_dst = 0x1CA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3720 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3721 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3722 if (context->regs[REG_MODE_2] & BIT_PAL) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3723 *jump_start = 0x100;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3724 *jump_dst = 0x1FA;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3725 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3726 *jump_start = 0xEB;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3727 *jump_dst = 0x1E5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3728 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3729 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3730 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3731 *jump_start = 0xDB;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3732 *jump_dst = 0x1D5;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3733 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3734 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3735
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1077
diff changeset
3736 static uint32_t vdp_cycles_to_line(vdp_context * context, uint32_t target)
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3737 {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3738 uint32_t jump_start, jump_dst;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3739 get_jump_params(context, &jump_start, &jump_dst);
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3740 uint32_t lines;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3741 if (context->vcounter < target) {
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3742 if (target < jump_start || context->vcounter > jump_start) {
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3743 lines = target - context->vcounter;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3744 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3745 lines = jump_start - context->vcounter + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3746 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3747 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3748 if (context->vcounter < jump_start) {
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
3749 lines = jump_start - context->vcounter + 512 - jump_dst;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3750 } else {
718
eaba6789f316 Update vscroll latch implementation to be more in line with what Eke-Eke has observed. Revert the change to vdp_cycles_to_line because it breaks hints on line 0. H-Int timing is still a little messed up, but the previous change made things worse.
Michael Pavone <pavone@retrodev.com>
parents: 717
diff changeset
3751 lines = 512 - context->vcounter;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3752 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3753 if (target < jump_start) {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3754 lines += target;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3755 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3756 lines += jump_start + target - jump_dst;
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3757 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3758 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3759 return MCLKS_LINE * (lines - 1) + vdp_cycles_next_line(context);
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3760 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3761
680
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
3762 uint32_t vdp_cycles_to_frame_end(vdp_context * context)
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
3763 {
1167
e758ddbf0624 Initial work on emulating top and bottom border area
Michael Pavone <pavone@retrodev.com>
parents: 1163
diff changeset
3764 return context->cycles + vdp_cycles_to_line(context, context->inactive_start);
680
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
3765 }
4996369f1463 Some small synchronization improvements that do not seem to fix anything
Michael Pavone <pavone@retrodev.com>
parents: 678
diff changeset
3766
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3767 uint32_t vdp_next_hint(vdp_context * context)
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3768 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3769 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3770 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3771 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3772 if (context->flags2 & FLAG2_HINT_PENDING) {
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3773 return context->pending_hint_start;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3774 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3775 uint32_t hint_line;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3776 if (context->state != ACTIVE) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3777 hint_line = context->regs[REG_HINT];
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3778 if (hint_line > context->inactive_start) {
724
2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents: 722
diff changeset
3779 return 0xFFFFFFFF;
2174f92c5f9b Fix bug in vdp_next_hint that was causing HINTs to fire repeatedly when they should not have fired at all based on an HINT interval that was larger than the number of active lines in the display
Michael Pavone <pavone@retrodev.com>
parents: 722
diff changeset
3780 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3781 } else {
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3782 hint_line = context->vcounter + context->hint_counter + 1;
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3783 if (context->vcounter < context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3784 if (hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3785 hint_line = context->regs[REG_HINT];
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3786 if (hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3787 return 0xFFFFFFFF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3788 }
1366
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3789 if (hint_line >= context->vcounter) {
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3790 //Next interrupt is for a line in the next frame that
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3791 //is higher than the line we're on now so just passing
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3792 //that line number to vdp_cycles_to_line will yield the wrong
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3793 //result
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3794 return context->cycles + vdp_cycles_to_line(context, 0) + hint_line * MCLKS_LINE;
1366
c74a2f31ae5f Fix regression in horizontal interrupt timing that was breaking the "water" palette swap in the Sonic series and other games
Michael Pavone <pavone@retrodev.com>
parents: 1365
diff changeset
3795 }
1325
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3796 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3797 } else {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3798 uint32_t jump_start, jump_dst;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3799 get_jump_params(context, &jump_start, &jump_dst);
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3800 if (hint_line >= jump_start && context->vcounter < jump_dst) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3801 hint_line = (hint_line + jump_dst - jump_start) & 0x1FF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3802 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3803 if (hint_line < context->vcounter && hint_line > context->inactive_start) {
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3804 return 0xFFFFFFFF;
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3805 }
58bfbed6cdb5 Fairly major rework of how active/passive is handled along with how the V30 mode bit is handled. Allows the vertical border extension trick in Overdrive 2 to work right
Michael Pavone <pavone@retrodev.com>
parents: 1322
diff changeset
3806 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3807 }
1371
5b20840711c1 Remove HINT_FUDGE and make a small adjustment to how VDP syncs with rest of system instead. Worse results on CRAM dot issue, but much less of a hack
Michael Pavone <pavone@retrodev.com>
parents: 1369
diff changeset
3808 return context->cycles + vdp_cycles_to_line(context, hint_line);
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3809 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3810
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3811 static uint32_t vdp_next_vint_real(vdp_context * context)
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3812 {
327
1b00258b1f29 Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents: 323
diff changeset
3813 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) {
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3814 return 0xFFFFFFFF;
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3815 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3816 if (context->flags2 & FLAG2_VINT_PENDING) {
717
22dbdf50d33c Small correction to VBLANK flag timing. Fixed some inconsistencies in interrupt timing calculation.
Michael Pavone <pavone@retrodev.com>
parents: 714
diff changeset
3817 return context->pending_vint_start;
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3818 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3819
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3820
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3821 return vdp_next_vint_z80(context);
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3822 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3823
1171
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3824 uint32_t vdp_next_vint(vdp_context *context)
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3825 {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3826 uint32_t ret = vdp_next_vint_real(context);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3827 #ifdef TIMING_DEBUG
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3828 static uint32_t last = 0xFFFFFFFF;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3829 if (last != ret) {
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3830 printf("vdp_next_vint is %d at frame %d, line %d, hslot %d\n", ret, context->frame, context->vcounter, context->hslot);
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3831 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3832 last = ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3833 #endif
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3834 return ret;
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3835 }
43fa92976ff2 Fix some timing inconsistencies in H40 mode. Added some ifdefed timing debug code.
Michael Pavone <pavone@retrodev.com>
parents: 1170
diff changeset
3836
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3837 uint32_t vdp_next_vint_z80(vdp_context * context)
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3838 {
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3839 uint16_t vint_line = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->inactive_start : context->inactive_start + 1;
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3840 if (context->vcounter == vint_line) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3841 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3842 if (context->regs[REG_MODE_4] & BIT_H40) {
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3843 if (context->hslot >= LINE_CHANGE_H40 || context->hslot <= VINT_SLOT_H40) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3844 uint32_t cycles = context->cycles;
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3845 if (context->hslot >= LINE_CHANGE_H40) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3846 if (context->hslot < 183) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3847 cycles += (183 - context->hslot) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3848 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3849
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3850 if (context->hslot < HSYNC_SLOT_H40) {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3851 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40;
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3852 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3853 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ )
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3854 {
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3855 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3856 }
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3857 cycles += (256 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3858 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3859
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3860 cycles += (VINT_SLOT_H40 - (context->hslot >= LINE_CHANGE_H40 ? 0 : context->hslot)) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3861 return cycles;
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
3862 }
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3863 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3864 if (context->hslot >= LINE_CHANGE_H32 || context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3865 if (context->hslot <= VINT_SLOT_H32) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3866 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32;
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3867 } else if (context->hslot < 233) {
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3868 return context->cycles + (VINT_SLOT_H32 + 256 - 233 + 148 - context->hslot) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3869 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3870 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3871 }
995
2bc27415565b Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
Michael Pavone <pavone@retrodev.com>
parents: 991
diff changeset
3872 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3873 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3874 } else {
1177
67e0462c30ce Fix line advancement in Mode 4 during inactive display. Fix a Mode 4 VInt timing discrepency
Michael Pavone <pavone@retrodev.com>
parents: 1175
diff changeset
3875 if (context->hslot >= LINE_CHANGE_MODE4) {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3876 return context->cycles + (VINT_SLOT_MODE4 + 256 - context->hslot) * MCLKS_SLOT_H32;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3877 }
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3878 if (context->hslot <= VINT_SLOT_MODE4) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3879 return context->cycles + (VINT_SLOT_MODE4 - context->hslot) * MCLKS_SLOT_H32;
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3880 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3881 }
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3882 }
1169
82d8b9324b10 Rework how inactive lines are handled. Fix H40 cycle increment in slot 182
Michael Pavone <pavone@retrodev.com>
parents: 1168
diff changeset
3883 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line);
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3884 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3885 if (context->regs[REG_MODE_4] & BIT_H40) {
1175
0e0386fa795c Fix H40 VInt inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1174
diff changeset
3886 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3887 } else {
1174
500d8deea802 Fix H32 VInt timing inconsistency
Michael Pavone <pavone@retrodev.com>
parents: 1173
diff changeset
3888 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3889 }
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3890 } else {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3891 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32;
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3892 }
623
66cc60215e5c Fix most of the breakage caused by the vcounter/hcounter changes
Michael Pavone <pavone@retrodev.com>
parents: 622
diff changeset
3893 return context->cycles + cycles_to_vint;
333
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3894 }
f16136a3835d Update Z80 vint timing
Mike Pavone <pavone@retrodev.com>
parents: 332
diff changeset
3895
1377
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3896 uint32_t vdp_next_nmi(vdp_context *context)
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3897 {
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3898 if (!(context->flags2 & FLAG2_PAUSE)) {
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3899 return 0xFFFFFFFF;
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3900 }
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3901 return context->cycles + vdp_cycles_to_line(context, 0x1FF);
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3902 }
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3903
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3904 void vdp_pbc_pause(vdp_context *context)
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3905 {
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3906 context->flags2 |= FLAG2_PAUSE;
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3907 }
e587f16e7d3d Implemented SMS pause button
Michael Pavone <pavone@retrodev.com>
parents: 1371
diff changeset
3908
953
08346262990b Remove the int number argument to vdp_int_ack since it is no longer used
Michael Pavone <pavone@retrodev.com>
parents: 952
diff changeset
3909 void vdp_int_ack(vdp_context * context)
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3910 {
1160
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3911 //CPU interrupt acknowledge is only used in Mode 5
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3912 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3913 //Apparently the VDP interrupt controller is not very smart
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3914 //Instead of paying attention to what interrupt is being acknowledged it just
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3915 //clears the pending flag for whatever interrupt it is currently asserted
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3916 //which may be different from the interrupt it was asserting when the 68k
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3917 //started the interrupt process. The window for this is narrow and depends
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3918 //on the latency between the int enable register write and the interrupt being
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3919 //asserted, but Fatal Rewind depends on this due to some buggy code
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3920 if ((context->flags2 & FLAG2_VINT_PENDING) && (context->regs[REG_MODE_2] & BIT_VINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3921 context->flags2 &= ~FLAG2_VINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3922 } else if((context->flags2 & FLAG2_HINT_PENDING) && (context->regs[REG_MODE_1] & BIT_HINT_EN)) {
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3923 context->flags2 &= ~FLAG2_HINT_PENDING;
5f119fe935e7 Update H32 and Mode 4 mappings based on latest tests
Michael Pavone <pavone@retrodev.com>
parents: 1157
diff changeset
3924 }
317
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3925 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3926 }
e5e8b48ad157 Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents: 291
diff changeset
3927
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3928 void vdp_serialize(vdp_context *context, serialize_buffer *buf)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3929 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3930 save_int8(buf, VRAM_SIZE / 1024);//VRAM size in KB, needed for future proofing
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3931 save_buffer8(buf, context->vdpmem, VRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3932 save_buffer16(buf, context->cram, CRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3933 save_buffer16(buf, context->vsram, VSRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3934 save_buffer8(buf, context->sat_cache, SAT_CACHE_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3935 for (int i = 0; i <= REG_DMASRC_H; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3936 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3937 save_int8(buf, context->regs[i]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3938 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3939 save_int32(buf, context->address);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3940 save_int32(buf, context->serial_address);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3941 save_int8(buf, context->cd);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3942 uint8_t fifo_size;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3943 if (context->fifo_read < 0) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3944 fifo_size = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3945 } else if (context->fifo_write > context->fifo_read) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3946 fifo_size = context->fifo_write - context->fifo_read;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3947 } else {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3948 fifo_size = context->fifo_write + FIFO_SIZE - context->fifo_read;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3949 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3950 save_int8(buf, fifo_size);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3951 for (int i = 0, cur = context->fifo_read; i < fifo_size; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3952 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3953 fifo_entry *entry = context->fifo + cur;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3954 cur = (cur + 1) & (FIFO_SIZE - 1);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3955 save_int32(buf, entry->cycle);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3956 save_int32(buf, entry->address);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3957 save_int16(buf, entry->value);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3958 save_int8(buf, entry->cd);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3959 save_int8(buf, entry->partial);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3960 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3961 //FIXME: Flag bits should be rearranged for maximum correspondence to status reg
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3962 save_int16(buf, context->flags2 << 8 | context->flags);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3963 save_int32(buf, context->frame);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3964 save_int16(buf, context->vcounter);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3965 save_int8(buf, context->hslot);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3966 save_int16(buf, context->hv_latch);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3967 save_int8(buf, context->state);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3968 save_int16(buf, context->hscroll_a);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3969 save_int16(buf, context->hscroll_b);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3970 save_int16(buf, context->vscroll_latch[0]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3971 save_int16(buf, context->vscroll_latch[1]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3972 save_int16(buf, context->col_1);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3973 save_int16(buf, context->col_2);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3974 save_int16(buf, context->test_port);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3975 save_buffer8(buf, context->tmp_buf_a, SCROLL_BUFFER_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3976 save_buffer8(buf, context->tmp_buf_b, SCROLL_BUFFER_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3977 save_int8(buf, context->buf_a_off);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3978 save_int8(buf, context->buf_b_off);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3979 //FIXME: Sprite rendering state is currently a mess
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3980 save_int8(buf, context->sprite_index);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3981 save_int8(buf, context->sprite_draws);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3982 save_int8(buf, context->slot_counter);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3983 save_int8(buf, context->cur_slot);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3984 for (int i = 0; i < MAX_DRAWS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3985 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3986 sprite_draw *draw = context->sprite_draw_list + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3987 save_int16(buf, draw->address);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3988 save_int16(buf, draw->x_pos);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3989 save_int8(buf, draw->pal_priority);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3990 save_int8(buf, draw->h_flip);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3991 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3992 for (int i = 0; i < MAX_SPRITES_LINE; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3993 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3994 sprite_info *info = context->sprite_info_list + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3995 save_int8(buf, info->size);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3996 save_int8(buf, info->index);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3997 save_int16(buf, info->y);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3998 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
3999 save_buffer8(buf, context->linebuf, LINEBUF_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4000
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4001 save_int32(buf, context->cycles);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4002 save_int32(buf, context->pending_vint_start);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4003 save_int32(buf, context->pending_hint_start);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4004 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4005
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4006 void vdp_deserialize(deserialize_buffer *buf, void *vcontext)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4007 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4008 vdp_context *context = vcontext;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4009 uint8_t vramk = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4010 load_buffer8(buf, context->vdpmem, (vramk * 1024) <= VRAM_SIZE ? vramk * 1024 : VRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4011 if ((vramk * 1024) > VRAM_SIZE) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4012 buf->cur_pos += (vramk * 1024) - VRAM_SIZE;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4013 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4014 load_buffer16(buf, context->cram, CRAM_SIZE);
1431
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
4015 for (int i = 0; i < CRAM_SIZE; i++)
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
4016 {
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
4017 update_color_map(context, i, context->cram[i]);
030b40139de9 Update VDP color map when loading a native save state
Michael Pavone <pavone@retrodev.com>
parents: 1428
diff changeset
4018 }
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4019 load_buffer16(buf, context->vsram, VSRAM_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4020 load_buffer8(buf, context->sat_cache, SAT_CACHE_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4021 for (int i = 0; i <= REG_DMASRC_H; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4022 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4023 context->regs[i] = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4024 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4025 context->address = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4026 context->serial_address = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4027 context->cd = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4028 uint8_t fifo_size = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4029 if (fifo_size > FIFO_SIZE) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4030 fatal_error("Invalid fifo size %d", fifo_size);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4031 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4032 if (fifo_size) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4033 context->fifo_read = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4034 context->fifo_write = fifo_size & (FIFO_SIZE - 1);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4035 for (int i = 0; i < fifo_size; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4036 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4037 fifo_entry *entry = context->fifo + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4038 entry->cycle = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4039 entry->address = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4040 entry->value = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4041 entry->cd = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4042 entry->partial = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4043 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4044 } else {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4045 context->fifo_read = -1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4046 context->fifo_write = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4047 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4048 uint16_t flags = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4049 context->flags2 = flags >> 8;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4050 context->flags = flags;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4051 context->frame = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4052 context->vcounter = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4053 context->hslot = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4054 context->hv_latch = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4055 context->state = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4056 context->hscroll_a = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4057 context->hscroll_b = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4058 context->vscroll_latch[0] = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4059 context->vscroll_latch[1] = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4060 context->col_1 = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4061 context->col_2 = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4062 context->test_port = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4063 load_buffer8(buf, context->tmp_buf_a, SCROLL_BUFFER_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4064 load_buffer8(buf, context->tmp_buf_b, SCROLL_BUFFER_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4065 context->buf_a_off = load_int8(buf) & SCROLL_BUFFER_MASK;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4066 context->buf_b_off = load_int8(buf) & SCROLL_BUFFER_MASK;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4067 context->sprite_index = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4068 context->sprite_draws = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4069 context->slot_counter = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4070 context->cur_slot = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4071 for (int i = 0; i < MAX_DRAWS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4072 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4073 sprite_draw *draw = context->sprite_draw_list + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4074 draw->address = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4075 draw->x_pos = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4076 draw->pal_priority = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4077 draw->h_flip = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4078 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4079 for (int i = 0; i < MAX_SPRITES_LINE; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4080 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4081 sprite_info *info = context->sprite_info_list + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4082 info->size = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4083 info->index = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4084 info->y = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4085 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4086 load_buffer8(buf, context->linebuf, LINEBUF_SIZE);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4087
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4088 context->cycles = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4089 context->pending_vint_start = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4090 context->pending_hint_start = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4091 update_video_params(context);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1422
diff changeset
4092 }
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4093
1649
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4094 static vdp_context *current_vdp;
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4095 static void vdp_debug_window_close(uint8_t which)
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4096 {
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4097 //TODO: remove need for current_vdp global, and find the VDP via current_system instead
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4098 for (int i = 0; i < VDP_NUM_DEBUG_TYPES; i++)
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4099 {
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4100 if (current_vdp->enabled_debuggers & (1 << i) && which == current_vdp->debug_fb_indices[i]) {
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4101 vdp_toggle_debug_view(current_vdp, i);
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4102 break;
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4103 }
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4104 }
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4105 }
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4106
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4107 void vdp_toggle_debug_view(vdp_context *context, uint8_t debug_type)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4108 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4109 if (context->enabled_debuggers & 1 << debug_type) {
1642
c6b2c0f8cc61 Implemented support for toggling off a debug view
Michael Pavone <pavone@retrodev.com>
parents: 1641
diff changeset
4110 render_destroy_window(context->debug_fb_indices[debug_type]);
c6b2c0f8cc61 Implemented support for toggling off a debug view
Michael Pavone <pavone@retrodev.com>
parents: 1641
diff changeset
4111 context->enabled_debuggers &= ~(1 << debug_type);
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4112 } else {
1634
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4113 uint32_t width,height;
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4114 uint8_t fetch_immediately = 0;
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4115 char *caption;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4116 switch(debug_type)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4117 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4118 case VDP_DEBUG_PLANE:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4119 caption = "BlastEm - VDP Plane Debugger";
1634
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4120 width = height = 1024;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4121 break;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4122 case VDP_DEBUG_VRAM:
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4123 caption = "BlastEm - VDP VRAM Debugger";
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4124 width = 1024;
e397766c3028 Added VRAM debug window
Michael Pavone <pavone@retrodev.com>
parents: 1632
diff changeset
4125 height = 512;
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4126 break;
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4127 case VDP_DEBUG_CRAM:
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4128 caption = "BlastEm - VDP CRAM Debugger";
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4129 width = 512;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4130 height = 512;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4131 fetch_immediately = 1;
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4132 break;
1641
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4133 case VDP_DEBUG_COMPOSITE:
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4134 caption = "BlastEm - VDP Plane Composition Debugger";
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4135 width = LINEBUF_SIZE;
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4136 height = context->inactive_start + context->border_top + context->border_bot;
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4137 fetch_immediately = 1;
bc9bb4e5856f Basic version of layer compositing debug view in a separate window
Michael Pavone <pavone@retrodev.com>
parents: 1640
diff changeset
4138 break;
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4139 default:
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4140 return;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4141 }
1649
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4142 current_vdp = context;
b500e971da75 Allow closing VDP debug windows with the close button in the window title bar
Michael Pavone <pavone@retrodev.com>
parents: 1644
diff changeset
4143 context->debug_fb_indices[debug_type] = render_create_window(caption, width, height, vdp_debug_window_close);
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4144 if (context->debug_fb_indices[debug_type]) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4145 context->enabled_debuggers |= 1 << debug_type;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4146 }
1638
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4147 if (fetch_immediately) {
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4148 context->debug_fbs[debug_type] = render_get_framebuffer(context->debug_fb_indices[debug_type], &context->debug_fb_pitch[debug_type]);
f27142c48567 Initial stab at CRAM debug in a detached window
Michael Pavone <pavone@retrodev.com>
parents: 1637
diff changeset
4149 }
1631
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4150 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4151 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4152
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4153 void vdp_inc_debug_mode(vdp_context *context)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4154 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4155 uint8_t active = render_get_active_framebuffer();
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4156 if (active < FRAMEBUFFER_USER_START) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4157 return;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4158 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4159 for (int i = 0; i < VDP_NUM_DEBUG_TYPES; i++)
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4160 {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4161 if (context->enabled_debuggers & (1 << i) && context->debug_fb_indices[i] == active) {
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4162 context->debug_modes[i]++;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4163 return;
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4164 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4165 }
c4ba3177b72d WIP new VDP plane debug view and support for detached VDP debug views generally
Michael Pavone <pavone@retrodev.com>
parents: 1629
diff changeset
4166 }